16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 192

Mitigation of Various Power Quality Problems Using

Unified Series Shunt Compensator in PSCAD/EMTDC
S. Asha Kiranmai M.Manjula A.V.R.S.Sarma
Assistant Professor Associate Professor Professor
Department of Electrical & Department of Electrical Department of Electrical
Electronics Engineering Engineering Engineering
Bhoj Reddy Engineering College University College of Engineering University College of Engineering
for Women, Hyderabad-059, India Osmania University, Hyderabad-7 Osmania University, Hyderabad-7
e-mail:asha_ks2006@yahoo.co.in e-mail:manjulamane04@yahoo.com e-mail:avrs2000@yahoo.com

Abstract—Power quality in the distribution system is the such as Unified Power Flow Controller (UPFC), Synchronous
important issue for industrial, commercial and residential Static Compensator (STATCOM), Dynamic Voltage Restorer
applications. An increasing demand for high quality, reliable (DVR), solid-state transfer switch, and solid-state fault current
electrical power and an increasing number of distorting loads limiter are developed for improving power quality and
have led an increased awareness of power quality both by reliability of a system [3], [4]. Advanced control and improved
customers and utilities. This paper deals with the simulation of a semiconductor switching of these devices have achieved a new
Unified Series Shunt Compensator (USSC), which is aimed at era for power-quality mitigation.
mitigating most of the Power Quality problems such as,
(i) Voltage Sag compensation, (ii) Voltage Swell compensation, Investigations have been carried out to study the
(iii) Voltage Flicker reduction, (iv) Voltage Unbalance mitigation effectiveness of these devices in power-quality mitigation such
(v) UPS mode of operation and (vi) Harmonics elimination. as sag compensation, harmonics elimination, unbalance
The modeling and simulation of the USSC has been carried out by compensation, reactive power compensation, power-flow
using Power Systems Computer Aided Design (PSCAD) software. control, power factor correction and flicker reduction [5] – [11].
The USSC simulation model comprises of two 12-pulse inverters These devices have been developed for mitigating specific
which are connected in series and in shunt to the system. power-quality problems. For example, UPFC works well for
A generalized sinusoidal pulse width modulation switching power-flow control. DVR, which acts as a series compensator,
technique has been developed in the proposed controller design is used for voltage sag compensation. STATCOM, which is a
for fast control action of the USSC. The USSC has mitigated
shunt compensator, is used for reactive power and voltage sag
several Power Quality problems giving better performance.
compensation.
Keywords-12-pulse inverters, GTO switches, Power quality, The STATCOM and DVR are only useful for compensating
PWM technique, Unified Series Shunt Compensator. a particular type of power-quality problem and therefore, it is
necessary to develop a new kind of unified series-shunt
I. INTRODUCTION compensator (USSC) which can mitigate various power-quality
Now a days, the high quality of electric power has become problems [12], [13]. By using a unified approach of series-shunt
very much importance to electric utilities and for customers. compensators, it is possible to compensate for a variety of
Utility and customer-side disturbances result in terminal voltage power-quality problems in a distribution system including
fluctuations, transients, and waveform distortions on the electric voltage sag compensation, swell compensation, unbalance
grid resulting in power quality problems. Power Quality is voltage mitigation and flicker reduction. This paper deals with
mainly affected by the increased use of non-linear loads such as the modeling and simulation of Unified Series Shunt
power electronic equipment, variable speed drives, electronic Compensator and it’s effectiveness in mitigating various power
control gears etc. Poor power quality can affect the safe, reliable quality problems. The simulations are carried out by using
and efficient operation of the equipment. Various aspects of Power Systems Computer Aided Design (PSCAD), the most
power quality are voltage sag, voltage swell, voltage powerful and intuitive CAD software.
fluctuations, voltage unbalance, harmonics etc [1], [2]. The section-II gives the basic configuration of Unified
For power-quality improvement, the development of power Series Shunt Compensator used for the study. The section III
electronic devices such as Flexible AC Transmission Systems deals with the principle operation of USSC. The section IV
(FACTS) and custom power devices have introduced an gives the simulation circuit diagram of USSC which is
emerging branch of technology providing the power system developed in PSCAD. The section V describes the shunt and
with versatile new control capabilities [3], [4]. In general, series controllers of USSC. The section VI gives the simulation
FACTS devices are used in transmission control whereas results obtained by operating USSC under voltage sag, voltage
custom power devices are used for distribution control. Since swell, voltage unbalance, voltage flicker, and UPS mode.
the introduction of FACTS and custom power concept, devices The harmonic elimination of USSC is also presented.

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 16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 193

II. BASIC CONFIGURATION OF USSC

The Unified Series Shunt Compensator is a combination of
series and shunt voltage source inverters as shown in Fig. 1.
The basic components of the USSC are two 12-pulse voltage
source inverters composed of forced commutated power
semiconductor switches, typically Gate Turn Off (GTO)
thyristor valves. One voltage source inverter is connected in
series with the line through a set of series injection
transformers, while the other is connected in shunt with the line
through a set of shunt transformers. The dc terminals of the two
inverters are connected together and their common dc voltage is
supported by a capacitor bank. Fig. 2. Principle Operation of USSC

connection. Thus, USSC includes the functions of both series

and shunt connected inverters which generates or absorbs
reactive power to regulate voltage magnitude and current flow
at the ac terminal, respectively.

IV. SIMULATION CIRCUIT DIAGRAM OF USSC

DEVELOPED IN PSCAD
The simulation circuit diagram of USSC which has been
developed to mitigate various power quality problems is shown
in Fig. 3. It consists of 22 kV distribution system having a static
load of 5.2 MVA with USSC connected.
The USSC consist of two 12-pulse inverters in which one is
connected in series and the other in shunt. The shunt connected
Fig. 1. Basic Configuration of USSC
inverter is connected to the line by means of two sets of three
single- phase transformers which are of Y-Y and Y-Δ
III. PRINCIPLE OPERATION OF USSC configurations to avoid phase shift of other than the order of
The principle operation of a USSC is described by referring 12n  1 harmonics in the secondary of the transformers, which
to the model shown in Fig. 2. The series connected inverter may result in large circulating current due to common core of
injects a voltage Vdq in series with the distribution line, which in flux. However, the series connected inverter is connected to the
turn changes the voltage VL across the distribution line, hence line by means of two sets of three single-phase transformers
changing the current and the power flow through the which are of Y-Δ configuration. This is because, usually
distribution line. The exchange of real power Pinv and reactive Y-connected secondary windings allow only the injection of
power Qinv can be written in terms of phase angle Φ (the angle positive and negative sequence voltages. The delta connection
between the injected voltage Vdq and the line current IL), prevents zero sequence currents entering into the system from
the injected voltage Vdq and the line current I, as the inverter. The primary windings of all the single-phase
transformers are connected in series in order to avoid harmonic
Pinv Vdq IL cosφ  circulating current. The leakage reactance of all the
transformers is kept low so as to prevent a large voltage drop.
Qinv Vdq IL sinφ  The 22/4.16-kV step-down transformers with a leakage
The current injected by the shunt inverter has a real or direct reactance of 0.01 per unit are considered. The capacitor plays an
component Id, which can be in phase or in opposite phase with important role in the USSC operation by acting as a dc source to
the line and a reactive or quadrature component Iq, which is in provide reactive power to the load and to regulate the dc
quadrature with the line voltage, thereby emulating an inductive voltage. The size of the dc capacitor considered in this
or a capacitive reactance at the point of connection with the simulation is 3340 µF [13].
distribution line. The reactive current can be independently
controlled which in turn will regulate the line voltage. V. CONTROL SYSTEM OF USSC
The USSC behaves as an ideal ac-to-ac inverter, in which The control system of the USSC consists of a shunt inverter
the exchange of real power at the terminal of one inverter to the controller and a series inverter controller. The shunt inverter
terminal of the other inverter is through the common dc link controller controls the current injected into the line and whereas
capacitor. The shunt inverter is controlled in such a way as to the series controller controls the series voltage injected into the
provide precisely the right amount of real power at its dc line. When the series and the shunt connected inverters operate
terminal to meet the real power needs of the series inverter and as stand-alone devices, they exchange almost exclusively
to regulate the dc voltage of the dc bus. Thus, real power is reactive power at their terminals. The series connected inverter
absorbed from or delivered to the distribution line through the injects a voltage in quadrature with the line current thereby
shunt connected inverter, which injects a current at the point of emulating an inductive or a capacitive reactance in series with

Department of Electrical Engineering, Univ. College of Engg., Osmania University, Hyderabad, A.P, INDIA.
 16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 194

Fig. 3. Simulation circuit diagram of USSC

Fig. 4. Simplified block diagram of Shunt Inverter Control System
the line. The shunt connected inverter injects a reactive current,
thereby also emulating a reactance at the point of connection.
While operating both series and shunt-connected inverters B. Series Inverter Controller of USSC
together as a USSC, the series injected voltage can be at any In the series inverter, the SPWM technique is also used to
angle with respect to the line current. The exchange of real control the magnitude and phase of the ac voltage by
power flow can be between the terminals of series and shunt synchronizing the GTO’s switching to the ac system voltages.
connected inverters through the common dc link capacitor. The control for the series inverter is almost similar to that of the
shunt inverter, but the only difference is that, the measured
A. Shunt Inverter Controller of USSC phase currents are input to the PLL. The series inverter injected
voltages are kept in quadrature with the line currents to provide
The controller of a shunt inverter is used to operate the
series compensation, whereas in the shunt inverter injected
voltage source inverter such a way that the phase angle between
currents are kept in quadrature with the line voltage.
the inverter voltage and the line voltage is dramatically adjusted
so that the shunt inverter generates or absorbs reactive power at
the point of connection of the system. Fig. 4 shows the VI. SIMULATION RESULTS
simplified block diagram of shunt inverter control system using Simulations were carried out on USSC to illustrate it’s
Sinusoidal Pulse Width Modulated (SPWM) switching. effectiveness in compensation for voltage sag, voltage swell,
The measured three-phase voltages are fed to the voltage unbalance, voltage flicker, and UPS mode of operation.
Phase Locked Loop (PLL1), which provides the voltage The harmonic elimination of USSC is also presented.
synchronizing signal with an angle θ. The reference and
measured voltages are compared and processed through lag-lead A. Voltage Sag Compensation
network and PI controller to generate angle order δ which is Voltage sag condition is simulated by creating a balanced
combined with θ to generate voltage modulating signal. three phase to ground fault at time t = 1 s for a duration of
The Phase Locked Loop (PLL2), also provides a voltage 0.75 s. For the system without the USSC, the load voltage drops
synchronizing signal which is multiplied by a carrier frequency from 0.9 p.u. to 0.5 p.u., as shown in Fig. 5(a). For the system
of 1.65 kHz and is passed through non-linear block to generate with the USSC connected, the load voltage increases from 0.50
triangular carrier signal. In the SPWM technique, the triangular to 1.0 p.u., as shown in Fig. 5(b). The minimum and maximum
carrier signal is compared with the voltage-modulating signal so voltage values obtained at the starting and ending of voltage sag
as to obtain the firing signals of the GTOs. The zero crossings are 0.91 and 1.1 p.u., respectively. Thus it can be seen from the
of the voltage ramps fire/block the GTOs, depending on the simulation results that the USSC show a better voltage sag
displacement angle δ. If δ = 0, the shunt inverter output voltage compensation capability in terms of the voltage magnitudes.
is said to be in phase with the ac system voltage. However, if
there is an error between the reference voltage and the system B. Voltage Swell Compensation
voltage in per unit, that is, Vp.u < Vref, then the displacement Voltage swell is generated by connecting a capacitive load
angle δ > 0 and the shunt inverter voltage lags behind the ac to the line by switching on the breaker at time t = 1 s and is
system voltage thus causing real power flow into the shunt switched off at time t = 1.75 s. For the system without the
inverter. Consequently, the dc capacitor voltage will increase, USSC, the load voltage increases from 0.9 to 1.3 p.u. due to the
thus causing an increase in the ac output voltage of the shunt energization of the capacitor, as shown in Fig. 6(a). For the
inverter. The increase in ac output voltage causes a reduction in system with the USSC connected, the load voltage is decreased
the error voltage until Vp.u = Vref. If Vp.u > Vref, then the from 1.3 p.u. to the rated value 1.0 p.u., as shown in Fig. 6(b).
displacement angle δ < 0 and the shunt inverter voltage leads The minimum and maximum voltages values at the starting and
the ac voltage thus causing real power flow into the system. ending of voltage swell are 0.94 p.u. and 1.07 p.u., respectively.
Consequently, the dc capacitor voltage will decrease, thus Thus it can be seen from the simulation results that the USSC
causing a decrease in the ac output voltage of the shunt inverter show a better voltage swell compensation capability in terms of
and a reduction in the error voltage until Vp.u = Vref. the voltage magnitudes.

Department of Electrical Engineering, Univ. College of Engg., Osmania University, Hyderabad, A.P, INDIA.
 16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 195

the USSC, the load voltage profile has improved and

the percentage of voltage unbalance decreases from 16.94 % to
1.48 %.

Fig. 5(a). Load Voltage during Voltage Sag without USSC

Fig. 7(a). Three Phase Load Voltages during Voltage Unbalance caused
by LG fault without USSC connected

Fig. 5(b). Load Voltage during Voltage Sag with USSC

Fig. 7(b). Three Phase Load Voltages during Voltage Unbalance caused
by LG fault with USSC connected

Fig. 6(a). Load Voltage during Voltage Swell without USSC (ii) Two LG faults: Two single phase to ground faults of
different severity on the phases A and C are applied at time
t = 1 s for a fault duration of 100 ms. Fig. 8(a) shows the
simulation results of the three-phase unbalanced voltages for the
system without the USSC connected. It can be seen that during
the fault condition, the maximum phase voltages are,
VAmax=12.25 kV, VBmax=16 kV and VCmax=9.5 kV.
The percentage of voltage unbalance is 27.15 %. This value
indicates that the voltage unbalance is severe during the fault
because the limit of the voltage unbalance is specified as 2%.
Fig. 6(b). Load Voltage during Voltage Swell with USSC

C. Voltage Unbalance Mitigation

The effect of voltage unbalance is detrimental as it causes
heating in motors, thus requiring them to be derated. Unbalance
can also affect sensitive single phase loads because it creates
under voltage in one or more of the lines. Therefore, it is
important to investigate on whether the USSC can mitigate
voltage unbalance. Unbalanced voltage conditions are created Fig. 8(a). Three Phase Load Voltages during Voltage Unbalance caused
by applying a single LG fault and two LG faults. by two LG faults without USSC connected
(i) Single LG fault: A Single phase to ground fault on the
phase A is created at time t = 1 s for a fault duration of 100 ms.
Fig. 7(a) shows the simulation results of the three-phase
unbalanced voltages for the system without the USSC
connected. It can be seen that during the fault condition, the
maximum phase voltages are, VAmax=12.25 kV, VBmax=16 kV
and VCmax=16 kV. The percentage of voltage unbalance is
16.94%. This value is above the voltage unbalance limit of 2%.
With the USSC connected in the system, the three-phase load
voltages are obtained as shown in Fig. 7(b) with the maximum
Fig. 8(b). Three Phase Load Voltages during Voltage Unbalance caused
phase voltages of, VAmax=17.7 kV, VBmax=18.2 kV and
by two LG faults with USSC connected
VCmax=18 kV. It is evident from Fig. 7(b) that in the presence of

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 16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 196

With the USSC connected in the system, the three-phase When the USSC is connected in the system, the USSC
load voltages are obtained as shown in Fig. 8(b) and the recovers the load voltage from 0.0 to 1.0 p.u. within a short time
maximum phase voltages are, VAmax= 18.13 kV, VBmax=18.5 kV as shown in Fig. 10(b). In the UPS mode, both the series and
and VCmax= 17.8 kV. It is evident from Fig. 8(b) that in the shunt inverters of the USSC operate in parallel and support a
presence of the USSC, the load voltage profile has improved in load of the sum of the inverters rating.
which the phase A and C voltages are increased and the phase B
voltage is reduced, thus making the three phase voltages more
balanced. The percentage of voltage unbalance decreases from
27.15 % to 1.892%.

D. Voltage Flicker Reduction

Voltage flicker is a phenomenon of annoying light intensity
fluctuation caused by variable electric loads and arc furnaces
have been a major power-quality concern. To illustrate the use Fig. 10(a). Load Voltage during Outage without USSC
of the USSC in reducing voltage flicker, simulations were
carried out by connecting a variable electric load of 5.2 MVA,
22 kV as the source of voltage flicker.
Fig. 9(a) shows the flicker effect of a phase A voltage for
the system without the USSC connected. By connecting the
USSC, it can be seen that the voltage of phase A is flicker free,
as shown in Fig. 9(b). The results shown here are for the phase
A voltage but however the responses are similar for the phase B
and phase C voltages. Fig. 10(b). Load Voltage during Outage with USSC
The simulation results show that without the USSC
connected, the effect of the variable electric load results in a F. Harmonic Elimination of USSC
voltage flicker index of 0.321 in which the value exceeds its
Due to high frequency switching losses, the inverters have
IEEE SCC22 standard limit of 0.07. However, with the USSC
generated a voltage Total Harmonic Distortion (THD) of about
connected, it is noted that the calculated voltage flicker index is
in the range of 45% to 60% as shown in Fig. 11(a). This value is
reduced to 0.013.
higher than the acceptable level of 5%. Therefore, an
inductance-capacitance (LC) passive filter is connected at the
load side of distribution system in order to eliminate harmonics.
The filter parameters used are L = 0.1 mH and C = 25 µF.
Simulations were carried out and the THD of the system
without and with the filter inserted into the system recorded are
as shown in Fig. 11(a) and 11(b), respectively.

Fig. 9(a). Load Voltage during Voltage Flicker without USSC

Fig. 11(a). Total Harmonic Distortion without Filter

Fig. 9(b). Load Voltage during Voltage Flicker with USSC

E. UPS Mode of Operation

To operate the USSC in Uninterruptible Power Supply
(UPS) mode, an outage is first created by applying a three phase
fault at time t = 1 s for a duration of 0.75 s. A DC source is Fig. 11(b). Total Harmonic Distortion with Filter
connected to the common DC bus to function as an energy
source for UPS operation to supply real power to the load. From the simulation results, it can be seen that with the filter
The outage simulation result is as shown in Fig. 10(a). connected, the harmonics are suppressed and the THD of the

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 16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 197

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Department of Electrical Engineering, Univ. College of Engg., Osmania University, Hyderabad, A.P, INDIA.