#include "spi_tst_drv.

h"
#include "evalsoc.h"
#include "system_arcs.h"
#include <stdio.h>

int main(void) {
unsigned int rdata ;
char data_tmp[16];

unsigned int iocfg;

#ifdef SDIO_PINMUX1
iocfg = 1;
#else
#ifdef SDIO_PINMUX2
iocfg = 2;
#else
#ifdef SDIO_PINMUX3
iocfg = 3;
#else
#ifdef SDIO_PINMUX4
iocfg = 4;
#else
#ifdef SDIO_PINMUX5
iocfg = 5;
#else
#ifdef SDIO_PINMUX6
iocfg = 6;
#else
iocfg = 1;
#endif //SDIO_PINMUX6
#endif //SDIO_PINMUX5
#endif //SDIO_PINMUX4
#endif //SDIO_PINMUX3
#endif //SDIO_PINMUX2
#endif //SDIO_PINMUX1
sdio_common(iocfg);
CMN_SYS_NDFT->REG_SYSPLL_CFG.bit.SYSPLL_ENABLE = 0x1;
CMN_SYS_NDFT->REG_PERI_CLK_CFG4.bit.ENA_SMID_CLK =0x1; // enable sdiod

CMN_SYS_NDFT->REG_SYSPLL_CTRL.bit.SYSPLL_POSTDIV_PERI_DIV_SEL =0x0; //
enable sdiod
ECLIC_EnableIRQ(SDIOH_IRQn);
ECLIC_EnableIRQ(SDIOD_IRQn);
print("Hello, I am CoreA!\n");

/**************************************************************************/
/*****************************CONFIG FLOW**********************************/
/**************************************************************************/
//config sdio device
SDIOD->REG_SMID_CARD_RDY.bit.FUNCTION1_READY = 0x1; //enable io1
SDIOD->REG_SMID_CARD_RDY.bit.FUNCTION2_READY = 0x1; //enable io2
SDIOH->REG_VR1.bit.LO_SD_RSTN = 0x1; // Release Reset signal
//Config sdio host
SDIOH->REG_CCR_TCR_SRR.bit.INTER_CLK_EN = 0x1;
print("Delay\n");
SDIOH->REG_CCR_TCR_SRR.bit.LOW_BIT_SD_CLK_SEL = 0x3;
SDIOH->REG_CCR_TCR_SRR.bit.LOW_BIT_SD_CLK_SEL = 0x0;
 do {
rdata = SDIOH->REG_CCR_TCR_SRR.bit.CLK_STABLE;
} while(rdata == 0x0);
SDIOH->REG_CCR_TCR_SRR.bit.SD_CLK_EN = 0x1;
SDIOH->REG_HC1_PCR_BGCR.bit.SD_BUS_POW = 0x1; // Set SD power enable
SDIOH->REG_HC1_PCR_BGCR.bit.SD_BUS_VOL = 0x3; // Set SD power enable
//SDIOH->REG_VR1.bit.LO_SD_RSTN = 0x1; // Release Reset signal

//---- Set Interrupt Status Enable and Signal Enable ----//

SDIOH->REG_NISER_EISER.all = 0x03ff01ff; // Set Status enable reg

SDIOH->REG_NISEN_EISEN.all = 0x03ff01cf; // Set Signal enable reg

//---- Determine the SD Data width, Data FIFO type and Size fifo_size=128Word
----//
print("Determine the SD Data Width\n");

rdata = SDIOH->REG_HWA.bit.HW_CONFIG;
if ((rdata & 0x80) == 0) {
print(" Use 4 bits SD Data Width\n");
//---- Change Bus Width ----//
SDIOH->REG_HC1_PCR_BGCR.bit.DATA_WIDTH = 0x1; // Set bus width to 4bit and high
speed enable
SDIOH->REG_HC1_PCR_BGCR.bit.HI_SPEED = 0x1;

//---- Set DDR mode ----//

SDIOH->REG_AC12ES_HC2.bit.UHS_MODE_SEL = 0x1; // Set to SDR25
}

SDIOH->REG_ARG1.all = 0xff8000;
SDIOH->REG_TMR_CR.all = 0x05020000; // CMD5 issue
__WFI();

rdata = SDIOH->REG_RESP0.all ;
printf("CMD5 response=0x%x\n",rdata);
SDIOH->REG_ARG1.all = 0x0;
SDIOH->REG_TMR_CR.all = 0x03120000; // CMD3 issue get rca
__WFI();

rdata = SDIOH->REG_RESP0.all ;
printf("CMD3 response=0x%x\n",rdata);
SDIOH->REG_ARG1.all = rdata; // It's device rca addr
SDIOH->REG_TMR_CR.all = 0x07120000; // CMD7 issue
__WFI();
SDIOH->REG_ARG1.all = 0x800004fe;
SDIOH->REG_TMR_CR.all = 0x341a0000; // CMD52 issue
__WFI();
SDIOH->REG_ARG1.all = 0x80022080; //function 1 ; block size 0x80(128B)
SDIOH->REG_TMR_CR.all = 0x341a0000; // CMD52 issue
__WFI();
SDIOH->REG_ARG1.all = 0x80000e82; //bus width = 4 bits
SDIOH->REG_TMR_CR.all = 0x341a0000; // CMD52 issue
__WFI();

/**************************************************************************/
/*****************************WRITE FLOW***********************************/
/**************************************************************************/
//Use 1K bytes SRAM for dtat FIFO (128x64);
 //---- Multi block write ----//
//Set block size 512B
print("set_blocklen_cmd53\n");
SDIOH->REG_BSR_BCR.bit.BLK_SIZE_R = 0x80;
SDIOH->REG_BSR_BCR.bit.BLK_CNT_R = 0x4; //4 block
rdata = SDIOH->REG_PSR.all;
while((rdata & 0x1) != 0) {
rdata = SDIOH->REG_PSR.all;
}
//SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_ADDRESS_VALID = 0x1;
//SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_BUFFER_SIZE = 0x80;
//SDIOD->REG_SMID_DMA1_ADDR.all = DATA_BASE;
SDIOH->REG_ARG1.all = 0x9c002004; //block size 0x80, block count : 4

SDIOH->REG_TMR_CR.all = 0x353a0022; // Cmd53 issue

__WFI();

for(int k=0 ; k<4; k++) {

rdata = SDIOH->REG_NISR_EISR.bit.BUF_W_RDY_R;
while(rdata == 0) {
rdata = SDIOH->REG_NISR_EISR.bit.BUF_W_RDY_R;
}
SDIOH->REG_NISR_EISR.bit.BUF_W_RDY_R = 1; // Clear buffer write ready
interrupt
printf("k=%x write complete\n",k);
for (int i=0;i<32;i=i+1) {
SDIOH->REG_BDP.all = 0x12a45800 + k*32+i;
//printf("write complete k=%x, i=%x\n",k,i);
}
}
while(rdata != 0) {
rdata = SDIOH->REG_BSR_BCR.bit.BLK_CNT_R;
printf("wait blk cnt to 0 %x\n", rdata);
}

///**************************************************************************/
///*****************************READ FLOW************************************/
///**************************************************************************/
printf("start read operation");

//read back one block data

SDIOH->REG_BSR_BCR.bit.BLK_CNT_R = 0x4; //3 block
rdata = SDIOH->REG_PSR.all;
while((rdata & 0x3) != 0x0) {
rdata = SDIOH->REG_PSR.all;
printf("waiting for PSR %x\n",rdata);
}
//SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_BUFFER_SIZE = 0x80;
//SDIOD->REG_SMID_DMA1_ADDR.all = DATA_BASE;
SDIOH->REG_ARG1.all = 0x1c012004; //block size 0x80, block count : 2

SDIOH->REG_TMR_CR.all = 0x353a0032; // Cmd53 issue

 __WFI();

print("wait buffer read ready\n");

for(int k=0 ; k<4; k++) {
rdata = SDIOH->REG_NISR_EISR.bit.BUF_R_RDY_R;
while(rdata == 0) {
rdata = SDIOH->REG_NISR_EISR.bit.BUF_R_RDY_R;
}
SDIOH->REG_NISR_EISR.bit.BUF_R_RDY_R = 1; // Clear buffer read ready
interrupt

for (int i=0;i<32;i=i+1) {

rdata = SDIOH->REG_BDP.all;
if(rdata != (0x12a45800 + k*32+i)) {
printf("ERROR: k=%0d, i=%0d, rdata=0x%0x, exp=0x%x\n",k,i,rdata,
(0x12a45800 + k*32+i));
c_fail();
} else {
//printf("rdata[%0x]=0x%0x\n",k*32+i,rdata);
}
}
}

c_pass();
return 0;
}
//Interrupt Handler
__INTERRUPT void eclic_sdioh_int_handler (void) {
unsigned int rdata ;
rdata = SDIOH->REG_NISR_EISR.all;
printf("aaaaaaaaaaaaaaaaaaaaaa SDIO Intr = 0x%x\n", rdata);
if((rdata & 0x1)== 0x1) {
print("CMD Done\n");
SDIOH->REG_NISR_EISR.all = 0x1; // Clear cmd complete interrupt
}
if((rdata & 0x2)== 0x2) {
print("Tran complete\n");
SDIOH->REG_NISR_EISR.all = 0x2; // Clear transfer complete interrupt
}
if((rdata & 0x100)== 0x100) {
print("Tran complete 100 \n");
SDIOH->REG_NISER_EISER.bit.CARD_INT_ST_EN = 0x0; // Clear transfer complete
interrupt
}
}

__INTERRUPT void eclic_sdiod_int_handler (void) {

unsigned int rdata ;
rdata = SDIOD->REG_SMID_INT_STAT.all;
printf("aaaaaaaaaaaaaaaaaaaaaa SDIO Device Intr = 0x%x\n", rdata);
if((rdata & 0x40000000)== 0x40000000) {
print("LRST Done\n");
SDIOD->REG_SMID_INT_STAT_EN.bit.LRST_INTERRUPT = 0x0;
SDIOD->REG_SMID_INT_STAT.bit.LRST_INTERRUPT = 0x1;
}
if((rdata & 0x2000000)== 0x2000000) {
 print("programed Done\n");
SDIOD->REG_SMID_INT_STAT.bit.PROGRAM_START = 0x1;
}
if((rdata & 0x00000008)== 0x00000008) {
print("A write operation is coming \n");
SDIOD->REG_SMID_INT_STAT.bit.WRITE_START_INTERRUPT = 0x1;
//config DMA reg
SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_BUFFER_SIZE = 0x0;
SDIOD->REG_SMID_DMA1_ADDR.all = DATA_BASE;
SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_ADDRESS_VALID = 0x1;

}
if((rdata & 0x00000010)== 0x00000010) {
print("A read operation is coming \n");
SDIOD->REG_SMID_INT_STAT.bit.READ_START_INTERRUPT = 0x1;
//config DMA reg
SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_BUFFER_SIZE = 0x0;
SDIOD->REG_SMID_DMA1_ADDR.all = DATA_BASE;
SDIOD->REG_SMID_DMA1_CTRL.bit.DMA1_ADDRESS_VALID = 0x1;
}
if((rdata & 0x00000001)== 0x00000001) {
print("A trans completed\n");
SDIOD->REG_SMID_CONTROL_REG.bit.PROGRAM_DONE = 0x1;
SDIOD->REG_SMID_INT_STAT.bit.TRANSFER_COMPLETE_INTERRUPT = 0x1;
}
}