ST10F272

16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

Features
■ 16-bit CPU with DSP functions
– 31.25ns instruction cycle time at 64MHz
max CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator PQFP144 (28 x 28 x 3.4mm) LQFP144 (20 x 20 x 1.4mm)
(Plastic Quad Flat Package) (Low Profile Quad Flat Package)
– Enhanced boolean bit manipulations
– Single-cycle context switching support ■ A/D converter
■ On-chip memories – 24-channel 10-bit
– 256 Kbyte Flash memory (32-bit fetch) – 3 µs minimum conversion time
– Single voltage Flash memories with ■ Serial channels
erase/program controller and 100K – Two synch. / asynch. serial channels
erasing/programming cycles.
– Two high-speed synchronous channels
– Up to 16 Mbyte linear address space for
– One I2C standard interface
code and data (5 Mbytes with CAN or I2C)
■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN
– 2 Kbyte internal RAM (IRAM)
busses (64 or 2x32 message, C-CAN version)
– 18 Kbyte extension RAM (XRAM)
■ Fail-safe protection
– Programmable external bus configuration &
characteristics for different address ranges – Programmable watchdog timer
– Five programmable chip-select signals – Oscillator watchdog
– Hold-acknowledge bus arbitration support ■ On-chip bootstrap loader
■ Interrupt ■ Clock generation
– 8-channel peripheral event controller for – On-chip PLL with 4 to 8 MHz oscillator
single cycle interrupt driven data transfer – Direct or prescaled clock input
– 16-priority-level interrupt system with 56 ■ Real time clock and 32 kHz on-chip oscillator
sources, sampling rate down to 15.6ns
■ Up to 111 general purpose I/O lines
■ Timers
– Individually programmable as input, output
– Two multi-functional general purpose timer or special function
units with 5 timers
– Programmable threshold (hysteresis)
■ Two 16-channel capture / compare units
■ Idle, power down and stand-by modes
■ 4-channel PWM unit + 4-channel XPWM
■ Single voltage supply: 5V ±10%
Order Codes
Max CPU Temperature
Part Number Package Flash RAM
Frequency (MHz) range (°C)
ST10F272Z2Q3 PQFP144 64 256 KB 20 KB -40/+125
ST10F272Z2T3 LQFP144 40 256 KB 20 KB -40/+125

June 2006 Rev 1 1/179

www.st.com 1
Contents ST10F272

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.2 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.2 Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 37
5.5.3 Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 38
5.5.4 Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 38
5.5.5 . . . . . . . . . . . . . . . Flash non volatile access protection register 1 high 39

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5.5.6 XBus flash volatile temporary access unprotection register (XFVTAUR0) .

39
5.5.7 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5.8 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5.9 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 45
6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 46
6.3.1 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.2 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.3 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.3 MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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13.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

14 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

15 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 70
15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 72

16 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

17 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

18 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.3.3 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 111

23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
24.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
24.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
24.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
24.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
24.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
24.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
24.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

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24.8.7 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

24.8.8 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
24.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
24.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
24.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
24.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
24.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
24.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
24.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 173

25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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ST10F272 List of tables

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Summary of IFLASH address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3. Address space reserved to the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. Flash modules sectorization (Read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Flash modules sectorization
(Write operations or with ROMS1=’1’ or BootStrap mode)27
Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. XBus flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. ST10F272 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 26. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 27. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 28. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 29. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 31. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 32. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 59
Table 33. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 59
Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 60
Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 61
Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 62
Table 37. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 62
Table 38. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 64
Table 39. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 64
Table 40. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 70
Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 71
Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 71
Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 72
Table 44. Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 73
Table 45. Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 73
Table 46. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 47. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 48. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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List of tables ST10F272

Table 49. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 50. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 104
Table 51. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 52. List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 53. List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 54. List of flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 55. IDMANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 56. IDCHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 57. IDMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 58. IDPROG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 61. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 62. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 63. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 68. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 70. PLL characteristics (VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C) . . . . . . . . . . . . . . 153
Table 71. Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 72. Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 73. 32kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 74. Minimum values of negative resistance (module) for 32kHz oscillator . . . . . . . . . . . . . . . 155
Table 75. External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 76. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 78. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 81. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 83. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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ST10F272 List of figures

List of figures

Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. ST10F272 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value). . . . . 25
Figure 5. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. CPU block diagram (MAC Unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 10. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 12. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 13. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 76
Figure 14. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 76
Figure 15. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 77
Figure 16. Connection to one CAN bus with internal Parallel Mode enabled . . . . . . . . . . . . . . . . . . . 77
Figure 17. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 18. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 19. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 20. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 21. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 22. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 23. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 24. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 25. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 26. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 28. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 29. SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . 98
Figure 30. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 31. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 32. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 33. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 101
Figure 34. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 102
Figure 35. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 36. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 37. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 38. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 134
Figure 39. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 40. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 41. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 42. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 43. Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 44. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 45. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 46. ST10F272 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 47. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 48. 32kHz crystal oscillator connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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List of figures ST10F272

Figure 49. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 159
Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 160
Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 161
Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 162
Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 165
Figure 55. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 166
Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 167
Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 168
Figure 58. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 59. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 60. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 63. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 64. 144-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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ST10F272 Introduction

1 Introduction

The ST10F272 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-
chip CMOS microcontrollers.
The ST10F272 combines high CPU performance (up to 32 million instructions per second)
with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
ST10F272 is processed in 0.18µm CMOS technology. The MCU core and the logic is
supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V
supply and I/Os work at 5V.
The device is upward compatible with the ST10F269 device, with the following set of
differences:
Flash control interface is now based on STMicroelectronics third generation of stand-alone
Flash memories (M29F400 series), with an embedded Program/Erase Controller. This
completely frees up the CPU during programming or erasing the Flash.
Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is
used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin
to 5.0V external supply. Instead, this pin should be connected to a decoupling capacitor
(ceramic type, typical value 10nF, maximum value 100nF).
The AC and DC parameters are modified due to a difference in the maximum CPU
frequency.
A new VDD pin replaces DC2 of ST10F269.
EA pin assumes a new alternate functionality: it is also used to provide a dedicated power
supply (see VSTBY) to maintain biased a portion of the XRAM (16Kbytes) when the main
Power Supply of the device (VDD and consequently the internally generated V18) is turned
off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5-5.5
Volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8V
for the RAM, the low-voltage section of the 32kHz oscillator and the Real Time Clock
module when not disabled. It is allowed to exceed the upper limit up to 6V for a very short
period of time during the global life of the device, and exceed the lower limit down to 4V
when RTC and 32kHz on-chip oscillator are not used.
A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0,
while the new one is referred as XSSC or simply SSC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic SSC,
and the new XSSC.
A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while
the new one is referred as XASC or simply as ASC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic ASC,
and the new XASC.
A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here PWM0,
while the new one is referred as XPWM or simply as PWM1). Note that some restrictions
and functional differences due to the XBUS peculiarities are present between the classic
PWM, and the new XPWM.
An I2C interface on the XBUS is added (see X-I2C or simply I2C interface).

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Introduction ST10F272

CLKOUT function can output either the CPU clock (like in ST10F269) or a software
programmable prescaled value of the CPU clock.
On-chip RAM memory has been increased (Flash size remained the same).
PLL multiplication factors have been adapted to new frequency range.
A/D Converter is not fully compatible versus ST10F269 (timing and programming model).
Formula for the convertion time is still valid, while the sampling phase programming model is
different.
Besides, additional 8 channels are available on P1L pins as alternate function: the accuracy
reachable with these extra channels is reduced with respect to the standard Port5 channels.
External Memory bus is affected by limitations on maximum speed and maximum
capacitance load: ST10F272 is not able to address an external memory at 64MHz with 0
wait states.
XPERCON register bit mapping modified according to new peripherals implementation (not
fully compatible with ST10F269).
Bondout chip for emulation (ST10R201) cannot achieve more than 50MHz at room
temperature (so no real time emulation possible at maximum speed).
Input section characteristics are different. The threshold programmability is extended to all
port pins (additional XPICON register); it is possible to select standard TTL (with up to
400mV of hysteresis) and standard CMOS (with up to 750mV of hysteresis).
Output transition is not programmable.
CAN module is enhanced: ST10F272 implements two C-CAN modules, so the programming
model is slightly different. Besides, the possibility to map in parallel the two CAN modules is
added (on P4.5/P4.6).
On-chip main oscillator input frequency range has been reshaped, reducing it from 1-25MHz
down to 4-8MHz. This is a low power oscillator amplifier, that allows a power consumption
reduction when Real Time Clock is running in Power Down mode, using as reference the on-
chip main oscillator clock. When this on-chip amplifier is used as reference for Real Time
Clock module, the Power-down consumption is dominated by the consumption of the
oscillator amplifier itself.
A second on-chip oscillator amplifier circuit (32kHz) is implemented for low power modes: it
can be used to provide the reference to the Real Time Clock counter (either in Power Down
or Stand-by mode). Pin XTAL3 and XTAL4 replace a couple of VDD/VSS pins of ST10F269.
Possibility to re-program internal XBUS chip select window characteristics (XRAM2 window)
is added.

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ST10F272 Introduction

Figure 1. Logic symbol

V18 VDD VSS

XTAL1 Port 0
XTAL2 16-bit
XTAL3 Port 1
XTAL4 16-bit
RSTIN Port 2
RSTOUT 16-bit
VAREF Port 3
15-bit
VAGND
ST10F272 Port 4
NMI 8-bit
EA / VSTBY Port 6
READY 8-bit
ALE Port 7
RD 8-bit
WR / WRL Port 8
8-bit
Port 5
16-bit RPD

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Pin data ST10F272

2 Pin data

Figure 2. Pin configuration (top view)

P1L.6 / A6 / AN22 *(*)

P1L.3 / A3 / AN19 *(*)

P1L.2 / A2 / AN18 *(*)
P1L.7 / A7 / AN23 (*)

P1L.5 / A5 / AN21 (*)

P1L.4 / A4 / AN20 (*)

P1L.1 / A1 / AN17 (*)

P1L.0 / A0 / AN16 (*)
P1H.7 / A15 / CC27I
P1H.6 / A14 / CC26I
P1H.5 / A13 / CC25I
P1H.4 / A12 / CC24I

P0H.7 / AD15
P0H.6 / AD14
P0H.5 / AD13
P0H.4 / AD12
P0H.3 / AD11
P0H.2 / AD10
P0H.1 / AD9
P1H.3 / A11
P1H.2 / A10
P1H.1 / A9
P1H.0 / A8
RSTOUT
XTAL4
XTAL3

XTAL1
XTAL2
RSTIN

VDD

VDD

VDD
VSS

VSS

VSS
NMI
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P6.0 / CS0 1 108 P0H.0 / AD8
P6.1 / CS1 2 107 P0L.7 / AD7
P6.2 / CS2 3 106 P0L.6 / AD6
P6.3 / CS3 4 105 P0L.5 / AD5
P6.4 / CS4 5 104 P0L.4 / AD4
P6.5 / HOLD / SCLK1 6 103 P0L.3 / AD3
P6.6 / HLDA / MTSR1 7 102 P0L.2 / AD2
P6.7 / BREQ / MRST1 8 101 P0L.1 / AD1
P8.0 / XPOUT0 / CC16IO 9 100 P0L.0 / AD0
P8.1 / XPOUT1 / CC17IO 10 99 EA / VSTBY
P8.2 / XPOUT2 / CC18IO 11 98 ALE
P8.3 / XPOUT3 / CC19IO 12 97 READY
P8.4 / CC20IO 13 96 WR/WRL
P8.5 / CC21IO 14 95 RD
P8.6 / RxD1 / CC22IO 15 94 VSS
P8.7 / TxD1 / CC23IO 16 93 VDD
VDD 17 92 P4.7 / A23 / CAN2_TxD / SDA
VSS 18 91 P4.6 / A22 / CAN1_TxD / CAN2_TxD
P7.0 / POUT0 19 ST10F272 90 P4.5 / A21 / CAN1_RxD / CAN2_RxD
P7.1 / POUT1 20 89 P4.4 / A20 / CAN2_RxD / SCL
P7.2 / POUT2 21 88 P4.3 / A19
P7.3 / POUT3 22 87 P4.2 / A18
P7.4 / CC28IO 23 86 P4.1 / A17
P7.5 / CC29IO 24 85 P4.0 / A16
P7.6 / CC30IO 25 84 RPD
P7.7 / CC31IO 26 83 VSS
P5.0 / AN0 27 82 VDD
P5.1 / AN1 28 81 P3.15 / CLKOUT
P5.2 / AN2 29 80 P3.13 / SCLK0
P5.3 / AN3 30 79 P3.12 / BHE / WRH
P5.4 / AN4 31 78 P3.11 / RxD0
P5.5 / AN5 32 77 P3.10 / TxD0
P5.6 / AN6 33 76 P3.9 / MTSR0
P5.7 / AN7 34 75 P3.8 / MRST0
P5.8 / AN8 35 74 P3.7 / T2IN
P5.9 / AN9 36 73 P3.6 / T3IN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P2.0 / CC0IO
P2.1 / CC1IO
P2.2 / CC2IO
P2.3 / CC3IO
P2.4 / CC4IO
P2.5 / CC5IO
P2.6 / CC6IO
P2.7 / CC7IO

V18
VAREF

VSS

VSS

P3.1 / T6OUT

P3.3 / T3OUT

VSS
VAGND
P5.10 / AN10 / T6EUD
P5.11 / AN11 / T5EUD

VDD

P2.8 / CC8IO / EX0IN

P2.9 / CC9IO / EX1IN
P2.10 / CC10IO / EX2IN
P2.11 / CC11IO / EX3IN
P2.12 / CC12IO / EX4IN
P2.13 / CC13IO / EX5IN
P2.14 / CC14IO / EX6IN
P5.12 / AN12 / T6IN
P5.13 / AN13 / T5IN
P5.14 / AN14 / T4EUD
P5.15 / AN15 / T2EUD

P2.15 / CC15IO / EX7IN / T7IN

P3.0 / T0IN

P3.2 / CAPIN

P3.4 / T3EUD
P3.5 / T4IN

VDD

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ST10F272 Pin data

Table 1. Pin description

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
1-8 I/O high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The
following Port 6 pins have alternate functions:
1 O P6.0 CS0 Chip select 0 output
... ... ... ... ...

P6.0 - P6.7 5 O P6.4 CS4 Chip select 4 output

I P6.5 HOLD External master hold request input
6
I/O SCLK1 SSC1: master clock output / slave clock input
O P6.6 HLDA Hold acknowledge output
7
I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I
O P6.7 BREQ Bus request output
8
I/O MRST1 SSC1: master-receiver / slave-transmitter I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
9-16 I/O high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).
The following Port 8 pins have alternate functions:
I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output
9
O XPWM0 PWM1: channel 0 output
... ... ... ... ...
I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output
P8.0 - P8.7 12
O XPWM0 PWM1: channel 3 output
13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output
14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output
I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output
15
I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)
I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output
16 ASC1: Clock / Data output
O TxD1
(Asynchronous/Synchronous)

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Pin data ST10F272

Table 1. Pin description (continued)

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
19-26 I/O high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
The following Port 7 pins have alternate functions:
19 O P7.0 POUT0 PWM0: channel 0 output
P7.0 - P7.7
... ... ... ... ...
22 O P7.3 POUT3 PWM0: channel 3 output
23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output
... ... ... ... ...
26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
27-36 I
ANx (Analog input channel x), or they are timer inputs. The input threshold of
39-44 I
Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate
functions:
39 I P5.10 T6EUD GPT2: timer T6 external up/down control input
P5.0 - P5.9
P5.10 - P5.15 40 I P5.11 T5EUD GPT2: timer T5 external up/down control input
41 I P5.12 T6IN GPT2: timer T6 count input
42 I P5.13 T5IN GPT2: timer T5 count input
43 I P5.14 T4EUD GPT1: timer T4 external up/down control input
44 I P5.15 T2EUD GPT1: timer T2 external up/down control input
16-bit bidirectional I/O port, bit-wise programmable for input or output via
direction bit. Programming an I/O pin as input forces the corresponding output
47-54
I/O driver to high impedance state. Port 2 outputs can be configured as push-pull or
57-64
open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following Port 2 pins have alternate functions:
47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output
... ... ... ... ...
P2.0 - P2.7 54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output
P2.8 - P2.15
57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output
I EX0IN Fast external interrupt 0 input
... ... ... ... ...
64 I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output
I EX7IN Fast external interrupt 7 input
I T7IN CAPCOM2: timer T7 count input

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ST10F272 Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
65-70, I/O output via direction bit. Programming an I/O pin as input forces the corresponding
73-80, I/O output driver to high impedance state. Port 3 outputs can be configured as push-
81 I/O pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or
CMOS). The following Port 3 pins have alternate functions:
65 I P3.0 T0IN CAPCOM1: timer T0 count input
66 O P3.1 T6OUT GPT2: timer T6 toggle latch output
67 I P3.2 CAPIN GPT2: register CAPREL capture input
68 O P3.3 T3OUT GPT1: timer T3 toggle latch output
69 I P3.4 T3EUD GPT1: timer T3 external up/down control input
70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture
P3.0 - P3.5
P3.6 - P3.13, 73 I P3.6 T3IN GPT1: timer T3 count/gate input
P3.15
74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture
75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O
76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I
77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)
78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)
79 O P3.12 BHE External memory high byte enable signal
WRH External memory high byte write strobe
80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input
System clock output (programmable divider on CPU
81 O P3.15 CLKOUT
clock)

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Pin data ST10F272

Table 1. Pin description (continued)

Symbol Pin Type Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold is selectable (TTL or
85-92 I/O CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open
drain drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
85 O P4.0 A16 Segment address line
86 O P4.1 A17 Segment address line
87 O P4.2 A18 Segment address line
88 O P4.3 A19 Segment address line
O A20 Segment address line

P4.0 –P4.7 89 I P4.4 CAN2_RxD CAN2: receive data input

I/O SCL I2C Interface: serial clock
O A21 Segment address line
90 I P4.5 CAN1_RxD CAN1: receive data input
I CAN2_RxD CAN2: receive data input
O A22 Segment address line
91 O P4.6 CAN1_TxD CAN1: transmit data output
O CAN2_TxD CAN2: transmit data output
O A23 Most significant segment address line
92 O P4.7 CAN2_TxD CAN2: transmit data output
I/O SDA I2C Interface: serial data
External memory read strobe. RD is activated for every external instruction or
RD 95 O
data read access.
External memory write strobe. In WR-mode this pin is activated for every external
data write access. In WRL mode this pin is activated for low byte data write
WR/WRL 96 O
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
Ready input. The active level is programmable. When the ready function is
READY/ enabled, the selected inactive level at this pin, during an external memory
97 I
READY access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
Address latch enable output. In case of use of external addressing or of
ALE 98 O
multiplexed mode, this signal is the latch command of the address lines.

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ST10F272 Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

External access enable pin.

A low level applied to this pin during and after Reset forces the ST10F272 to start
the program from the external memory space. A high level forces ST10F272 to
start in the internal memory space. This pin is also used (when Stand-by mode is
entered, that is ST10F272 under reset and main VDD turned off) to bias the 32
kHz oscillator amplifier circuit and to provide a reference voltage for the low-
EA / VSTBY 99 I power embedded voltage regulator which generates the internal 1.8V supply for
the RTC module (when not disabled) and to retain data inside the Stand-by
portion of the XRAM (16Kbyte).
It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device
life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In
running mode, this pin can be tied low during reset without affecting 32 kHz
oscillator, RTC and XRAM activities, since the presence of a stable VDD
guarantees the proper biasing of all those modules.
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold of Port 0 is selectable
(TTL or CMOS).
In case of an external bus configuration, PORT0 serves as the address (A) and
as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.
Demultiplexed bus modes
P0L.0 -P0L.7,
100-107,
P0H.0 Data path width 8-bit 16-bi
108, I/O
P0H.1 -
111-117 P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes

Data path width 8-bit 16-bi

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 – A15 AD8 - AD15

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus
(A) in demultiplexed bus modes: if at least BUSCONx is configured such the
demultiplexed mode is selected, the pis of PORT1 are not available for general
118-125 purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS).
I/O
128-135
The pins of P1L also serve as the additional (up to 8) analog input channels for
P1L.0 - P1L.7 the A/D converter, where P1L.x equals ANy (Analog input channel y,
P1H.0 - where y = x + 16). This additional function have higher priority on demultiplexed
P1H.7 bus function.
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO CAPCOM2: CC24 capture input
133 I P1H.5 CC25IO CAPCOM2: CC25 capture input
134 I P1H.6 CC26IO CAPCOM2: CC26 capture input
135 I P1H.7 CC27IO CAPCOM2: CC27 capture input

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Pin data ST10F272

Table 1. Pin description (continued)

Symbol Pin Type Function

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.
XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input
XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F272. An
internal pull-up resistor permits power-on reset using only a capacitor connected
RSTIN 140 I
to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
Internal Reset Indication Output. This pin is driven to a low level during hardware,
RSTOUT 141 O software or watchdog timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
NMI 142 I order to force the ST10F272 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
VAREF 37 - A/D converter reference voltage and analog supply
VAGND 38 - A/D converter reference and analog ground
Timing pin for the return from interruptible power down mode and synchronous /
RPD 84 -
asynchronous reset selection.
17, 46,
Digital supply voltage = + 5V during normal operation, idle and power down
72,82,93
VDD - modes.
, 109,
It can be turned off when Stand-by RAM mode is selected.
126, 136
18,45,
55,71,
VSS 83,94, - Digital ground
110,
127, 139
1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)
V18 56 -
must be connected between this pin and nearest VSS pin.

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ST10F272 Functional description

3 Functional description

The architecture of the ST10F272 combines advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The block diagram gives an overview of the
different on-chip components and the high bandwidth internal bus structure of the
ST10F272.

Figure 3. Block diagram

16
32
IFLASH 16
256K CPU-Core and MAC Unit IRAM
2K

XRAM1
2K 16 Watchdog
(PEC) 16 PEC
16 Oscillator
XRAM2 16
16K 16 32kHz
(STBY) XPWM Oscillator
16 16 Interrupt Controller
XRTC XASC PLL
16 16
XI2C XSSC 5V-1.8V
Voltage
16 16 Regulator
XCAN1 XCAN2

16
Port 0

GPT1 / GPT2
External Bus

CAPCOM2

CAPCOM1
10-bit ADC
Controller

ASC0

SSC0

PWM

16 16
Port 1

Port 2
8
Port 4

BRG BRG

Port 6 Port 5 Port 3 Port 7 Port 8

8 16 15 8 8

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Memory organization ST10F272

4 Memory organization

The memory space of the ST10F272 is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16M Bytes. The entire memory space can be accessed Byte wise or Word wise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFLASH: 256K Bytes of on-chip Flash memory. It is divided in 8 blocks (B0F0...B0F7) that
constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF
(8Kbyte) appears at address 00’0000h: refer to Chapter 5: Internal Flash memory on
page 26 for more details on memory mapping in boot mode. The summary of address range
for IFLASH is the following:

Table 2. Summary of IFLASH address range

Blocks User Mode Size

B0TF Not visible 8K

B0F0 00’0000h - 00’1FFFh 8K
B0F1 00’2000h - 00’3FFFh 8K
B0F2 00’4000h - 00’5FFFh 8K
B0F3 00’6000h - 00’7FFFh 8K
B0F4 01’8000h - 01’FFFFh 32K
B0F5 02’0000h - 02’FFFFh 64K
B0F6 03’0000h - 03’FFFFh 64K
B0F7 04’0000h - 04’FFFFh 64K

IRAM: 2K Bytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 8K/16K+2K Bytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code.
The XRAM is divided into 2 areas, the first 2K Bytes named XRAM1 and the second 8K/16K
Bytes named XRAM2, connected to the internal XBUS and are accessed like an external
memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns
access at 64MHz CPU clock). Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.

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ST10F272 Memory organization

After reset the XRAM2 is mapped from address 09’0000h.

XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA /
VSTBY pin when main supply VDD is turned off.
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.

ST10F272 XRAM: 16K+2K Bytes of XRAM

The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled.
The XRAM2 (16K Bytes) address range is after reset 09’0000h - 09’3FFFh and is mirrored
every 16KByte boundary.

SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of address space is reserved for the special
function register areas. SFRs are Wordwide registers which are used to control and to
monitor the function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
If one or the two CAN modules are used, Port 4 cannot be programmed to output all 8
segment address lines. Thus, only 4 segment address lines can be used, reducing the
external memory space to 5M Bytes (1M Byte per CS line).
RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The
RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz
CPU clock. No tristate waitstate is used.
PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of
62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64MHz
CPU clock. No tristate waitstate is used.
SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus

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Memory organization ST10F272

(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock.
No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used.
The following set of features are provided:
● CLKOUT programmable divider
● XBUS interrupt management registers
● ADC multiplexing on P1L register
● Port1L digital disable register for extra ADC channels
● CAN2 multiplexing on P4.5/P4.6
● CAN1-2 main clock prescaler
● Main Voltage Regulator disable for power-down mode
● TTL / CMOS threshold selection for Port0, Port1, and Port5.
In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16M Bytes of external memory can be connected to the microcontroller.

Visibility of XBUS peripherals

In order to keep the ST10F272 compatible with the ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to Chapter 23: Register set on page 112.

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ST10F272 Memory organization

Figure 4. ST10F272 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value)
Code
Segment Page Segment Page RAM / SFR (4Kbyte)
FF FFFF 1023 11 FFFF 67
255 66
17 Ext. Memory
65
01 0000
00 FFFF 00 FFFF
11 0000 64 SFR 512
10 FFFF 67 00 FE00 SFR 512
00 FDFF
66 00 FE00
16 Ext. Memory 65 00 FDFF
64
10 0000
0F FFFF XRAM2 63
IRAM 2K
XRAM2 62
15 XRAM2 61

0F 0000 XRAM2 60
0E FFFF XRAM2 59
00 F600 IRAM 2K
XRAM2 58 00 F5FF
14 XRAM2 57

0E 0000 XRAM2 56 Reserved 1K

0D FFFF XRAM2 55
XRAM2 54 00 F200
13 XRAM2 53
00 F1FF
ESFR 512
XRAM2 52 00 F000
0D 0000 00 F600
00 EFFF
XADRS3 = 800Bh (512K)

0C FFFF XRAM2 51 XCAN1 256 00 F5FF

XRAM2 50 XCAN2 256
12 XRAM2 49 XRTC 256
XRAM2 48 XPWM 256
0C 0000 Reserved 1K
0B FFFF XRAM2 47 XMiscellaneous 256
XRAM2
11
46
XI2C 256
XRAM2 45
XRAM2
XASC 256 00 F200
0B 0000 44
XSSC 256 00 F1FF
0A FFFF XRAM2 43
00 E800
XRAM2 42
00 E7FF ESFR 512
10 XRAM2 41 00 F000
XRAM2 40 00 EFFF
0A 0000
09 FFFF XRAM2 39
XRAM1 2K
XRAM2 38
9 XRAM2 37

09 0000 XRAM2 36
08 FFFF 35
00 E000
Reserved 34 00 DFFF
8 33

08 0000 32
07 FFFF 31

Reserved 30
7 29

07 0000 28
06 FFFF 27

Reserved 26
6 25

06 0000 24
05 FFFF 23

Reserved 22
5 21

05 0000 20
04 FFFF 19
18
4 FLASH 17 Ext. Memory 8K
04 0000 16
03 FFFF 15

FLASH 14
3 13
12
03 0000
02 FFFF 11
FLASH 10
2 9

02 0000 8
01 FFFF FLASH 7
6
1 5 Address Area, where XRAM2
01 0000
Ext. Memory
4 is mirrored every 16Kbytes
00 FFFF 3
boundary after reset
Ext. Memory 2

0
0 1
0 FLASH
0
Bit-addressable Memory
00 0000 00 0000 00 C000

16 MB FLASH + XRAM - 1Mbyte Data Page 3 (Segment 0) - 16Kbyte

* The first 32K of FLASH may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT).
Absolute Memory Address are hexadecimal values, while Data Page Number are decimal values.

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5 Internal Flash memory

5.1 Overview
The on-chip Flash is composed by one matrix module, 256 KBytes wide.
This module is on ST10 Internal bus, so it is called IFLASH

Figure 5. Flash structure

IFLASH Control Section

Flash Control HV and Ref.

Registers Generator

Bank 0: 256 Kbyte

Program Memory
+ Program/Erase
8 Kbyte Test-Flash Controller

I-BUS Interface

The programming operations of the flash are managed by an embedded Flash

Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations
are internally generated.
The Data bus is 32-bit wide for fetch accesses to IFLASH, while it is 16 bit wide for read
accesses to IFLASH. Read/write accesses to IFLASH Control Registers area are 16 bit
wide.

5.2 Functional description

5.2.1 Structure
The following table shows the Address space reserved to the Flash module.

Table 3. Address space reserved to the Flash module

Description Addresses Size

IFLASH sectors 0x00 0000 to 0x04 FFFF 256 Kbyte

Reserved IBUS area 0x05 0000 to 0x07 FFFF 192 Kbyte
Registers and Flash internal reserved area 0x08 0000 to 0x08 FFFF 64 Kbyte

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5.2.2 Modules structure

The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory
divided in 8 sectors (B0F0...B0F7). Bank 0 contains also a reserved sector named Test-
Flash. The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register
Interface and other internal service memory space used by the Flash Program/Erase
controller.
The following tables show the memory mapping of the Flash when it is accessed in read
mode (Table 4: Flash modules sectorization (Read operations)), and when accessed in
write or erase mode (Table 5: Flash modules sectorization (Write operations or with
ROMS1=’1’ or BootStrap mode)): note that with this second mapping, the first four banks
are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON
register).

Table 4. Flash modules sectorization (Read operations)

Bank Description Addresses Size ST10 Bus size

Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB
Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB
Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB
B0 32-bit (I-BUS)
Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB
Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB
Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB
Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Table 5. Flash modules sectorization

(Write operations or with ROMS1=’1’ or BootStrap mode)
Bank Description Addresses Size ST10 Bus size

Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB
Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB
Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB
B0 Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB 32-bit (I-BUS)
Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB
Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB
Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB
Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

The table above refers to the configuration when bit ROMS1 of SYSCON register is set.

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When Bootstrap mode is entered:

● Test-Flash is seen and available for code fetches (address 00’0000h)
● User I-Flash is only available for read and write accesses
● Write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever ROMS1 bit in SYSCON value
● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in
segment 0.
Example:
In default configuration, to program address 0, user must put the value 01'0000h in the
FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must
be performed.
Next Table 6 shows the Control Register interface composition: this set of registers can be
addressed by the CPU.

Table 6. Control register interface

Bus
Name Description Addresses Size
size

FCR1-0 Flash Control Registers 1-0 0x0008 0000 - 0x0008 0007 8 byte
FDR1-0 Flash Data Registers 1-0 0x0008 0008 - 0x0008 000F 8 byte
FAR Flash Address Registers 0x0008 0010 - 0x0008 0013 4 byte
FER Flash Error Register 0x0008 0014 - 0x0008 0015 2 byte
Flash Non Volatile Protection I 0x0008 DFB0 - 0x0008
FNVWPIR 2 byte
Register DFB1 16-bit
Flash Non Volatile Access Protection 0x0008 DFB8 - 0x0008
FNVAPR0 2 byte
Register 0 DFB9
Flash Non Volatile Access Protection 0x0008 DFBC - 0x0008
FNVAPR1 4 byte
Register 1 DFBF
XBus Flash Volatile Temporary
XFVTAUR0 0x0000 EB50 - 0x0000 EB51 2 byte
Access Unprotection Register 0

5.2.3 Low power mode

The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (tPD).
Recovery time from Power Down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
Note: PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.

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5.3 Write operation

The Flash module have one single register interface mapped in the memory space of the
IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control
registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit
registers are used to store Flash Address and Data for Program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible
with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write).
Before accessing the IFlash module (and consequently also the Flash register to be used for
program/erasing operations), bit ROMEN in SYSCON register shall be set.
During a Flash write operation any attempt to read the flash itself, that is under modification,
will output invalid data (software trap 009Bh). This means that the Flash is not fetchable
when a programming operation is active: the write operation commands must be executed
from another memory (internal RAM or external memory), as in ST10F269 device. In fact,
due to IBUS characteristics, it is not possible to perform a write operation on IFLASH, when
fetching code from IFLASH.
Direct addressing is not allowed for write accesses to IFLASH Control Registers.
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.

Power supply drop

If during a write operation the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the module is
reset to Read mode. At following Power-on, the interrupted Flash write operation must be
repeated.

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5.4 Registers description

5.4.1 Flash control register 0 low

The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High
(FCR0H) is used to enable and to monitor all the write operations on the IFLASH. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap Mode only.

FCR0L (0x08 0000) FCR Reset Value: 0000h:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LOCK res. res. BSY0 res.
R R

Table 7. Flash control register 0 low

Bit Function

Bank 0 Busy (IFLASH)

This bit indicates that a write operation is running on Bank 0 (IFLASH). It is
automatically set when bit WMS is set. Setting Protection operation sets bit BSY0
BSY0 (since protection registers are in this Block). When this bit is set, every read
access to Bank 0 will output invalid data (software trap 009Bh), while every write
access to the Bank will be ignored. At the end of the write operation or during a
Program or Erase Suspend this bit is automatically reset and the Bank returns to
read mode. After a Program or Erase Resume this bit is automatically set again.
Flash Registers Access Locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
LOCK bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSY0 bit is reset.

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5.4.2 Flash control register 0 high

The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap Mode only.

FCR0H (0x08 0002) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WMS SUSP WPG DWPG SER reserved SPR reserved
RW RW RW RW RW RW

Table 8. Flash control register 0 high

Bit Function

Set Protection
This bit must be set to select the Set Protection operation. The Set Protection
operation allows to program 0s in place of 1s in the Flash Non Volatile Protection
Registers. The Flash Address in which to program must be written in the FARH/L
SPR registers, while the Flash Data to be programmed must be written in the FDR0H/L
before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0E8FB0-
0x08DFBF. SPR bit is automatically reset at the end of the Set Protection
operation.
Sector Erase
This bit must be set to select the Sector Erase operation in the Flash modules. The
Sector Erase operation allows to erase all the Flash locations to value 0xFF. From
SER 1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be
selected to be erased through bits BxFy of FCR1H/L registers before starting the
execution by setting bit WMS. It is not necessary to pre-program the sectors to
0x00, because this is done automatically. SER bit is automatically reset at the end
of the Sector Erase operation.
Double Word Program
This bit must be set to select the Double Word (64 bits) Program operation in the
Flash module. The Double Word Program operation allows to program 0s in place
DWPG of 1s. The Flash Address in which to program (aligned with even words) must be
written in the FARH/L registers, while the 2 Flash Data to be programmed must be
written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word)
before starting the execution by setting bit WMS. DWPG bit is automatically reset
at the end of the Double Word Program operation.
Word Program
This bit must be set to select the Word (32 bits) Program operation in the Flash
module. The Word Program operation allows to program 0s in place of 1s. The
WPG Flash Address to be programmed must be written in the FARH/L registers, while
the Flash Data to be programmed must be written in the FDR0H/L registers before
starting the execution by setting bit WMS. WPG bit is automatically reset at the
end of the Word Program operation.

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Table 8. Flash control register 0 high (continued)

Bit Function

Suspend
This bit must be set to suspend the current Program (Word or Double Word) or
Sector Erase operation in order to read data in one of the Sectors of the Bank
under modification or to program data in another Bank. The Suspend operation
resets the Flash Bank to normal read mode (automatically resetting bit BSY0).
When in Program Suspend, the Flash module accepts only the following
SUSP operations: Read and Program Resume. When in Erase Suspend the module
accepts only the following operations: Read, Erase Resume and Program (Word
or Double Word; Program operations cannot be suspended during Erase
Suspend). To resume a suspended operation, the WMS bit must be set again,
together with the selection bit corresponding to the operation to resume (WPG,
DWPG, SER).
Note: It is forbidden to start a new Write operation with bit SUSP already set.
Write Mode Start
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
WMS resume a suspended operation, this bit must be set again. It is forbidden to set this
bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to
start a new write (program or erase) operation (by setting WMS high) when bit
SUSP of FCR0 is high. Resetting this bit by software has no effect.

5.4.3 Flash control register 1 low

The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High
(FCR1H), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.

FCR1L (0x08 0004) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
RS RS RS RS RS RS RS RS

Table 9. Flash control register 1 low

Bit Function

Bank 0 IFLASH Sector 9:0 Status

These bits must be set during a Sector Erase operation to select the sectors to
erase in Bank 0. Besides, during any erase operation, these bits are automatically
B0F(7:0) set and give the status of the 8 sectors of Bank 0 (B0F7-B0F0). The meaning of
B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end
of a Write operation if no errors are detected.

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5.4.4 Flash control register 1 high

The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.

FCR1H (0x08 0006) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved B0S reserved
RS

Table 10. Flash control register 1 high

Bit Function

Bank 0 Status (IFLASH)

During any erase operation, this bit is automatically modified and gives the status
B0S of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of a
erase operation if no errors are detected.

During any erase operation, this bit is automatically set and gives the status of the Bank 0.
The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an
erase operation if no errors are detected.

Table 11. Banks (BxS) and sectors (BxFy) status bits meaning
ERR SUSP B0S = 1 meaning B0Fy = 1 meaning

1 - Erase Error in Bank 0 Erase Error in Sector y of Bank 0

0 1 Erase Suspended in Bank 0 Erase Suspended in Sector y of Bank 0
0 0 Don’t care Don’t care

5.4.5 Flash data register 0 low

The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L)
are used during the program operations to store Flash Address in which to program and
Data to program.

FDR0L (0x08 0008) FCR Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 12. Flash data register 0 low

Bit Function

Data Input 15:0

These bits must be written with the Data to program the Flash with the following
DIN(15:0)
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.

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5.4.6 Flash data register 0 high

FDR0H (0x08 000A) FCR Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 13. Flash data register 0 high

Bit Function

Data Input 31:16

These bits must be written with the Data to program the Flash with the following
DIN(31:16)
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.

5.4.7 Flash data register 1 low

FDR1L (0x08 000C) FCR Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 14. Flash data register 1 low

Bit Function

Data Input 15:0

These bits must be written with the Data to program the Flash with the following
DIN(15:0)
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.

5.4.8 Flash data register 1 high

FDR1H (0x08 000E) FCR Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 15. Flash data register 1 high

Bit Function

Data Input 31:16

DIN(31:16) These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.

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5.4.9 Flash address register low

FARL (0x08 0010) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 reserved
RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 16. Flash address register low

Bit Function

Address 15:2
These bits must be written with the Address of the Flash location to program in the
ADD(15:2)
following operations: Word Program (32-bit) and Double Word Program (64-bit). In
Double Word Program bit ADD2 must be written to ‘0’.

5.4.10 Flash address register high

FARH (0x08 0012) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ADD20 ADD19 ADD18 ADD17 ADD16

RW RW RW RW RW

Table 17. Flash address register high

Bit Function

Address 20:16
ADD(20:16) These bits must be written with the Address of the Flash location to program in the
following operations: Word Program and Double Word Program.

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5.4.11 Flash error register

Flash Error register, as well as all the other Flash registers, can be properly read only once
LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit
is reset as well; for this reason, it is definitively meaningful reading FER register content only
when LOCK bit and BSY0 bit are cleared.

FER (0x8 0014h) FCR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WPF RESER SEQER reserved 10ER PGER ERER ERR

RC RC RC RC RC RC RC

Table 18. Flash error register

Bit Function

Write Error
This bit is automatically set when an error occurs during a Flash write operation or
ERR
when a bad write operation setup is done. Once the error has been discovered
and understood, ERR bit must be software reset.
Erase Error
This bit is automatically set when an Erase error occurs during a Flash write
ERER operation. This error is due to a real failure of a Flash cell, that can no more be
erased. This kind of error is fatal and the sector where it occurred must be
discarded. This bit has to be software reset.
Program Error
This bit is automatically set when a Program error occurs during a Flash write
PGER operation. This error is due to a real failure of a Flash cell, that can no more be
programmed. The word where this error occurred must be discarded. This bit has
to be software reset.
1 over 0 Error
This bit is automatically set when trying to program at 1 bits previously set at 0
10ER (this does not happen when programming the Protection bits). This error is not due
to a failure of the Flash cell, but only flags that the desired data has not been
written. This bit has to be software reset.
Sequence Error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L,
SEQER FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid Write
Operation. In this case no Write Operation is executed. This bit has to be software
reset.
Resume Error
This bit is automatically set when a suspended Program or Erase operation is not
RESER
resumed correctly due to a protocol error. In this case the suspended operation is
aborted. This bit has to be software reset.
Write Protection Flag
This bit is automatically set when trying to program or erase in a sector write
WPF protected. In case of multiple Sector Erase, the not protected sectors are erased,
while the protected sectors are not erased and bit WPF is set. This bit has to be
software reset.

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5.5 Protection strategy

The protection bits are stored in Non Volatile Flash cells inside IFLASH module, that are
read once at reset and stored in 4 Volatile registers. Before they are read from the Non
Volatile cells, all the available protections are forced active during reset.
The protections can be programmed using the Set Protection operation (see Flash Control
Registers paragraph), that can be executed from all the internal or external memories
except from the Flash itself.
Two kind of protections are available: write protections to avoid unwanted writings and
access protections to avoid piracy. In next paragraphs all different level of protections are
shown, and architecture limitations are highlighted as well.

5.5.1 Protection registers

The 4 Non Volatile Protection Registers are one time programmable for the user.
One register (FNVWPIR) is used to store the Write Protection fuses respectively for each
sector IFLASH module. The other three Registers (FNVAPR0 and FNVAPR1L/H) are used
to store the Access Protection fuses.

5.5.2 Flash non volatile write protection I register

FNVWPIR (0x08 DFB0) NVR Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0
RW RW RW RW RW RW RW RW

Table 19. Flash non volatile write protection I register

Bit Function

Write Protection Bank 0 / Sectors 9-0 (IFLASH)

W0P(9:0) These bits, if programmed at 0, disable any write access to the sectors of Bank 0
(IFLASH)

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5.5.3 Flash non volatile access protection register 0

FNVAPR0 (0x08 DFB8) NVR Reset value: ACFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DBGP ACCP

RW RW

Table 20. Flash non volatile access protection register 0

Bit Function

Access Protection
This bit, if programmed at 0, disables any access (read/write) to data mapped
ACCP
inside IFlash Module address space, unless the current instruction is fetched from
IFlash.
Debug Protection
This bit, if erased at 1, allows to by-pass all the protections using the Debug
features through the Test Interface. If programmed at 0, on the contrary, all the
DBGP
debug features, the Test Interface and all the Flash Test Modes are disabled. Even
STMicroelectronics will not be able to access the device to run any eventual failure
analysis.

5.5.4 Flash non volatile access protection register 1 low

FNVAPR1L (0x08 DFBC) NVR Delivery value:: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 21. Flash non volatile access protection register 1 low

Bit Function

Protections Disable 15-0

If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP
PDS(15:0) is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP
have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit
PENx-1 has already been programmed at 0.

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5.5.5 Flash non volatile access protection register 1 high

FNVAPR1H (0x08 DFBE) NVR Delivery value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 22. Flash non volatile access protection register 1 high

Bit Function

Protections Enable 15-0

If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit
PEN15-0
ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has
already been programmed at 0.

5.5.6 XBus flash volatile temporary access unprotection register (XFVTAUR0)

XFVTAUR0 (0x00 EB50) NVR Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAUB
reserved RW

Table 23. XBus flash volatile temporary access unprotection register

Bit Function

Temporary Access Unprotection bit

If this bit is set to 1, the Access Protection is temporary disabled.
TAUB
This bit can be written only executing from IFlash.This fact guarantees that only a
code executed in IFlash, can unprotect the IFlash, when it is Access Protected.

5.5.7 Access protection

The I-Flash module has one level of access protection (access to data both in Reading and
Writing): if bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at
0, the I-Flash module becomes access protected: data in the I-Flash module can be read
only if the current execution is from the I-Flash module itself.
To enable Access Protection, the following sequence of operations is recommended:
● execution from external memory or internal Rams
● program TAUB bit at 1 in XFVTAUR0 register
● program ACCP bit in FNVAPR0 to 0 using Set Protection operation
● program TAUB bit at 0 in XFVTAUR0 register
● Access Protection is active when both ACCP bit and TAUB bit are set to 0.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order
to analyze rejects. Protection can be permanently enabled again by programming bit PEN0
of FNVAPR1L. The action to disable and enable again Access Protections in a permanent
way can be executed a maximum of 16 times. To execute the above described operations,
the Flash has to be temporary unprotected (See Section 5.5.9: Temporary unprotection)

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Internal Flash memory ST10F272

Trying to write into the access protected Flash from internal RAM or external memories will
be unsuccessful. Trying to read into the access protected Flash from internal RAM or
external memories will output a dummy data (software trap 0x009Bh).
When the Flash module is protected in access, also the data access through PEC of a
peripheral is forbidden. To read/write data in PEC mode from/to a protected Bank, first it is
necessary to temporary unprotect the Flash module.
In the following table a summary of all levels of possible Access protection is reported: in
particular, supposing to enable all possible access protections, when fetching from a
memory as listed in the first column, what is possible and what is not possible to do (see
column headers) is shown in the table.

Figure 6. Summary of access protection level

Read XRAMS or
Read IFLASH / Read FLASH Write FLASH
Ext Mem / Jump to
Jump to IFLASH Registers Registers
XRAM or Ext Mem

Fetching from IFLASH Yes / Yes Yes / Yes Yes No

Fetching from IRAM No / Yes Yes / Yes Yes No
Fetching from XRAM No / Yes Yes / Yes Yes No
Fetching from External
No / Yes Yes / Yes Yes No
Memory

When the Access Protection is enabled, Flash registers can not be written, so no
program/erase operation can be run on I-Flash. To enable the access to registers again, the
Temporary Access Unprotection procedure has to be followed (see Section 5.5.9).

5.5.8 Write protection

The Flash modules have one level of Write Protections: each Sector of each Bank of each
Flash Module can be Software Write Protected by programming at 0 the related bit W0Px in
FNVWPIRL register.

5.5.9 Temporary unprotection

Bits W0Px of FNVWPIRL can be temporary unprotected by executing the Set Protection
operation and by writing 1 into these bits.
To restore the write protection bits it is necessary to reset the microcontroller or to execute a
Set Protection operation and write 0 into the desired bits.
In reality, when a temporary write unprotection operation is executed, the corresponding
volatile register is written to 1, while the non volatile registers bits previously written to 0 (for
a protection set operation), will continue to maintain the 0. For this reason, the User
software must be in charge to track the current write protection status (for instance using a
specific RAM area), it is not possible to deduce it by reading the non volatile register content
(a temporary unprotection cannot be detected).
To temporary unprotect the Flash when the Access Protection is active, it is necessary to set
at 1 the bit TAUB in XFVTAUR0. This bit can be write at 1, only executing from Flash: in this
way only an instruction executed from Flash can unprotect the Flash itself.
To restore the Access Protection, it is necessary to reset the microcontroller or to write at 0
the bit TAUB in XFVTAUR0.

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ST10F272 Internal Flash memory

5.6 Write operation examples

In the following, examples for each kind of Flash write operation are presented.
Note: The write operation commands must be executed from another memory (internal RAM or
external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not
possible to perform write operation in Flash while fetching code from Flash.
Moreover, direct addressing is not allowed for write accesses to IFlash control registers.
This means that both address and data for a writing operation must be loaded in one of
ST10 GPR register (R0...R15).
Write operation on IBus registers is 16 bit wide.

Example of indirect addressing mode

MOV RWm, #ADDRESS; /*Load Add in RWm*/
MOV RWn, #DATA; /*Load Data in RWn*/
MOV [RWm], RWn; /*Indirect addressing*/

Word program
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x025554
FCR0H|= 0x2000; /*Set WPG in FCR0H*/
FARL = 0x5554; /*Load Add in FARL*/
FARH = 0x0002; /*Load Add in FARH*/
FDR0L = 0xAAAA; /*Load Data in FDR0L*/
FDR0H = 0xAAAA; /*Load Data in FDR0H*/
FCR0H|= 0x8000; /*Operation start*/

Double word program

Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and
data 0xAA55AA55 at address 0x03555C in IFLASH Module.
FCR0H |= 0x1000; /*Set DWPG/
FARL = 0x5558; /*Load Add in FARL*/
FARH = 0x0003; /*Load Add in FARH*/
FDR0L = 0x55AA; /*Load Data in FDR0L*/
FDR0H = 0x55AA; /*Load Data in FDR0H*/
FDR1L = 0xAA55; /*Load Data in FDR1L*/
FDR1H = 0xAA55; /*Load Data in FDR1H*/
FCR0H |= 0x8000; /*Operation start*/
Double Word Program is always performed on the Double Word aligned on a even Word: bit
ADD2 of FARL is ignored.

Sector erase
Example: Sector Erase of sectors B0F1 and B0F0 of Bank 0 in IFLASH Module.
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR1L |= 0x0003; /*Set B0F1, B0F0*/
FCR0H |= 0x8000; /*Operation start*/

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Suspend and resume

Word Program, Double Word Program, and Sector Erase operations can be suspended in
the following way:
FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
Then the operation can be resumed in the following way:
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR0H |= 0x8000; /*Operation resume*/
Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is
already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of
Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise
the operation is aborted and bit RESER of FER is set.

Erase suspend, program and resume

A Sector Erase operation can be suspended in order to program (Word or Double Word)
another Sector.
Example: Sector Erase of sector B0F1 of IFLASH Module.
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR1L |= 0x0002; /*Set B0F1*/
FCR0H |= 0x8000; /*Operation start*/
Example: Sector Erase Suspend.
FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
do /*Loop to wait for LOCK=0 and WMS=0*/
{tmp1 = FCR0L;
tmp2 = FCR0H;
} while ((tmp1 && 0x0010) || (tmp2 && 0x8000));
Example: Word Program of data 0x5555AAAA at address 0x045554 in IFLASH module.
FCR0H &= 0xBFFF; /*Rst SUSP in FCR0H*/
FCR0H|= 0x2000;/*Set WPG in FCR0H*/
FARL = 0x5554; /*Load Add in FARL*/
FARH = 0x0004; /*Load Add in FARH*/
FDR0L = 0xAAAA; /*Load Data in FDR0L*/
FDR0H = 0x5555; /*Load Data in FDR0H*/
FCR0H |= 0x8000; /*Operation start*/
Once the Program operation is finished, the Erase operation can be resumed in the
following way:
FCR0H|= 0x0800;/*Set SER in FCR0H*/
FCR0H|= 0x8000;/*Operation resume*/
Notice that during the Program Operation in Erase suspend, bits SER and SUSP are low. A
Word or Double Word Program during Erase Suspend cannot be suspended.
In summary:

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ST10F272 Internal Flash memory

A Sector Erase can be suspended by setting SUSP bit.

● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and
SER must be reset, then bit WPG and WMS can be set.
● To resume the Sector Erase operation bit SER must be set again.
● In any case it is forbidden to start any write operation with SUSP bit already set.

Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFLASH module.
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFB4; /*Load Add of register FNVWPIR in FARL*/
FARH = 0x0008; /*Load Add of register FNVWPIR in FARH*/
FDR0L = 0xFFF0; /*Load Data in FDR0L*/
FDR0H = 0xFFFF; /*Load Data in FDR0H*/
FCR0H |= 0x8000; /*Operation start*/
Example 2: Enable Access and Debug Protection.
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFB8; /*Load Add of register FNVAPR0 in FARL*/
FARH = 0x0008; /*Load Add of register FNVAPR0 in FARH*/
FDR0L = 0xFFFC; /*Load Data in FDR0L*/
FCR0H |= 0x8000; /*Operation start*/
Example 3: Disable in a permanent way Access and Debug Protection.
XFVTAUR0 = 0x0001; /*Set TAUB in XFVTAUR0*/
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFBC; /*Load Add of register FNVAPR1L in FARL*/
FARH = 0x0008; /*Load Add of register FNVAPR1L in FARH*/
FDR0L = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/
FCR0H |= 0x8000; /*Operation start*/
Example 4: Enable again in a permanent way Access and Debug Protection, after having
disabled them.
XFVTAUR0 = 0x0001; /*Set TAUB in XFVTAUR0*/
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFBC; /*Load Add register FNVAPR1H in FARL*/
FARH = 0x0008; /*Load Add register FNVAPR1H in FARH*/
FDR0H = 0xFFFE; /*Load Data in FDR0H for clearing
PEN0*/
FCR0H |= 0x8000; /*Operation start*/
XFVTAUR0 = 0x0000; /*Reset TAUB in XFVTAUR0*/
Disable and re-enable of Access and Debug Protection in a permanent way (as shown by
examples 3 and 4) can be done for a maximum of 16 times.

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Internal Flash memory ST10F272

5.7 Write operation summary

In general, each write operation is started through a sequence of 3 steps:
1. The first instruction is used to select the desired operation by setting its corresponding
selection bit in the Flash Control Register 0.
2. The second step is the definition of the Address and Data for programming or the
Sectors or Banks to erase.
3. The last instruction is used to start the write operation, by setting the start bit WMS in
the FCR0.
Once selected, but not yet started, one operation can be canceled by resetting the operation
selection bit.
A summary of the available Flash Module Write Operations are shown in the following
Table 24.

Table 24. Flash write operations

Operation Select bit Address and data Start bit

FARL/FARH
Word Program (32-bit) WPG WMS
FDR0L/FDR0H
FARL/FARH
Double Word Program (64-bit) DWPG FDR0L/FDR0H WMS
FDR1L/FDR1H
Sector Erase SER FCR1L/FCR1H WMS
Set Protection SPR FDR0L/FDR0H WMS
Program/Erase Suspend SUSP None None

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ST10F272 Bootstrap loader

6 Bootstrap loader

ST10F272 implements Boot capabilities in order to:

● Support bootstrap via UART or bootstrap via CAN for the standard bootstrap.
● Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different
way.

6.1 Selection among user-code, standard or selective bootstrap

The boot modes are triggered with a special combination set on Port0L[5...4]. Those
signals, as other configuration signals, are latched on the rising edge of RSTIN pin.
● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) will select the normal mode
(also called User Mode) and select the user Flash to be mapped from address
00’0000h.
● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) will select ST10 standard
bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from
address 00'0000h; user Flash is active and available for read accesses).
● Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) will activate new verifications to
select which bootstrap software to execute:
– if the User mode signature in the User Flash is programmed correctly, then a
software reset sequence is selected and the User code is executed;
– if the User mode signature is not programmed correctly in the user Flash, then the
User key location is read again. Its value will determine which communication
channel will be enabled for bootstraping
.

Table 25. ST10F272 boot mode selection

P0.5 P0.4 ST10 decoding

1 1 User Mode: user Flash mapped at 00’0000h

Standard Bootstrap Loader: User Flash mapped from 00’0000h, code fetches
1 0
redirected to Test-Flash at 00’0000h
Selective Boot Mode: User Flash mapped from 00’0000h, code fetches
0 1 redirected to Test-Flash at 00’0000h (different sequence execution in respect of
Standard Bootstrap Loader)
0 0 Reserved

6.2 Standard bootstrap loader

After entering the standard BSL mode and the respective initialization, the ST10F272 scans
the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from CAN
interface, or a start condition from UART line.
Start condition on UART RxD: ST10F272 starts standard bootstrap loader. This bootstrap
loader is identical to other ST10 devices (example: ST10F269, ST10F168).
Valid dominant bit on CAN1 RxD: ST10F272 start bootstrapping via CAN1.

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Bootstrap loader ST10F272

6.3 Alternate and selective boot mode (ABM and SBM)

6.3.1 Activation of the ABM and SBM

Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of
RSTIN.

6.3.2 User mode signature integrity check

The behavior of the Selective Boot Mode is based on the computing of a signature between
the content of 2 memory locations and a comparison with a reference signature. This
requires that users who use Selective Boot have reserved and programmed the Flash
memory locations.

6.3.3 Selective boot mode

When the user signature is not correct, instead of executing the Standard Bootstrap Loader
(triggered by P0L.4 low at reset), additional check is made.
Depending on the value at the User key location, following behavior will occur:
● A jump is performed to the Standard Bootstrap Loader
● Only UART is enabled for bootstraping
● Only CAN1 is enabled for bootstraping
● The device enters an infinite loop.

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ST10F272 Central processing unit (CPU)

7 Central processing unit (CPU)

The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and
dedicated SFRs. Additional hardware has been added for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Most of the ST10F272’s instructions can be executed in one instruction cycle which requires
31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in
one instruction cycle independent of the number of bits to be shifted.
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x
16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run the current context. This bank of General
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.
A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU.
The number of register banks is only restricted by the available Internal RAM space. For
easy parameter passing, a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack
pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer
value upon each stack access for the detection of a stack overflow or underflow.

Figure 7. CPU block diagram (MAC Unit not included)

16
CPU 2K Byte
Internal
SP MDH R15 RAM
STKOV MDL
STKUN Mul./Div.-HW
256K Byte Bit-Mask Gen. Bank
Exec. Unit General n
Flash
Instr. Ptr Purpose
memory Registers
4-Stage ALU
Pipeline
32 16-Bit
PSW R0 Bank
Barrel-Shift
SYSCON i
CP
BUSCON 0
BUSCON 1 ADDRSEL 1
BUSCON 2 ADDRSEL 2
BUSCON 3 ADDRSEL 3 Bank
BUSCON 4 ADDRSEL 4 16 0
Data Pg. Ptrs Code Seg. Ptr.

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Central processing unit (CPU) ST10F272

7.1 Multiplier-accumulator unit (MAC)

The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order
to improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a
repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-
accumulate, 32-bit signed arithmetic operations.

Figure 8. MAC unit architecture

Operand 1 Operand 2
16 16
GPR Pointers *

IDX0 Pointer
IDX1 Pointer

QR0 GPR Offset Register

QR1 GPR Offset Register 16 x 16
signed/unsigned
Multiplier
QX0 IDX Offset Register Concatenation
QX1 IDX Offset Register

32 32
Mux
Sign Extend
MRW Scaler
0h 08000h 0h
40 40 40 40 40
Repeat Unit Mux Mux
Interrupt
Controller 40 40
MCW
A B
ST10 CPU 40-bit Signed Arithmetic Unit

MSW 40
Flags MAE MAH MAL
Control Unit

40
Note: * Shared with standard ALU
8-bit Left/Right
Shifter

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ST10F272 Central processing unit (CPU)

7.2 Instruction set summary

The Table 26 lists the instructions of the ST10F272. The detailed description of each
instruction can be found in the “ST10 Family Programming Manual”.

Table 26. Standard instruction set summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2/4

ADDC(B) Add word (byte) operands with Carry 2/4
SUB(B) Subtract word (byte) operands 2/4
SUBC(B) Subtract word (byte) operands with Carry 2/4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bit-wise AND, (word/byte operands) 2/4
OR(B) Bit-wise OR, (word/byte operands) 2/4
XOR(B) Bit-wise XOR, (word/byte operands) 2/4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
Bit-wise modify masked high/low byte of bit-addressable direct word
BFLDH/L 4
memory with immediate data
CMP(B) Compare word (byte) operands 2/4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4
Determine number of shift cycles to normalize direct word GPR and
PRIOR 2
store result in direct word GPR
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2/4
MOVBS Move byte operand to word operand with sign extension 2/4
MOVBZ Move byte operand to word operand with zero extension 2/4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4

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Central processing unit (CPU) ST10F272

Table 26. Standard instruction set summary (continued)

Mnemonic Description Bytes

J(N)B Jump relative if direct bit is (not) set 4

JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI,
Call absolute/indirect/relative subroutine if condition is met 4
CALLR
CALLS Call absolute subroutine in any code segment 4
Push direct word register onto system stack and call absolute
PCALL 4
subroutine
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
Push direct word register onto system stack and update register
SCXT 4
with word operand
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
Return from intra-segment subroutine and pop direct word register
RETP 2
from system stack
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2/4
EXTS(R) Begin EXTended Segment (and Register) sequence 2/4
NOP Null operation 2

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ST10F272 Central processing unit (CPU)

7.3 MAC co-processor specific instructions

The Table 27 lists the MAC instructions of the ST10F272. The detailed description of each
instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC
instructions are encoded on 4 Bytes.

Table 27. MAC instruction set summary

Mnemonic Description

CoABS Absolute Value of the Accumulator

CoADD(2) Addition
CoASHR(rnd) Accumulator Arithmetic Shift Right & Optional Round
CoCMP Compare Accumulator with Operands
CoLOAD(-,2) Load Accumulator with Operands
CoMAC(R,u,s,-,rnd) (Un)Signed/(Un)Signed Multiply-Accumulate & Optional Round
(Un)Signed/(Un)Signed Multiply-Accumulate with Parallel Data
CoMACM(R)(u,s,-,rnd)
Move & Optional Round
CoMAX / CoMIN Maximum / Minimum of Operands and Accumulator
CoMOV Memory to Memory Move
CoMUL(u,s,-,rnd) (Un)Signed/(Un)Signed multiply & Optional Round
CoNEG(rnd) Negate Accumulator & Optional Round
CoNOP No-Operation
CoRND Round Accumulator
CoSHL / CoSHR Accumulator Logical Shift Left / Right
CoSTORE Store a MAC Unit Register
CoSUB(2,R) Substraction

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External bus controller ST10F272

8 External bus controller

All of the external memory accesses are performed by the on-chip external bus controller.
The EBC can be programmed to single chip mode when no external memory is required, or
to one of four different external memory access modes:
● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
● 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
● 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
● 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use
PORT0 for input / output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are programmable giving the choice of a wide
range of memories and external peripherals.
Up to four independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics.
These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3
and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these four address windows are controlled by
BUSCON0. Up to five external CS signals (four windows plus default) can be generated in
order to save external glue logic. Access to very slow memories is supported by a ‘Ready’
function.
A HOLD / HLDA protocol is available for bus arbitration which shares external resources
with other bus masters.
The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN
once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In
master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the
slave mode is selected where pin HLDA is switched to input. This directly connects the slave
controller to another master controller without glue logic.
For applications which require less external memory space, the address space can be
restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an
address space of 16M Bytes is used, otherwise four, two or no address lines.
Chip select timing can be made programmable. By default (after reset), the CSx lines
change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the
SYSCON register the CSx lines change with the rising edge of ALE.
The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers.
When the READY function is enabled for a specific address window, each bus cycle within
the window must be terminated with the active level defined by bit RDYPOL in the
associated BUSCON register.

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ST10F272 Interrupt system

9 Interrupt system

The interrupt response time for internal program execution is from 78ns to 187.5ns at
64 MHz CPU clock.
The ST10F272 architecture supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources (internal or external) to the
microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or
by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’
from the current CPU activity to perform a PEC service. A PEC service implies a single Byte
or Word data transfer between any two memory locations with an additional increment of
either the PEC source or destination pointer. An individual PEC transfer counter is implicitly
decremented for each PEC service except when performing in the continuous transfer
mode. When this counter reaches zero, a standard interrupt is performed to the
corresponding source related vector location. PEC services are very well suited to perform
the transmission or the reception of blocks of data. The ST10F272 has 8 PEC channels,
each of them offers such fast interrupt-driven data transfer capabilities.
An interrupt control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its
related register, each source can be programmed to one of sixteen interrupt priority levels.
Once starting to be processed by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge,
falling edge or both edges).
Fast external interrupts may also have interrupt sources selected from other peripherals; for
example the CANx controller receive signals (CANx_RxD) and I2C serial clock signal can be
used to interrupt the system.
Table 28 shows all the available ST10F272 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Table 28. Interrupt sources

Source of Interrupt or Request Enable Interrupt Vector Trap
PEC Service Request Flag Flag Vector Location Number

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h

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Table 28. Interrupt sources (continued)

Source of Interrupt or Request Enable Interrupt Vector Trap
PEC Service Request Flag Flag Vector Location Number

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h

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ST10F272 Interrupt system

Table 28. Interrupt sources (continued)

Source of Interrupt or Request Enable Interrupt Vector Trap
PEC Service Request Flag Flag Vector Location Number

GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h

GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
See Paragraph 9.1 XP0IR XP0IE XP0INT 00’0100h 40h
See Paragraph 9.1 XP1IR XP1IE XP1INT 00’0104h 41h
See Paragraph 9.1 XP2IR XP2IE XP2INT 00’0108h 42h
See Paragraph 9.1 XP3IR XP3IE XP3INT 00’010Ch 43h

Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.

9.1 X-Peripheral interrupt

The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next Figure 9, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
● Byte High XIRxSEL[15:8] Interrupt Enable bits
● Byte Low XIRxSEL[7:0] Interrupt Flag bits
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL
register) define a mask which controls which sources will be associated with the unique

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available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also
provide information about events which are not currently serviced by the interrupt controller
(since masked through the enable bits), allowing an effective software management also in
absence of the possibility to serve the related interrupt request: a periodic polling of the flag
bits may be implemented inside the user application.

Figure 9. X-Interrupt basic structure

7 0
Flag[7:0] XIRxSEL[7:0] (x = 0, 1, 2, 3)

IT Source 7

IT Source 6

IT Source 5

IT Source 4
XPxIC.XPxIR (x = 0, 1, 2, 3)
IT Source 3

IT Source 2

IT Source 1

IT Source 0

Enable[7:0] XIRxSEL[15:8] (x = 0, 1, 2, 3)
15 8

The Table 29 summarizes the mapping of the different interrupt sources which shares the
four X-interrupt vectors.

Table 29. X-Interrupt detailed mapping

XP0INT XP1INT XP2INT XP3INT

CAN1 Interrupt x x

CAN2 Interrupt x x

I2C Receive x x x

I2C Transmit x x x

I2C Error x

SSC1 Receive x x x

SSC1 Transmit x x x

SSC1 Error x

ASC1 Receive x x x

ASC1 Transmit x x x

ASC1 Transmit Buffer x x x

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Table 29. X-Interrupt detailed mapping (continued)

XP0INT XP1INT XP2INT XP3INT

ASC1 Error x

PLL Unlock / OWD x

PWM1 Channel 3...0 x x

9.2 Exception and error traps list

Table 30 shows all of the possible exceptions or error conditions that can arise during run-
time.

Table 30. Trap priorities

Trap Trap Vector Trap Trap*
Exception Condition
Flag Vector Location Number Priority

Reset Functions:
Hardware Reset RESET 00’0000h 00h III
Software Reset RESET 00’0000h 00h III
Watchdog Timer Overflow RESET 00’0000h 00h III
Class A Hardware Traps:
Non-Maskable Interrupt NMI NMITRAP 00’0008h 02h II
Stack Overflow STKOF STOTRAP 00’0010h 04h II
Stack Underflow STKUF STUTRAP 00’0018h 06h II
Class B Hardware Traps:
Undefined Opcode UNDOPC BTRAP 00’0028h 0Ah I
MAC Interruption MACTRP BTRAP 00’0028h 0Ah I
Protected Instruction Fault PRTFLT BTRAP 00’0028h 0Ah I
Illegal word Operand Access ILLOPA BTRAP 00’0028h 0Ah I
Illegal Instruction Access ILLINA BTRAP 00’0028h 0Ah I
Illegal External Bus Access ILLBUS BTRAP 00’0028h 0Ah I
Reserved [002Ch - 003Ch] [0Bh - 0Fh]
Any Current
Software Traps Any
0000h – 01FCh CPU
TRAP Instruction [00h - 7Fh]
in steps of 4h Priority

Note: * - All the class B traps have the same trap number (and vector) and the same lower priority
compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the
second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are
serviced.

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10 Capture / compare (CAPCOM) units

The ST10F272 has two 16-channel CAPCOM units which support generation and control of
timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 MHz CPU
clock.
The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases
for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows precise
adjustments to application specific requirements. In addition, external count inputs for
CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers
relative to external events.
Each of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7
or T8, respectively), and programmed for capture or compare functions. Each of the 32
registers has one associated port pin which serves as an input pin for triggering the capture
function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents
of the allocated timer will be latched (captured) into the capture/compare register in
response to an external event at the port pin which is associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition at
the pin can be selected as the triggering event. The contents of all registers which have
been selected for one of the five compare modes are continuously compared with the
contents of the allocated timers.
When a match occurs between the timer value and the value in a capture / compare
register, specific actions will be taken based on the selected compare mode.
The input frequencies fTx, for the timer input selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies, resolution and periods which result from the
selected pre-scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in
the Table 32 and Table 33 respectively.
The numbers for the timer periods are based on a reload value of 0000h. Note that some
numbers may be rounded to 3 significant figures.

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ST10F272 Capture / compare (CAPCOM) units

Table 31. Compare modes

Compare
Function
Modes

Interrupt-only compare mode; several compare interrupts per timer period are
Mode 0
possible
Pin toggles on each compare match; several compare events per timer period are
Mode 1
possible
Interrupt-only compare mode; only one compare interrupt per timer period is
Mode 2
generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare
Mode 3
event per timer period is generated
Double Register Two registers operate on one pin; pin toggles on each compare match; several
Mode compare events per timer period are possible.

Table 32. CAPCOM timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection TxI
fCPU = 40 MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler for
8 16 32 64 128 256 512 1024
fCPU

312.5 156.25 78.125 39.1

Input Frequency 5MHz 2.5MHz 1.25MHz 625 kHz
kHz kHz kHz kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
104.8
Period 13.1ms 26.2ms 52.4ms 209.7ms 419.4ms 838.9ms 1.678s
ms

Table 33. CAPCOM timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection TxI
fCPU = 64 MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler for
8 16 32 64 128 256 512 1024
fCPU

Input Frequency 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs
Period 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms 1.049s

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General purpose timer unit ST10F272

11 General purpose timer unit

The GPT unit is a flexible multifunctional timer/counter structure which is used for time
related tasks such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized
into two separate modules GPT1 and GPT2. Each timer in each module may operate
independently in several different modes, or may be concatenated with another timer of the
same module.

11.1 GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode.
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a
programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input.
Table 34 and Table 35 list the timer input frequencies, resolution and periods for each pre-
scaler option at 40MHz and 64MHz CPU clock respectively.
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /
underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3.

Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T2I / T3I / T4I
fCPU = 40 MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler
8 16 32 64 128 256 512 1024
factor
1.25 312.5 156.25 78.125
Input frequency 5MHz 2.5MHz 625 kHz 39.1 kHz
MHz kHz kHz kHz

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ST10F272 General purpose timer unit

Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T2I / T3I / T4I
fCPU = 40 MHz
000b 001b 010b 011b 100b 101b 110b 111b

Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs

Period 104.8
13.1ms 26.2ms 52.4ms 209.7ms 419.4ms 838.9ms 1.678s
maximum ms

Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T2I / T3I / T4I
fCPU = 64 MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler
8 16 32 64 128 256 512 1024
factor
Input Freq 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs
Period
8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms 1.049s
maximum
Figure 10. Block diagram of GPT1
T2EUD U/D

GPT1 Timer T2 Interrupt

CPU Clock T2 Request
2n n=3...10
Mode
T2IN Control
Reload
Capture

CPU Clock
2n n=3...10 T3 T3OUT
T3IN Mode GPT1 Timer T3 T3OTL
Control
U/D
T3EUD
Capture
T4 Reload Interrupt
T4IN Mode Request
CPU Clock Control
2n n=3...10
GPT1 Timer T4 Interrupt
Request
T4EUD U/D

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General purpose timer unit ST10F272

11.2 GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 36 and Table 37 list the timer input frequencies, resolution and periods for each pre-
scaler option at 40MHz and 64MHz CPU clock respectively.

Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T5I / T6I
fCPU = 40MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler
4 8 16 32 64 128 256 512
factor
1.25 312.5 156.25 78.125
Input Freq 10MHz 5MHz 2.5MHz 625 kHz
MHz kHz kHz kHz
Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs
Period
6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms
maximum

Table 37. GPT2 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T5I / T6I
fCPU = 64MHz
000b 001b 010b 011b 100b 101b 110b 111b

Pre-scaler
4 8 16 32 64 128 256 512
factor
Input Freq 16MHz 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz
Resolution 62.5ns 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs
Period
4.1ms 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms
maximum

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ST10F272 General purpose timer unit

Figure 11. Block diagram of GPT2

T5EUD
U/D
CPU Clock 2n n=2...9 T5
GPT2 Timer T5 Interrupt
Mode Request
T5IN Control Clear

Capture
Interrupt
CAPIN Request
GPT2 CAPREL

Reload Interrupt
Request

T6IN Toggle FF
T6
CPU Clock Mode GPT2 Timer T6 T60TL T6OUT
2n n=2...9 Control
U/D to CAPCOM
T6EUD Timers

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PWM modules ST10F272

12 PWM modules

Two pulse width modulation modules are available on ST10F272: standard PWM0 and
XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned
or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and
single shot outputs. The Table 38 and Table 39 show the PWM frequencies for different
resolutions. The level of the output signals is selectable and the PWM modules can
generate interrupt requests.

Figure 12. Block diagram of PWM module

PPx Period Register *

Match
Comparator

Clock 1 Input PTx * Up/Down/

Clock 2 Control 16-bit Up/Down Counter Clear Control
Run

Match
Comparator Output Control POUTx
Enable

Shadow Register Write Control

* User readable / writeable register PWx Pulse Width Register *

Table 38. PWM unit frequencies and resolutions at 40 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU Clock/1 25ns 156.25 kHz 39.1 kHz 9.77 kHz 2.44Hz 610Hz
CPU
1.6µs 2.44 kHz 610Hz 152.6Hz 38.15Hz 9.54Hz
Clock/64

Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU Clock/1 25ns 78.12 kHz 19.53 kHz 4.88 kHz 1.22 kHz 305.2Hz
CPU
1.6µs 1.22 kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz
Clock/64

Table 39. PWM unit frequencies and resolutions at 64 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU Clock/1 15.6ns 250 kHz 62.5 kHz 15.63 kHz 3.91Hz 977Hz
CPU
1.0µs 3.91 kHz 976.6Hz 244.1Hz 61.01Hz 15.26Hz
Clock/64

Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU Clock/1 15.6ns 125 kHz 31.25 kHz 7.81 kHz 1.95 kHz 488.3Hz
CPU
1.0µs 1.95 kHz 488.28Hz 122.07Hz 30.52Hz 7.63Hz
Clock/64

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ST10F272 Parallel ports

13 Parallel ports

13.1 Introduction
The ST10F272 MCU provides up to 111 I/O lines with programmable features. These
capabilities bring very flexible adaptation of this MCU to wide range of applications.
ST10F272 has nine groups of I/O lines gathered as follows:
● Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high
as most significant byte)
● Port 1 is a two time 8-bit port named P1L and P1H
● Port 2 is a 16-bit port
● Port 3 is a 15-bit port (P3.14 line is not implemented)
● Port 4 is a 8-bit port
● Port 5 is a 16-bit port input only
● Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software
controlled with dedicated registers.
For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bit-
wise) for push-pull or open drain operation using ODPx registers.
The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of
a pin is clocked into the input latch once per state time, regardless whether the port is
configured for input or output. The threshold is selected with PICON and XPICON registers
control bits.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A read-
modify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
I/O lines support an alternate function which is detailed in the following description of each
port.

13.2 I/O’s special features

13.2.1 Open drain mode

Some of the I/O ports of ST10F272 support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to get an AND wired logical
function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections),
and is controlled through the respective Open Drain Control Registers ODPx.

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13.2.2 Input threshold control

The standard inputs of the ST10F272 determine the status of input signals according to TTL
levels. In order to accept and recognize noisy signals, CMOS input thresholds can be
selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds
are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs
from toggling while the respective input signal level is near the thresholds.
The Port Input Control registers PICON and XPICON are used to select these thresholds for
each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and
P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each.
All options for individual direction and output mode control are available for each pin,
independent of the selected input threshold.

13.3 Alternate port functions

Each port line has one associated programmable alternate input or output function.
● PORT0 and PORT1 may be used as address and data lines when accessing external
memory. Besides, PORT1 provides also:
– Input capture lines
– 8 additional analog input channels to the A/D converter
● Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module
and of the ASC1.
Port 2 is also used for fast external interrupt inputs and for timer 7 input.
● Port 3 includes the alternate functions of timers, serial interfaces, the optional bus
control signal BHE and the system clock output (CLKOUT).
● Port 4 outputs the additional segment address bit A23...A16 in systems where more
than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I2C
lines are provided.
● Port 5 is used as analog input channels of the A/D converter or as timer control signals.
● Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals and the SSC1 lines.
If the alternate output function of a pin is to be used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset
and are configured automatically. Otherwise the pin remains in the high-impedance state
and is not effected by the alternate output function. The respective port latch should hold a
‘1’, because its output is ANDed with the alternate output data (except for PWM output
signals).
If the alternate input function of a pin is used, the direction of the pin must be programmed
for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default
after reset. If no external device is connected to the pin, however, one can also set the
direction for this pin to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be
used for testing purposes to allow a software trigger of an alternate input function by writing
to the port output latch.
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin.

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ST10F272 Parallel ports

This is done by setting or clearing the direction control bit DPx.y of the pin before enabling
the alternate function.
There are port lines, however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be
switched several times for an instruction fetch in order to output the addresses and to input
the data.
Obviously, this cannot be done through instructions. In these cases, the direction of the port
line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate level of the port output latches check how the alternate data
output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port lines
with only an alternate output function, however, have different structures due to the way the
direction of the pin is switched and depending on whether the pin is accessible by the user
software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines.

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A/D converter ST10F272

14 A/D converter

A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is
integrated on-chip. An automatic self-calibration adjusts the A/D converter module to
process parameter variations at each reset event. The sample time (for loading the
capacitors) and the conversion time is programmable and can be adjusted to the external
circuitry.
The ST10F272 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection
between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for
a detailed description.
A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog
channels (with higher restrictions when overload conditions occur); in particular, Port 5
channels are more accurate than the Port 1 ones. Refer to Electrical Characteristic section
for details.
The A/D converter input bandwidth is limited by the achievable accuracy: supposing a
maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other
causes), in worst case of temperature and process, the maximum frequency for a sine wave
analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation
on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be
reduced to 800 Hz.
If static signal is applied during sampling phase, series resistance shall not be greater than
20kΩ (this taking into account eventual input leakage). It is suggested to not connect any
capacitance on analog input pins, in order to reduce the effect of charge partitioning (and
consequent voltage drop error) between the external and the internal capacitance: in case
an RC filter is necessary the external capacitance must be greater than 10nF to minimize
the accuracy impact.
Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt
request is generated when the result of a previous conversion has not been read from the
result register at the time the next conversion is complete, or the next conversion is
suspended until the previous result has been read. For applications which require less than
16+8 analog input channels, the remaining channel inputs can be used as digital input port
pins.
The A/D converter of the ST10F272 supports different conversion modes:
● Single channel single conversion: The analog level of the selected channel is
sampled once and converted. The result of the conversion is stored in the ADDAT
register.
● Single channel continuous conversion: The analog level of the selected channel is
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
register.
● Auto scan single conversion: The analog level of the selected channels are sampled
once and converted. After each conversion the result is stored in the ADDAT register.
The data can be transferred to the RAM by interrupt software management or using the
powerful Peripheral Event Controller (PEC) data transfer.
● Auto scan continuous conversion: The analog level of the selected channels are
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT

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ST10F272 A/D converter

register. The data can be transferred to the RAM by interrupt software management or
using the PEC data transfer.
● Wait for ADDAT read mode: When using continuous modes, in order to avoid to
overwrite the result of the current conversion by the next one, the ADWR bit of ADCON
control register must be activated. Then, until the ADDAT register is read, the new
result is stored in a temporary buffer and the conversion is on hold.
● Channel injection mode: When using continuous modes, a selected channel can be
converted in between without changing the current operating mode. The 10-bit data of
the conversion are stored in ADRES field of ADDAT2. The current continuous mode
remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630
CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It
compensates the capacitance mismatch, so the calibration procedure does not need any
update during normal operation.
No conversion can be performed during this time: the bit ADBSY shall be polled to verify
when the calibration is over, and the module is able to start a convertion.

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Serial channels ST10F272

15 Serial channels

Serial communication with other microcontrollers, microprocessors, terminals or external

peripheral components is provided by up to four serial interfaces: two asynchronous /
synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial
channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates
without the requirement of oscillator tuning. For transmission, reception and erroneous
reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A
more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and
SSC1 (XBUS mapped).

15.1 Asynchronous / synchronous serial interfaces

The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial
communication between the ST10F272 and other microcontrollers, microprocessors or
external peripherals.

15.2 ASCx in asynchronous mode

In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop
bits can be selected. Parity framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. Full-
duplex communication up to 2M Bauds (at 64 MHz of fCPU) is supported in this mode.

Table 40. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz

Reload Value Reload Value

Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error
(hex) (hex)

1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007
56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E
38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015
19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B
9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056
4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD
2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B
1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056B / 056C
300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9
153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9

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ST10F272 Serial channels

Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = ‘0’, fCPU = 64 MHz S0BRS = ‘1’, fCPU = 64 MHz

Reload Value Reload Value

Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error
(hex) (hex)

2 000 000 0.0% / 0.0% 0000 / 0000 1 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 0010 / 0011 112 000 +6.3% / -7.0% 000A / 000B
56 000 +1.5% / -3.0% 0022 / 0023 56 000 +6.3% / -0.8% 0016 / 0017
38 400 +1.7% / -1.4% 0033 / 0034 38 400 +3.3% / -1.4% 0021 / 0022
19 200 +0.2% / -1.4% 0067 / 0068 19 200 +0.9% / -1.4% 0044 / 0045
9 600 +0.2% / -0.6% 00CF / 00D0 9 600 +0.9% / -0.2% 0089 / 008A
4 800 +0.2% / -0.2% 019F / 01A0 4 800 +0.4% / -0.2% 0114 / 0115
2 400 +0.2% / 0.0% 0340 / 0341 2 400 +0.1% / -0.2% 022A / 015B
1 200 0.1% / 0.0% 0681 / 0682 1 200 +0.1% / -0.1% 0456 / 0457
600 0.0% / 0.0% 0D04 / 0D05 600 +0.1% / 0.0% 08AD / 08AE
300 0.0% / 0.0% 1A09 / 1A0A 300 0.0% / 0.0% 115B / 115C
245 0.0% / 0.0% 1FE2 / 1FE3 163 0.0% / 0.0% 1FF2 / 1FF3

Note: The deviation errors given in the Table 40 and Table 41 are rounded. To avoid deviation
errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).

15.3 ASCx in synchronous mode

In synchronous mode, data is transmitted or received synchronously to a shift clock which is
generated by the ST10F272. Half-duplex communication up to 8M Baud (at 40 MHz of fCPU)
is possible in this mode.

Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz

Reload Value Reload Value

Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error
(hex) (hex)

5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D
56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B
38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056
19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD
9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B
4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6
2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056B / 056C
1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9

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Serial channels ST10F272

Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz

Reload Value Reload Value

Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error
(hex) (hex)

900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3
612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE

Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = ‘0’, fCPU = 64 MHz S0BRS = ‘1’, fCPU = 64 MHz

Reload Value Reload Value

Baud Rate (Baud) Deviation Error Baud Rate (Baud) Deviation Error
(hex) (hex)

8 000 000 0.0% / 0.0% 0000 / 0000 5 333 333 0.0% / 0.0% 0000 / 0000
112 000 +0.6% / -0.8% 0046 / 0047 112 000 +1.3% / -0.8% 002E / 002F
56 000 +0.6% / -0.1% 008D / 008E 56 000 +0.3% / -0.8% 005E / 005F
38 400 +0.2% / -0.3% 00CF / 00D0 38 400 +0.6% / -0.1% 0089 / 008A
19 200 +0.2% / -0.1% 019F / 01A0 19 200 +0.3% / -0.1% 0114 / 0115
9 600 +0.0% / -0.1% 0340 / 0341 9 600 +0.1% / -0.1% 022A / 022B
4 800 0.0% / 0.0% 0681 / 0682 4 800 0.0% / -0.1% 0456 / 0457
2 400 0.0% / 0.0% 0D04 / 0D05 2 400 0.0% / 0.0% 08AD / 08AE
1 200 0.0% / 0.0% 1A09 / 1A0A 1 200 0.0% / 0.0% 115B / 115C
977 0.0% / 0.0% 1FFB / 1FFC 900 0.0% / 0.0% 1724 / 1725
652 0.0% / 0.0% 1FF2 / 1FF3

Note: The deviation errors given in the Table 42 and Table 43 are rounded. To avoid deviation
errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency)

15.4 High speed synchronous serial interfaces

The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high-
speed serial communication between the ST10F272 and other microcontrollers,
microprocessors or external peripherals.
The SSCx supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the SSCx itself (master mode) or be received from an
external master (slave mode). Data width, shift direction, clock polarity and phase are
programmable.
This allows communication with SPI-compatible devices. Transmission and reception of data
is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial
clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with
16-bit reload capability, allowing Baud rate generation independent from the timers.

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ST10F272 Serial channels

Table 44 and Table 45 list some possible Baud rates against the required reload values and
the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is
anyway limited to 8Mbaud.

Table 44. Synchronous baud rate and reload values (fCPU = 40 MHz)
Baud Rate Bit Time Reload Value

Reserved --- 0000h

Can be used only with fCPU = 32 MHz (or
--- 0001h
lower)
6.6M Baud 150ns 0002h
5M Baud 200ns 0003h
2.5M Baud 400ns 0007h
1M Baud 1µs 0013h
100K Baud 10µs 00C7h
10K Baud 100µs 07CFh
1K Baud 1ms 4E1Fh
306 Baud 3.26ms FF4Eh

Table 45. Synchronous baud rate and reload values (fCPU = 64 MHz)
Baud Rate Bit Time Reload Value

Reserved --- 0000h

Can be used only with fCPU = 32 MHz (or
--- 0001h
lower)
Can be used only with fCPU = 48 MHz (or
--- 0002h
lower)
8M Baud 125ns 0003h
4M Baud 250ns 0007h
1M Baud 1µs 001Fh
100K Baud 10µs 013Fh
10K Baud 100µs 0C7Fh
1K Baud 1ms 7CFFh
489 Baud 2.04ms FF9Eh

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I2C interface ST10F272

16 I2C interface

The integrated I2C Bus Module handles the transmission and reception of frames over the
two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and transmit
data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
(both Standard and Fast I2C bus modes are supported).
The module can generate three different types of interrupt:
● Requests related to bus events, like start or stop events, arbitration lost, etc.
● Requests related to data transmission
● Requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are
automatically configured as bidirectional open-drain: the value of the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
When the I2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O
controlled by P4, DP4 and ODP4.
The speed of the I2C interface may be selected between Standard mode (0 to 100 kHz) and
Fast I2C mode (100 to 400 kHz).

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ST10F272 CAN modules

17 CAN modules

The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames according to the CAN
specification V2.0 part B (active). It is based on the C-CAN specification.
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers.
Because of duplication of the CAN controllers, the following adjustments are to be
considered:
● Same internal register addresses of both CAN controllers, but with base addresses
differing in address bit A8; separate chip select for each CAN module. Refer to
Chapter 4: Memory organization on page 22.
● The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and
the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
● The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and
the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
● Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS
interrupt lines together with other X-Peripherals sharing the four vectors.
● The CAN modules must be selected with corresponding CANxEN bit of XPERCON
register before the bit XPEN of SYSCON register is set.
● The reset default configuration is: CAN1 enabled, CAN2 disabled.
Note: If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment
address lines. Thus, only four segment address lines can be used, reducing the external
memory space to 5 Mbytes (1 Mbyte per CS line).

17.1 Configuration support

It is possible that both CAN controllers are working on the same CAN bus, supporting
together up to 64 message objects. In this configuration, both receive signals and both
transmit signals are linked together when using the same CAN transceiver. This
configuration is especially supported by providing open drain outputs for the CAN1_Txd and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4:
in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as Open-Drain).
The user is also allowed to map internally both CAN modules on the same pins P4.5 and
P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used
for I2C interface. This is possible by setting bit CANPAR of XMISC register. To access this
register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON
register.

17.2 CAN bus configurations

Depending on application, CAN bus configuration may be one single bus with a single or
multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F272 is
able to support these two cases.

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CAN modules ST10F272

Single CAN bus

The single CAN Bus multiple interfaces configuration may be implemented using two CAN
transceivers as shown in Figure 13.

Figure 13. Connection to single CAN bus via separate CAN transceivers

XMISC.CANPAR = 0

CAN1 CAN2
RX TX RX TX

P4.5 P4.6 P4.4 P4.7

CAN CAN
Transceiver Transceiver

CAN_H
CAN bus
CAN_L

The ST10F272 also supports single CAN Bus multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in Figure 14. Thanks to the OR-Wired
Connection, only one transceiver is required. In this case the design of the application must
take in account the wire length and the noise environment.

Figure 14. Connection to single CAN bus via common CAN transceivers
XMISC.CANPAR = 0

CAN1 CAN2
RX TX RX TX
+5V

P4.5 P4.6 P4.4 P4.7

2.7kW OD OD

CAN
Transceiver

CAN_H
CAN bus OD = Open Drain Output
CAN_L

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ST10F272 CAN modules

Multiple CAN bus

The ST10F272 provides two CAN interfaces to support such kind of bus configuration as
shown in Figure 15.

Figure 15. Connection to two different CAN buses (e.g. for gateway application)

XMISC.CANPAR = 0
CAN1 CAN2
RX TX RX TX

P4.5 P4.6 P4.4 P4.7

CAN CAN
Transceiver Transceiver

CAN_H CAN_H
CAN_L CAN_L
CAN bus 1 CAN bus 2

Parallel Mode
In addition to previous configurations, a parallel mode is supported. This is shown in
Figure 16.

Figure 16. Connection to one CAN bus with internal Parallel Mode enabled

XMISC.CANPAR = 1
(Both CAN enabled)
CAN1 CAN2
RX TX RX TX

P4.5 P4.6 P4.4 P4.7

CAN
Transceiver

CAN_H
CAN bus
CAN_L
1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O
while they cannot be used as external bus address lines.

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Real time clock ST10F272

18 Real time clock

The Real Time Clock is an independent timer, in which the clock is derived directly from the
clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator)
so that it can be kept on running even in Idle or Power down mode (if enabled to). Registers
access is implemented onto the XBUS. This module is designed with the following
characteristics:
● Generation of the current time and date for the system
● Cyclic time based interrupt, on Port2 external interrupts every ’RTC basic clock tick’
and after n ’RTC basic clock ticks’ (n is programmable) if enabled
● 58-bit timer for long term measurement
● Capability to exit the ST10 chip from Power down mode (if PWDCFG of SYSCON set)
after a programmed delay
The real time clock is based on two main blocks of counters. The first block is a prescaler
which generates a basic reference clock (for example a 1 second period). This basic
reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input
clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit
counter is loaded at each basic reference clock period with the value of the 20-bit
PRESCALER register. The value of the 20-bit RTCP register determines the period of the
basic reference clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The
second block of the RTC is a 32-bit counter that may be initialized with the current system
time. This counter is driven with the basic reference clock signal. In order to provide an
alarm function the contents of the counter is compared with a 32-bit alarm register. The
alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI),
may be generated when the value of the counter matches the alarm register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external
interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power
down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock
oscillator when entering the power down mode.
The last function implemented in the RTC is to switch off the main on-chip oscillator and the
32 kHz on chip oscillator if the ST10 enters the Power Down mode, so that the chip can be
fully switched off (if RTC is disabled).
At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 /
XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference
clock: when Power Down mode is entered, the RTC can either be stopped or left running,
and in both the cases the main oscillator is turned off, reducing the power consumption of
the device to the minimum required to keep on running the RTC counter and relative
reference oscillator. This is valid also if Stand-by mode is entered (switching off the main
supply VDD), since both the RTC and the low power oscillator (32 kHz) are biased by the
VSTBY. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main
oscillator drives the RTC counter, and since it is powered by the main power supply, it
cannot be maintained running in Stand-by mode, while in Power Down mode the main
oscillator is maintained running to provide the reference to the RTC module (if not disabled).

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ST10F272 Watchdog timer

19 Watchdog timer

The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in
the time interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is always monitored. The software must be designed
to service the watchdog timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the watchdog timer overflows and generates an internal
hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components
to be reset.
Each of the different reset sources is indicated in the WDTCON register:
● Watchdog Timer Reset in case of an overflow
● Software Reset in case of execution of the SRST instruction
● Short, Long and Power-On Reset in case of hardware reset (and depending of reset
pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be
identified during the initialization phase.
The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high
Byte of the watchdog timer register can be set to a pre-specified reload value (stored in
WDTREL).
Each time it is serviced by the application software, the high byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
The Table 46 and Table 47 show the watchdog time range for 40 MHz and 64 MHz CPU
clock respectively.

Table 46. WDTREL reload value (fCPU = 40 MHz)

Prescaler for fCPU = 40 MHz
Reload value in WDTREL
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)

FFh 12.8µs 819.2µs

00h 3.277ms 209.7ms

Table 47. WDTREL reload value (fCPU = 64 MHz)

Prescaler for fCPU = 64 MHz
Reload value in WDTREL
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)

FFh 8µs 512µs

00h 2.048ms 131.1ms

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System reset ST10F272

20 System reset

System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in Table 48.

Table 48. Reset event definition

RPD
Reset Source Flag Conditions
Status

Power-on reset PONR Low Power-on

Asynchronous Hardware reset Low tRSTIN > 1)
Synchronous Long Hardware LHWR tRSTIN > (1032 + 12) TCL + max(4 TCL,
High
reset 500ns)
tRSTIN > max(4 TCL, 500ns)
Synchronous Short Hardware
SHWR High tRSTIN ≤ (1032 + 12) TCL + max(4 TCL,
reset
500ns)
Watchdog Timer reset WDTR 3)
WDT overflow
3)
Software reset SWR SRST instruction execution

1) RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2)
See next Section 20.1 for more details on minimum reset pulse duration.
3)
The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4, 20.5 and 20.6).

20.1 Input filter

On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
● For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500ns).
● For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.

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20.2 Asynchronous reset

An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low
level. Then the ST10F272 is immediately (after the input filter delay) forced in reset default
state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all
internal/external bus cycles, it switches buses (data, address and control signals) and I/O
pin drivers to high-impedance, it pulls high Port0 pins.
Note: If an asynchronous reset occurs during a read or write phase in internal memories, the
content of the memory itself could be corrupted: to avoid this, synchronous reset usage is
strongly recommended.

Power-on reset
The asynchronous reset must be used during the power-on of the device. Depending
on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to
stabilize (Refer to Electrical Characteristics Section), with an already stable VDD. The logic
of the ST10F272 does not need a stabilized clock signal to detect an asynchronous reset,
so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin
and the RPD pin must be held at low level until the device clock signal is stabilized and the
system configuration value on Port0 is settled.
At Power-on it is important to respect some additional constraints introduced by the start-up
phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V
for the core logic: this time is computed from when the external reference (VDD) becomes
stable (inside specification range, that is at least 4.5V). This is a constraint for the
application hardware (external voltage regulator): the RSTIN pin assertion shall be extended
to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded FLASH. When booting from internal
memory, starting from RSTIN releasing, it needs a maximum of 1ms for its initialization:
before that, the internal reset (RST signal) is not released, so the CPU does not start code
execution in internal memory.
Note: This is not true if external memory is used (pin EA held low during reset phase). In this case,
once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the
internal reset signal RST is released as well, so the code execution can start immediately
after. Obviously, an eventual access to the data in internal Flash is forbidden before its
initialization phase is completed: an eventual access during starting phase will return FFFFh
(just at the beginning), while later 009Bh (an illegal opcode trap can be generated).
At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the start-
up time of the main oscillator (tSTUP = 1ms for resonator, 10ms for crystal) and PLL
synchronization time (tPSUP = 200µs): this means that if the internal FLASH is used, the
RSTIN pin could be released before the main oscillator and PLL are stable to recover some
time in the start-up phase (FLASH initialization only needs stable V18, but does not need
stable system clock since an internal dedicated oscillator is used).

Warning: It is recommended to provide the external hardware with a

current limitation circuitry. This is necessary to avoid
permanent damages of the device during the power-on
transient, when the capacitance on V18 pin is charged. For
the on-chip voltage regulator functionality 10nF are

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sufficient: anyway, a maximum of 100nF on V18 pin should

not generate problems of over-current (higher value is
allowed if current is limited by the external hardware).
External current limitation is anyway recommended also to
avoid risks of damage in case of temporary short between
V18 and ground: the internal 1.8V drivers are sized to drive
currents of several tens of Ampere, so the current shall be
limited by the external hardware. The limit of current is
imposed by power dissipation considerations (Refer to
Electrical Characteristics Section).

In next Figures 17 and 18 Asynchronous Power-on timing diagrams are reported,

respectively with boot from internal or external memory, highlighting the reset phase
extension introduced by the embedded FLASH module when selected.
Note: Never power the device without keeping RSTIN pin grounded: the device could enter in
unpredictable states, risking also permanent damages.

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Figure 17. Asynchronous power-on RESET (EA = 1)

≤ 1.2 ms (for resonator oscillation + PLL stabilization)
≤ 10.2 ms (for crystal oscillation + PLL stabilization)

≥ 1 ms (for on-chip VREG stabilization)

VDD
≤ 2 TCL

V18

XTAL1 ...

RPD

RSTIN ≥ 50 ns
≤ 500 ns
RSTF
(After Filter) 3..4 TCL

P0[15:13] transparent not t. not t.

P0[12:2] transparent not t.

P0[1:0] not transparent not t.

7 TCL
IBUS-CS
(Internal)
≤ 1 ms

FLARST

RST

Latching point of Port0 for

system start-up configuration

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Figure 18. Asynchronous power-on RESET (EA = 0)

≥ 1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)

VDD
3..8 TCL1)

V18

XTAL1 ...

RPD

RSTIN
≥ 50 ns
≤ 500 ns
RSTF
(After Filter) 3..4 TCL

P0[15:13] transparent not t.

P0[12:2] transparent not t.

P0[1:0] not transparent not t.

8 TCL

ALE

RST

Latching point of Port0 for

system start-up configuration

Note 1. 3 to 8 TCL depending on clock source selection.

Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Reset circuitry chapter and Figures 30, 31 and 32.
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.

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Figure 19. Asynchronous hardware RESET (EA = 1)

1)
≤ 2 TCL

RPD
≥ 50 ns
≤ 500 ns
RSTIN
≥ 50 ns
≤ 500 ns

RSTF 3..4 TCL

(After Filter)

P0[15:13] not transparent transparent not t. not t.

P0[12:2] not transparent transparent not t.

P0[1:0] not transparent not t.

7 TCL
IBUS-CS
(internal)
≤ 1 ms

FLARST

RST

Latching point of Port0 for

system start-up configuration

Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500ns to take into account of Input Filter on RSTIN pin

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Figure 20. Asynchronous hardware RESET (EA = 0)

1)
3..8 TCL2)

RPD
≥ 50 ns
≤ 500 ns
RSTIN ≥ 50 ns
≤ 500 ns

RSTF
3..4 TCL
(After Filter)

P0[15:13] not transparent transparent not t.

P0[12:2] not transparent transparent not t.

P0[1:0] not transparent not t.

8 TCL

ALE

RST

Latching point of Port0 for

system start-up configuration

Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500ns to take into account of Input Filter on RSTIN pin
Note 2. 3 to 8 TCL depending on clock source selection.

Exit from asynchronous reset state

When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
FLASH is used, the restarting occurs after the embedded FLASH initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F272 starts program execution from memory location
00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 19 and Figure 20.

20.3 Synchronous reset (warm reset)

A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 20.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. Note that this bit is always cleared on power-on or
after a reset sequence.

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Short and long synchronous reset

Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts.
It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is
sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short
Reset is flagged (Refer to Chapter 19 for details on reset flags); if it is recognized still low,
the Long reset is flagged as well. The major difference between Long and Short reset is that
during the Long reset, also P0(15:13) become transparent, so it is possible to change the
clock options.

Warning: In case of a short pulse on RSTIN pin, and when Bidirectional

reset is enabled, the RSTIN pin is held low by the internal
circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is
released, but due to the presence of the input analog filter the
internal input reset signal (RSTF in the drawings) is released
later (from 50 to 500ns). This delay is in parallel with the
additional 8 TCL, at the end of which the internal input reset
line (RSTF) is sampled, to decide if the reset event is Short or
Long. In particular:

● If 8 TCL > 500ns (FCPU < 8 MHz), the reset event is always recognized as Short
● If 8 TCL < 500ns (FCPU > 8 MHz), the reset event could be recognized either as Short
or Long, depending on the real filter delay (between 50 and 500ns) and the CPU
frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long
reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be re-configured. The
port returns not transparent 3-4TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL)
and released exactly at that time.
Note: When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be
recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);
so it might happen that a short reset pulse is not filtered by the analog input filter, but on the
other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would
generate a FLASH reset but not a system reset. In this condition, the FLASH answers
always with FFFFh, which leads to an illegal opcode and consequently a trap event is
generated.

Exit from synchronous reset state

The reset sequence is extended until RSTIN level becomes high. Besides, it is internally
prolonged by the FLASH initialization when EA=1 (internal memory selected). Then, the
code execution restarts. The system configuration is latched from Port0, and ALE, RD and
WR/WRL pins are driven to their inactive level. The ST10F272 starts program execution
from memory location 00'0000h in code segment 0. This starting location will typically point
to the general initialization routine. Timing of synchronous reset sequence are summarized
in Figures 21 and 22 where a Short Reset event is shown, with particular highlighting on the
fact that it can degenerate into Long Reset: the two figures show the behavior when booting
from internal or external memory respectively. Figures 23 and 24 reports the timing of a
typical synchronous Long Reset, again when booting from internal or external memory.

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Synchronous reset and RPD pin

Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a
Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance
(if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage
level on RPD pin reaches the input low threshold (around 2.5V), the reset event becomes
immediately asynchronous. In case of hardware reset (short or long) the situation goes
immediately to the one illustrated in Figure 19. There is no effect if RPD comes again above
the input threshold: the asynchronous reset is completed coherently. To grant the normal
completion of a synchronous reset, the value of the capacitance shall be big enough to
maintain the voltage on RPD pin sufficient high along the duration of the internal reset
sequence.
For a Software or Watchdog reset events, an active synchronous reset is completed
regardless of the RPD status.
It is important to highlight that the signal that makes RPD status transparent under reset is
the internal RSTF (after the noise filter).

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Figure 21. Synchronous short / long hardware RESET (EA = 1)

≤4 TCL4) ≤12 TCL < 1032 TCL

RSTIN 1) 3)

≥ 50 ns ≥ 50 ns ≥ 50 ns ≤ 2 TCL
≤ 500 ns ≤ 500 ns ≤ 500 ns

RSTF
(After Filter)

P0[15:13] not transparent

P0[12:2] not t. transparent not t.

P0[1:0] not transparent not t.

7 TCL
IBUS-CS
(Internal)
≤ 1 ms

FLARST
1024 TCL 8 TCL

RST

At this time RSTF is sampled HIGH or LOW

so it is SHORT or LONG reset
RSTOUT

RPD
2)
VRPD > 2.5V Asynchronous Reset not entered
200µA Discharge

Notes:

1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.

2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),

the asynchronous reset is then immediately entered.

3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.

Bit BDRSTEN is cleared after reset.

4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the

internal filter (refer to Section 21.1).

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Figure 22. Synchronous short / long hardware RESET (EA = 0)

≤4 TCL5) ≤12 TCL < 1032 TCL

RSTIN 1) 4)
≥ 50 ns ≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns ≤ 500 ns

RSTF
(After Filter)

P0[15:13] not transparent

P0[12:2] not t. transparent not t.

P0[1:0] not transparent not t.

3..8 TCL3) 8 TCL

ALE

1024 TCL 8 TCL

RST

At this time RSTF is sampled HIGH or LOW

so it is SHORT or LONG reset
RSTOUT

RPD
2) VRPD > 2.5V Asynchronous Reset not entered
200mA Discharge

Notes:
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation)
the asynchronous reset is then immediately entered.
3. 3 to 8 TCL depending on clock source selection.
4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).

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Figure 23. Synchronous long hardware RESET (EA = 1)

≤4 TCL2) ≤12 TCL 1024+8 TCL

RSTIN
≥ 50 ns ≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns ≤ 500 ns ≤ 2 TCL

RSTF
(After Filter) 3..4 TCL

P0[15:13] not transparent transparent not t.

P0[12:2] not t. transparent not t.

P0[1:0] not transparent not t.

7 TCL
IBUS-CS
(Internal)
≤ 1 ms

FLARST
1024+8 TCL

RST

At this time RSTF is sampled LOW

so it is definitely LONG reset
RSTOUT

RPD
1) VRPD > 2.5V Asynchronous Reset not entered
200µA Discharge

Notes:

1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered. Even if RPD returns above the threshold,
the reset is defnitively taken as asynchronous.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).

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Figure 24. Synchronous long hardware RESET (EA = 0)

4 TCL2) 12 TCL 1024+8 TCL

RSTIN
≥ 50 ns ≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns ≤ 500 ns

RSTF
(After Filter) 3..4 TCL

P0[15:13] not transparent transparent not t.

P0[12:2] transparent not t.

P0[1:0] not transparent not t.

3)
3..8 TCL 8 TCL

ALE

1024+8 TCL

RST

At this time RSTF is sampled LOW

so it is LONG reset
RSTOUT

RPD
1) VRPD > 2.5V Asynchronous Reset not entered
200µA Discharge

Notes:

1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
3. 3 to 8 TCL depending on clock source selection.

20.4 Software reset

A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, e.g. to
leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.

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Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and
29 for bidirectional.

20.5 Watchdog timer reset

When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and
29 for bidirectional.

Figure 25. SW / WDT unidirectional RESET (EA = 1)

RSTIN
≤ 2 TCL

P0[15:13] not transparent

P0[12:8] transparent not t.

P0[7:2] not transparent

P0[1:0] not transparent not t.

7 TCL
IBUS-CS
(Internal)
≤ 1 ms

FLARST
1024 TCL

RST

RSTOUT

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Figure 26. SW / WDT unidirectional RESET (EA = 0)

RSTIN

P0[15:13] not transparent

P0[12:8] transparent not t.

P0[7:2] not transparent

P0[1:0] not transparent not t.

8 TCL

ALE

1024 TCL

RST

RSTOUT

20.6 Bidirectional reset

As shown in the previous sections, the RSTOUT pin is driven active (low level) at the
beginning of any reset sequence (synchronous/asynchronous hardware, software and
watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization
routine, until the protected EINIT instruction (End of Initialization) is completed.
The Bidirectional Reset function is useful when external devices require a reset signal but
cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It
is, for instance, the case of external memory running initialization routine before the
execution of EINIT instruction.
Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It
only can be enabled during the initialization routine, before EINIT instruction is completed.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal,
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence the pull down is released and:
● After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low 8
TCL periods after the internal reset sequence completion (refer to Figure 21 and
Figure 22), the Short Reset becomes a Long Reset. On the contrary, if RSTF is
sampled high the device simply exits reset state.
● After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF
remains still low for at least 4 TCL periods (minimum time to recognize a Short
Hardware reset) after the reset exiting (refer to Figure 27 and Figure 28), the Software
or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains
low for less than 4 TCL, the device simply exits reset state.

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The Bidirectional reset is not effective in case RPD is held low, when a Software or
Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset
event is active and RPD becomes low, the RSTIN pin is immediately released, while the
internal reset sequence is completed regardless of RPD status change (1024 TCL).
Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization
routine.

WDTCON flags
Similarly to what already highlighted in the previous section when discussing about Short
reset and the degeneration into Long reset, similar situations may occur when Bidirectional
reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when
RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed,
so it remains still active (low) for a while. It means that depending on the internal clock
speed, a short reset may be recognized as a long reset: the WDTCON flags are set
accordingly.
Besides, when either Software or Watchdog bidirectional reset events occur, again when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is
recognized high or low: 8TCL after the completion of the internal sequence, the level of
RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and
WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).
Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently
internal signal RSTF) is sufficiently held low by the external hardware to inject a Long
Hardware reset. After this occurrence, the initialization routine is not able to recognize a
Software or Watchdog bidirectional reset event, since a different source is flagged inside
WDTCON register. This phenomenon does not occur when internal FLASH is selected
during reset (EA = 1), since the initialization of the FLASH itself extend the internal reset
duration well beyond the filter delay.
Next Figures 27, 28 and 29 summarize the timing for Software and Watchdog Timer
Bidirectional reset events: In particular Figure 29 shows the degeneration into Hardware
reset.

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Figure 27. SW / WDT bidirectional RESET (EA=1)

RSTIN
≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns

RSTF
(After Filter)

P0[15:13] not transparent

P0[12:8] transparent not t.

P0[7:2] not transparent

P0[1:0] not transparent not t.

≤ 2 TCL 7 TCL
IBUS-CS
(Internal)
≤ 1 ms

FLARST

1024 TCL

RST

RSTOUT

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Figure 28. SW / WDT bidirectional RESET (EA = 0)

RSTIN
≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns

RSTF
(After Filter)

P0[15:13] not transparent

P0[12:8] transparent not t.

P0[7:2] not transparent

P0[1:0] not transparent not t.

8 TCL

ALE

1024 TCL

RST

At this time RSTF is sampled HIGH

so SW or WDT Reset is flagged in WDTCON
RSTOUT

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Figure 29. SW / WDT bidirectional RESET (EA=0) followed by a HW RESET

RSTIN
≥ 50 ns ≥ 50 ns
≤ 500 ns ≤ 500 ns

RSTF
(After Filter)

P0[15:13] not transparent

P0[12:8] transparent not t.

P0[7:2] not transparent

P0[1:0] not transparent not t.

8 TCL

ALE

1024 TCL

RST

At this time RSTF is sampled LOW

so HW Reset is entered
RSTOUT

20.7 Reset circuitry

Internal reset circuitry is described in Figure 32. The RSTIN pin provides an internal pull-up
resistor of 50kΩ to 250kΩ (The minimum reset time must be calculated using the lowest
value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output
internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a
reset signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running codes before EINIT (end of initialization)
instruction is executed. RSTOUT pin is pulled high only when EINIT is executed.
The RPD pin provides an internal weak pull-down resistor which discharges external
capacitor at a typical rate of 200µA. If bit PWDCFG of SYSCON register is set, an internal
pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any
capacitor connected on RPD pin.
The simplest way to reset the ST10F272 is to insert a capacitor C1 between RSTIN pin and
VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between
RPD pin and VDD. The input RSTIN provides an internal pull-up device equalling a resistor of
50kΩ to 250kΩ (the minimum reset time must be determined by the lowest value). Select C1
that produce a sufficient discharge time to permit the internal or external oscillator and / or
internal PLL and the on-chip voltage regulator to stabilize.

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To ensure correct power-up reset with controlled supply current consumption, specially if
clock signal requires a long period of time to stabilize, an asynchronous hardware reset is
required during power-up. For this reason, it is recommended to connect the external R0-C0
circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin
forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up
R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is
turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin
discharging at a typical rate of 100-200µA. With this mechanism, after power-up reset, short
low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted
longer than the time needed for C0 to be discharged by the internal pull-down device, then
the device is forced in an asynchronous reset. This mechanism insures recovery from very
catastrophic failure.

Figure 30. Minimum external reset circuitry

RSTOUT External Hardware

RSTIN +
C1 a) Hardware
Reset

VCC

R0 b) For Power-up
Reset
(and Interruptible
RPD Power Down
+ mode)
C0
ST10F272

The minimum reset circuit of Figure 30 is not adequate when the RSTIN pin is driven from
the ST10F272 itself during software or watchdog triggered resets, because of the capacitor
C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset
sequence, and thus will trigger an asynchronous reset sequence.
Figure 31 shows an example of a reset circuit. In this example, R1-C1 external circuit is only
used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up
reset and to exit from Power Down mode. Diode D1 creates a wired-OR gate connection to
the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2
provides a faster cycle time for repetitive power-on resets.
R2 is an optional pull-up for faster recovery and correct biasing of TTL Open Collector
drivers.

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System reset ST10F272

Figure 31. System reset circuit

VDD

VDD
R2

External Hardware
R1
D2

RSTIN
+
VDD D1 C1

o.d. External
Reset Source
R0
Open Drain Inverter
RPD
+
C0
ST10F272

Figure 32. Internal (simplified) reset circuitry

EINIT Instruction

Clr
Q
RSTOUT
Set

Reset State
Machine
Clock VDD

SRST instruction
Internal Trigger watchdog overflow
Reset RSTIN
Signal Clr
BDRSTEN
Reset Sequence
(512 CPU Clock Cycles)

VDD

Asynchronous
Reset

RPD

From/to Exit Weak Pulldown

Powerdown (~200µA)
Circuit

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ST10F272 System reset

20.8 Reset application examples

Next two timing diagrams (Figure 33 and Figure 34) provides additional examples of
bidirectional internal reset events (Software and Watchdog) including in particular the
external capacitances charge and discharge transients (refer also to Figure 31 for the
external circuit scheme).

Figure 33. Example of software or watchdog bidirectional reset (EA = 1)

00h
EINIT

not transparent

not transparent

not transparent
not transparent

Latching point

Latching point

Latching point
Latching point
3..8 TCL

1Ch

< 4 TCL
Tfilter RST

transparent
< 500 ns

transparent

transparent
1 ms (C1 charge)

0Ch

not transparent
4 TCL

not transparent
1024 TCL (12.8 us)

Tfilter RST
< 500 ns

not transparent
04h

not transparent
VIH

VIL

VIL

WDTCON

P0[15:13]
RSTOUT

P0[12:8]

P0[7:2]

P0[1:0]
RSTIN

RSTF
ideal

RPD

[5:0]
RST

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102/179
System reset

1024 TCL (12.8 us) 1 ms (C1 charge) 3..8 TCL EINIT

RSTOUT

VIH
RSTIN
VIL

RSTF Tfilter RST Tfilter RST

ideal < 500 ns < 500 ns

RPD VIL

RST

4 TCL

WDTCON
[5:0] 04h 0Ch 1Ch 00h

< 4 TCL

P0[15:13] not transparent transparent not transparent

Latching point

P0[12:8] not transparent transparent not transparent

Latching point

P0[7:2] not transparent transparent not transparent

Latching point

P0[1:0] not transparent not transparent

Figure 34. Example of software or watchdog bidirectional reset (EA = 0)

Latching point
ST10F272
ST10F272 System reset

20.9 Reset summary

A summary of the different reset events is reported in the table below.

Table 49. Reset event

RSTIN WDTCON Flags

Asynch.
Synch.
Bidir
RPD
Event EA

SHWR
LHWR

WDTR
PONR

SWR
min max

1 ms (VREG)
1.2 ms
0 0 N Asynch. (Reson. + PLL) - 1 1 1 1 0
10.2 ms
Power-on Reset (Crystal + PLL)
0 1 N Asynch. 1ms (VREG) - 1 1 1 1 0
1 x x FORBIDDEN
x x Y NOT APPLICABLE
0 0 N Asynch. 500ns - 0 1 1 1 0

Hardware Reset 0 1 N Asynch. 500ns - 0 1 1 1 0

(Asynchronous) 0 0 Y Asynch. 500ns - 0 1 1 1 0
0 1 Y Asynch. 500ns - 0 1 1 1 0
1032 + 12 TCL +
1 0 N Synch. max (4 TCL, 500ns) 0 0 1 1 0
max(4 TCL, 500ns)
1032 + 12 TCL +
1 1 N Synch. max (4 TCL, 500ns) 0 0 1 1 0
max(4 TCL, 500ns)
Short Hardware 1032 + 12 TCL +
Reset max (4 TCL, 500ns)
1 0 Y Synch. max(4 TCL, 500ns) 0 0 1 1 0
(Synchronous) (1)
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
max (4 TCL, 500ns)
1 1 Y Synch. max(4 TCL, 500ns) 0 0 1 1 0
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
1 0 N Synch. - 0 1 1 1 0
max(4 TCL, 500ns)
1032 + 12 TCL +
1 1 N Synch. - 0 1 1 1 0
max(4 TCL, 500ns)
Long Hardware 1032 + 12 TCL +
Reset -
1 0 Y Synch. max(4 TCL, 500ns) 0 1 1 1 0
(Synchronous)
Activated by internal logic only for 1024 TCL
1032 + 12 TCL +
-
1 1 Y Synch. max(4 TCL, 500ns) 0 1 1 1 0
Activated by internal logic only for 1024 TCL

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System reset ST10F272

Table 49. Reset event (continued)

RSTIN WDTCON Flags

Asynch.
Synch.
Bidir
RPD

EA
Event

SHWR
LHWR

WDTR
PONR

SWR
min max

x 0 N Synch. Not activated 0 0 0 1 0

x 0 N Synch. Not activated 0 0 0 1 0
Software Reset (2)
0 1 Y Synch. Not activated 0 0 0 1 0
1 1 Y Synch. Activated by internal logic for 1024 TCL 0 0 0 1 0
x 0 N Synch. Not activated 0 0 0 1 1
x 0 N Synch. Not activated 0 0 0 1 1
Watchdog Reset (2)
0 1 Y Synch. Not activated 0 0 0 1 1
1 1 Y Synch. Activated by internal logic for 1024 TCL 0 0 0 1 1
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
flagged (see Section 20.6 for details).

The start-up configurations and some system features are selected on reset sequences as
described in Table 50 and Figure 35.
Table 50 describes what is the system configuration latched on PORT0 in the six different
reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.

Table 50. PORT0 latched configuration for the different reset events
PORT0
Segm. Addr. Lines
Clock Options

Chip Selects

Adapt Mode
WR config.

Emu Mode
X: Pin is sampled
Reserved

Reserved
Reserved
Bus Type

BSL

-: Pin is not sampled

P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0

Sample event

Software Reset - - - X X X X X X X - - - - - -
Watchdog Reset - - - X X X X X X X - - - - - -
Synchronous Short Hardware Reset - - - X X X X X X X X X X X X X
Synchronous Long Hardware Reset X X X X X X X X X X X X X X X X
Asynchronous Hardware Reset X X X X X X X X X X X X X X X X
Asynchronous Power-On Reset X X X X X X X X X X X X X X X X

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ST10F272 System reset

Figure 35. PORT0 bits latched into the different registers after reset

PORT0
H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0

CLKCFG SALSEL CSSEL WRC BUSTYP BSL Res. ADP EMU

RP0H

CLKCFG SALSEL CSSEL WRC Bootstrap Loader Internal Control Logic

Clock Port 4 Port 6 2

Generator Logic Logic
EA / VSTBY

P0L.7

P0L.7

SYSCON BUSCON0
BUS ALE
ROMEN BYTDIS WRCFG ACT0 CTL0 BTYP

10 9 8 7 10 9 7 6

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Power reduction modes ST10F272

21 Power reduction modes

Three different power reduction modes with different levels of power reduction have been
implemented in the ST10F272. In Idle mode only CPU is stopped, while peripheral still
operate. In Power Down mode both CPU and peripherals are stopped. In Stand-by mode
the main power supply (VDD) can be turned off while a portion of the internal RAM remains
powered via VSTBY dedicated power pin.
Idle and Power Down modes are software activated by a protected instruction and are
terminated in different ways as described in the following sections.
Stand-by mode is entered simply removing VDD, holding the MCU under reset state.
Note: All external bus actions are completed before Idle or Power Down mode is entered.
However, Idle or Power Down mode is not entered if READY is enabled, but has not been
activated (driven low for negative polarity, or driven high for positive polarity) during the last
bus access.

21.1 Idle mode

Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped
and the peripherals still run.
Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not,
the instruction following the IDLE instruction will be executed after return from interrupt
(RETI) instruction, then the CPU resumes the normal program.

21.2 Power down mode

Power Down mode starts by running PWRDN protected instruction. Internal clock is
stopped, all MCU parts are on hold including the watchdog timer. The only exception could
be the Real Time Clock if opportunely programmed and one of the two oscillator circuits as
a consequence (either the main or the 32 kHz on-chip oscillator).
When Real Time Clock module is used, when the device is in Power Down mode a
reference clock is needed. In this case, two possible configurations may be selected by the
user application according to the desired level of power reduction:
● A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4)
and running. In this case the main oscillator is stopped when Power Down mode is
entered, while the Real Time Clock continue counting using 32 kHz clock signal as
reference. The presence of a running low-power oscillator is detected after the Power-
on: this clock is immediately assumed (if present, or as soon as it is detected) as
reference for the Real Time Clock counter and it will be maintained forever (unless
specifically disabled via software).
● Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main
oscillator is not stopped when Power Down is entered, and the Real Time Clock
continue counting using the main oscillator clock signal as reference.
There are two different operating Power Down modes: protected mode and interruptible
mode.

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ST10F272 Power reduction modes

Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set.
Note: Leaving the main voltage regulator active during Power Down may lead to unexpected
behavior (ex: CPU wake-up) and power consumption higher than what specified.

21.2.1 Protected power down mode

This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power Down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.

21.2.2 Interruptible power down mode

This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible Power Down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins, or with an interrupt generated by
the Real Time Clock, or with an interrupt generated by the activity on CAN’s and I2C module
interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low
according the recommendations described in Chapter 20: System reset on page 80.
An external RC circuit must be connected to RPD pin, as shown in the Figure 36.

Figure 36. External RC circuitry on RPD pin

VDD
ST10F272
R0
220kΩ minimum
RPD
+
C0
1µF Typical

To exit Power Down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.

21.3 Stand-by mode

In Stand-by mode, it is possible to turn off the main VDD provided that VSTBY is available
through the dedicated pin of the ST10F272.
To enter Stand-by mode it is mandatory to held the device under reset: once the device is
under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital
interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain
active: the portion of XRAM, the RTC counters and 32 kHz on-chip oscillator amplifier.

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Power reduction modes ST10F272

In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS
during reset to exercise the EA functionality associated with the same pin: the voltage
supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz
oscillator used in conjunction with Real Time Clock module), is granted by the active main
VDD.
It must be noted that Stand-by Mode can generate problems associated with the usage of
different power supplies in CMOS systems; particular attention must be paid when the
ST10F272 I/O lines are interfaced with other external CMOS integrated circuits: if VDD of
ST10F272 becomes (for example in Stand-by Mode) lower than the output level forced by
the I/O lines of these external integrated circuits, the ST10F272 could be directly powered
through the inherent diode existing on ST10F272 output driver circuitry. The same is valid
for ST10F272 interfaced to active/inactive communication buses during Stand-by mode:
current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the
system (not only for the ST10F272 device). The device Stand-by mode current (ISTBY) may
vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD
and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this
phenomenon.

21.3.1 Entering stand-by mode

As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be
cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption.
As a consequence of a RESET event, the RAM Power Supply is switched to the internal
low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator).
The RAM interface will remain frozen until the bit XRAM2EN is set again by software
initialization routine (at next exit from main VDD power-on reset sequence).
Since V18 is falling down (as a consequence of VDD turning off), it can happen that the
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V18. This does not generate any problem, because the Stand-
by Mode switching dedicated circuit continues to confirm the RAM interface freezing,
irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when
internal V18 comes back over internal stand-by reference V18SB.
If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45V
with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a
temporary drop on internal V18 voltage versus internal V18SB during normal code execution,
no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F272 Core module, generating the RAM control signals, is powered by internal
V18 supply; during turning off transient these control signals follow the V18, while RAM is
switched to V18SB internal reference. It could happen that a high level of RAM write strobe
from ST10F272 Core (active low signal) is low enough to be recognized as a logic “0” by the
RAM interface (due to V18 lower than V18SB): The bus status could contain a valid address
for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.

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ST10F272 Power reduction modes

Warning: During power-off phase, it is important that the external

hardware maintains a stable ground level on RSTIN pin,
without any glitch, in order to avoid spurious exiting from
reset status with unstable power supply.

21.3.2 Exiting stand-by mode

After the system has entered the Stand-by Mode, the procedure to exit this mode consists of
a standard Power-on sequence, with the only difference that the RAM is already powered
through V18SB internal reference (derived from VSTBY pin external voltage).
It is recommended to held the device under RESET (RSTIN pin forced low) until external
VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V18 becomes higher than about 1.0V, there
is no warranty that the device stays under reset status if RSTIN is at high level during
power ramp up. So, it is important the external hardware is able to guarantee a stable
ground level on RSTIN along the power-on phase, without any temporary glitch.
The external hardware shall be responsible to drive low the RSTIN pin until the VDD is
stable, even though the internal LVD is active.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to
the main V18.
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.

21.3.3 Real time clock and stand-by mode

When Stand-by mode is entered (turning off the main supply VDD), the Real Time Clock
counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide
the reference to the counter. This is not possible if the main oscillator is used as reference
for the counter: Being the main oscillator powered by VDD, once this is switched off, the
oscillator is stopped.

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Power reduction modes ST10F272

21.3.4 Power reduction modes summary

In the following Table 51: Power reduction modes summary, a summary of the different
Power reduction modes is reported.

Table 51. Power reduction modes summary

STBY XRAM
32 kHz OSC
Peripherals

Main OSC

XRAM
VSTBY

CPU

RTC
VDD
Mode

on on off on off run off biased biased

Idle
on on off on on run on biased biased
on on off off off off off biased biased
Power Down on on off off on on off biased biased
on on off off on off on biased biased
off on off off off off off biased off
Stand-by
off on off off on off on biased off

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ST10F272 Programmable output clock divider

22 Programmable output clock divider

A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address
range.
When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the
CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of
register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15
a prescaled value of the CPU clock can be output.
When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15
does not output any clock signal, even though XCLKOUTDIV register is programmed.

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Register set ST10F272

23 Register set

This section summarizes all registers implemented in the ST10F272, ordered by name.

23.1 Special function registers

The following table lists all SFRs which are implemented in the ST10F272 in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”.
SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column
“Physical Address”.

Table 52. List of special function registers

Physical 8-bit Reset
Name Description
address address value

A/D converter end of conversion interrupt control

ADCIC b FF98h CCh - - 00h
register
ADCON b FFA0h D0h A/D converter control register 0000h
ADDAT FEA0h 50h A/D converter result register 0000h
ADDAT2 F0A0h E 50h A/D converter 2 result register 0000h
ADDRSEL1 FE18h 0Ch Address select register 1 0000h
ADDRSEL2 FE1Ah 0Dh Address select register 2 0000h
ADDRSEL3 FE1Ch 0Eh Address select register 3 0000h
ADDRSEL4 FE1Eh 0Fh Address select register 4 0000h
ADEIC b FF9Ah CDh A/D converter overrun error interrupt control register - - 00h
BUSCON0 b FF0Ch 86h Bus configuration register 0 0xx0h
BUSCON1 b FF14h 8Ah Bus configuration register 1 0000h
BUSCON2 b FF16h 8Bh Bus configuration register 2 0000h
BUSCON3 b FF18h 8Ch Bus configuration register 3 0000h
BUSCON4 b FF1Ah 8Dh Bus configuration register 4 0000h
CAPREL FE4Ah 25h GPT2 capture/reload register 0000h
CC0 FE80h 40h CAPCOM register 0 0000h
CC0IC b FF78h BCh CAPCOM register 0 interrupt control register - - 00h
CC1 FE82h 41h CAPCOM register 1 0000h
CC1IC b FF7Ah BDh CAPCOM register 1 interrupt control register - - 00h
CC2 FE84h 42h CAPCOM register 2 0000h
CC2IC b FF7Ch BEh CAPCOM register 2 interrupt control register - - 00h
CC3 FE86h 43h CAPCOM register 3 0000h
CC3IC b FF7Eh BFh CAPCOM register 3 interrupt control register - - 00h

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ST10F272 Register set

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

CC4 FE88h 44h CAPCOM register 4 0000h

CC4IC b FF80h C0h CAPCOM register 4 interrupt control register - - 00h
CC5 FE8Ah 45h CAPCOM register 5 0000h
CC5IC b FF82h C1h CAPCOM register 5 interrupt control register - - 00h
CC6 FE8Ch 46h CAPCOM register 6 0000h
CC6IC b FF84h C2h CAPCOM register 6 interrupt control register - - 00h
CC7 FE8Eh 47h CAPCOM register 7 0000h
CC7IC b FF86h C3h CAPCOM register 7 interrupt control register - - 00h
CC8 FE90h 48h CAPCOM register 8 0000h
CC8IC b FF88h C4h CAPCOM register 8 interrupt control register - - 00h
CC9 FE92h 49h CAPCOM register 9 0000h
CC9IC b FF8Ah C5h CAPCOM register 9 interrupt control register - - 00h
CC10 FE94h 4Ah CAPCOM register 10 0000h
CC10IC b FF8Ch C6h CAPCOM register 10 interrupt control register - - 00h
CC11 FE96h 4Bh CAPCOM register 11 0000h
CC11IC b FF8Eh C7h CAPCOM register 11 interrupt control register - - 00h
CC12 FE98h 4Ch CAPCOM register 12 0000h
CC12IC b FF90h C8h CAPCOM register 12 interrupt control register - - 00h
CC13 FE9Ah 4Dh CAPCOM register 13 0000h
CC13IC b FF92h C9h CAPCOM register 13 interrupt control register - - 00h
CC14 FE9Ch 4Eh CAPCOM register 14 0000h
CC14IC b FF94h CAh CAPCOM register 14 interrupt control register - - 00h
CC15 FE9Eh 4Fh CAPCOM register 15 0000h
CC15IC b FF96h CBh CAPCOM register 15 interrupt control register - - 00h
CC16 FE60h 30h CAPCOM register 16 0000h
CC16IC b F160h E B0h CAPCOM register 16 interrupt control register - - 00h
CC17 FE62h 31h CAPCOM register 17 0000h
CC17IC b F162h E B1h CAPCOM register 17 interrupt control register - - 00h
CC18 FE64h 32h CAPCOM register 18 0000h
CC18IC b F164h E B2h CAPCOM register 18 interrupt control register - - 00h
CC19 FE66h 33h CAPCOM register 19 0000h
CC19IC b F166h E B3h CAPCOM register 19 interrupt control register - - 00h
CC20 FE68h 34h CAPCOM register 20 0000h
CC20IC b F168h E B4h CAPCOM register 20 interrupt control register - - 00h

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Register set ST10F272

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

CC21 FE6Ah 35h CAPCOM register 21 0000h

CC21IC b F16Ah E B5h CAPCOM register 21 interrupt control register - - 00h
CC22 FE6Ch 36h CAPCOM register 22 0000h
CC22IC b F16Ch E B6h CAPCOM register 22 interrupt control register - - 00h
CC23 FE6Eh 37h CAPCOM register 23 0000h
CC23IC b F16Eh E B7h CAPCOM register 23 interrupt control register - - 00h
CC24 FE70h 38h CAPCOM register 24 0000h
CC24IC b F170h E B8h CAPCOM register 24 interrupt control register - - 00h
CC25 FE72h 39h CAPCOM register 25 0000h
CC25IC b F172h E B9h CAPCOM register 25 interrupt control register - - 00h
CC26 FE74h 3Ah CAPCOM register 26 0000h
CC26IC b F174h E BAh CAPCOM register 26 interrupt control register - - 00h
CC27 FE76h 3Bh CAPCOM register 27 0000h
CC27IC b F176h E BBh CAPCOM register 27 interrupt control register - - 00h
CC28 FE78h 3Ch CAPCOM register 28 0000h
CC28IC b F178h E BCh CAPCOM register 28 interrupt control register - - 00h
CC29 FE7Ah 3Dh CAPCOM register 29 0000h
CC29IC b F184h E C2h CAPCOM register 29 interrupt control register - - 00h
CC30 FE7Ch 3Eh CAPCOM register 30 0000h
CC30IC b F18Ch E C6h CAPCOM register 30 interrupt control register - - 00h
CC31 FE7Eh 3Fh CAPCOM register 31 0000h
CC31IC b F194h E CAh CAPCOM register 31 interrupt control register - - 00h
CCM0 b FF52h A9h CAPCOM Mode Control register 0 0000h
CCM1 b FF54h AAh CAPCOM Mode Control register 1 0000h
CCM2 b FF56h ABh CAPCOM Mode Control register 2 0000h
CCM3 b FF58h ACh CAPCOM mode Control register 3 0000h
CCM4 b FF22h 91h CAPCOM Mode Control register 4 0000h
CCM5 b FF24h 92h CAPCOM Mode Control register 5 0000h
CCM6 b FF26h 93h CAPCOM Mode Control register 6 0000h
CCM7 b FF28h 94h CAPCOM Mode Control register 7 0000h
CP FE10h 08h CPU Context Pointer register FC00h
CRIC b FF6Ah B5h GPT2 CAPREL interrupt control register - - 00h
CSP FE08h 04h CPU Code Segment Pointer register (read only) 0000h
DP0L b F100h E 80h P0L direction control register - - 00h

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ST10F272 Register set

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

DP0H b F102h E 81h P0h direction control register - - 00h

DP1L b F104h E 82h P1L direction control register - - 00h
DP1H b F106h E 83h P1h direction control register - - 00h
DP2 b FFC2h E1h Port 2 direction control register 0000h
DP3 b FFC6h E3h Port 3 direction control register 0000h
DP4 b FFCAh E5h Port 4 direction control register - - 00h
DP6 b FFCEh E7h Port 6 direction control register - - 00h
DP7 b FFD2h E9h Port 7 direction control register - - 00h
DP8 b FFD6h EBh Port 8 direction control register - - 00h
DPP0 FE00h 00h CPU data page pointer 0 register (10-bit) 0000h
DPP1 FE02h 01h CPU data page pointer 1 register (10-bit) 0001h
DPP2 FE04h 02h CPU data page pointer 2 register (10-bit) 0002h
DPP3 FE06h 03h CPU data page pointer 3 register (10-bit) 0003h
EMUCON FE0Ah 05h Emulation control register - - XXh
EXICON b F1C0h E E0h External interrupt control register 0000h
EXISEL b F1DAh E EDh External interrupt source selection register 0000h
IDCHIP F07Ch E 3Eh Device identifier register (n is the device revision) 110nh
IDMANUF F07Eh E 3Fh Manufacturer identifier register 0403h
IDMEM F07Ah E 3Dh On-chip memory identifier register 3040h
IDPROG F078h E 3Ch Programming voltage identifier register 0040h
IDX0 b FF08h 84h MAC unit address pointer 0 0000h
IDX1 b FF0Ah 85h MAC unit address pointer 1 0000h
MAH FE5Eh 2Fh MAC unit accumulator - high word 0000h
MAL FE5Ch 2Eh MAC unit accumulator - low word 0000h
MCW b FFDCh EEh MAC unit control word 0000h
MDC b FF0Eh 87h CPU multiply divide control register 0000h
MDH FE0Ch 06h CPU multiply divide register – high word 0000h
MDL FE0Eh 07h CPU multiply divide register – low word 0000h
MRW b FFDAh EDh MAC unit repeat word 0000h
MSW b FFDEh EFh MAC unit status word 0200h
ODP2 b F1C2h E E1h Port 2 open drain control register 0000h
ODP3 b F1C6h E E3h Port 3 open drain control register 0000h
ODP4 b F1CAh E E5h Port 4 open drain control register - - 00h
ODP6 b F1CEh E E7h Port 6 open drain control register - - 00h

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Register set ST10F272

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

ODP7 b F1D2h E E9h Port 7 open drain control register - - 00h

ODP8 b F1D6h E EBh Port 8 open drain control register - - 00h
ONES b FF1Eh 8Fh Constant value 1’s register (read only) FFFFh
P0L b FF00h 80h PORT0 low register (lower half of PORT0) - - 00h
P0H b FF02h 81h PORT0 high register (upper half of PORT0) - - 00h
P1L b FF04h 82h PORT1 low register (lower half of PORT1) - - 00h
P1H b FF06h 83h PORT1 high register (upper half of PORT1) - - 00h
P2 b FFC0h E0h Port 2 register 0000h
P3 b FFC4h E2h Port 3 register 0000h
P4 b FFC8h E4h Port 4 register (8-bit) - - 00h
P5 b FFA2h D1h Port 5 register (read only) XXXXh
P6 b FFCCh E6h Port 6 register (8-bit) - - 00h
P7 b FFD0h E8h Port 7 register (8-bit) - - 00h
P8 b FFD4h EAh Port 8 register (8-bit) - - 00h
P5DIDIS b FFA4h D2h Port 5 digital disable register 0000h
PECC0 FEC0h 60h PEC channel 0 control register 0000h
PECC1 FEC2h 61h PEC channel 1 control register 0000h
PECC2 FEC4h 62h PEC channel 2 control register 0000h
PECC3 FEC6h 63h PEC channel 3 control register 0000h
PECC4 FEC8h 64h PEC channel 4 control register 0000h
PECC5 FECAh 65h PEC channel 5 control register 0000h
PECC6 FECCh 66h PEC channel 6 control register 0000h
PECC7 FECEh 67h PEC channel 7 control register 0000h
PICON b F1C4h E E2h Port input threshold control register - - 00h
PP0 F038h E 1Ch PWM module period register 0 0000h
PP1 F03Ah E 1Dh PWM module period register 1 0000h
PP2 F03Ch E 1Eh PWM module period register 2 0000h
PP3 F03Eh E 1Fh PWM module period register 3 0000h
PSW b FF10h 88h CPU program status word 0000h
PT0 F030h E 18h PWM module up/down counter 0 0000h
PT1 F032h E 19h PWM module up/down counter 1 0000h
PT2 F034h E 1Ah PWM module up/down counter 2 0000h
PT3 F036h E 1Bh PWM module up/down counter 3 0000h
PW0 FE30h 18h PWM module pulse width register 0 0000h

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ST10F272 Register set

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

PW1 FE32h 19h PWM module pulse width register 1 0000h

PW2 FE34h 1Ah PWM module pulse width register 2 0000h
PW3 FE36h 1Bh PWM module pulse width register 3 0000h
PWMCON0 b FF30h 98h PWM module control register 0 0000h
PWMCON1 b FF32h 99h PWM module control register 1 0000h
PWMIC b F17Eh E BFh PWM module interrupt control register - - 00h
QR0 F004h E 02h MAC unit offset register r0 0000h
QR1 F006h E 03h MAC unit offset register R1 0000h
QX0 F000h E 00h MAC unit offset register X0 0000h
QX1 F002h E 01h MAC unit offset register X1 0000h
RP0H b F108h E 84h System start-up configuration register (read only) - - XXh
S0BG FEB4h 5Ah Serial channel 0 baud rate generator reload register 0000h
S0CON b FFB0h D8h Serial channel 0 control register 0000h
S0EIC b FF70h B8h Serial channel 0 error interrupt control register - - 00h
S0RBUF FEB2h 59h Serial channel 0 receive buffer register (read only) - - XXh
S0RIC b FF6Eh B7h Serial channel 0 receive interrupt control register - - 00h
S0TBIC b F19Ch E CEh Serial channel 0 transmit buffer interrupt control reg. - - 00h
S0TBUF FEB0h 58h Serial channel 0 transmit buffer register (write only) 0000h
S0TIC b FF6Ch B6h Serial channel 0 transmit interrupt control register - - 00h
SP FE12h 09h CPU system stack pointer register FC00h
SSCBR F0B4h E 5Ah SSC Baud rate register 0000h
SSCCON b FFB2h D9h SSC control register 0000h
SSCEIC b FF76h BBh SSC error interrupt control register - - 00h
SSCRB F0B2h E 59h SSC receive buffer (read only) XXXXh
SSCRIC b FF74h BAh SSC receive interrupt control register - - 00h
SSCTB F0B0h E 58h SSC transmit buffer (write only) 0000h
SSCTIC b FF72h B9h SSC transmit interrupt control register - - 00h
STKOV FE14h 0Ah CPU stack overflow pointer register FA00h
STKUN FE16h 0Bh CPU stack underflow pointer register FC00h
SYSCON b FF12h 89h CPU system configuration register 0xx0h 1)
T0 FE50h 28h CAPCOM timer 0 register 0000h
T01CON b FF50h A8h CAPCOM timer 0 and timer 1 control register 0000h
T0IC b FF9Ch CEh CAPCOM timer 0 interrupt control register - - 00h
T0REL FE54h 2Ah CAPCOM timer 0 reload register 0000h

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Register set ST10F272

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

T1 FE52h 29h CAPCOM timer 1 register 0000h

T1IC b FF9Eh CFh CAPCOM timer 1 interrupt control register - - 00h
T1REL FE56h 2Bh CAPCOM timer 1 reload register 0000h
T2 FE40h 20h GPT1 timer 2 register 0000h
T2CON b FF40h A0h GPT1 timer 2 control register 0000h
T2IC b FF60h B0h GPT1 timer 2 interrupt control register - - 00h
T3 FE42h 21h GPT1 timer 3 register 0000h
T3CON b FF42h A1h GPT1 timer 3 control register 0000h
T3IC b FF62h B1h GPT1 timer 3 interrupt control register - - 00h
T4 FE44h 22h GPT1 timer 4 register 0000h
T4CON b FF44h A2h GPT1 timer 4 control register 0000h
T4IC b FF64h B2h GPT1 timer 4 interrupt control register - - 00h
T5 FE46h 23h GPT2 timer 5 register 0000h
T5CON b FF46h A3h GPT2 timer 5 control register 0000h
T5IC b FF66h B3h GPT2 timer 5 interrupt control register - - 00h
T6 FE48h 24h GPT2 timer 6 register 0000h
T6CON b FF48h A4h GPT2 timer 6 control register 0000h
T6IC b FF68h B4h GPT2 timer 6 interrupt control register - - 00h
T7 F050h E 28h CAPCOM timer 7 register 0000h
T78CON b FF20h 90h CAPCOM timer 7 and 8 control register 0000h
T7IC b F17Ah E BDh CAPCOM timer 7 interrupt control register - - 00h
T7REL F054h E 2Ah CAPCOM timer 7 reload register 0000h
T8 F052h E 29h CAPCOM timer 8 register 0000h
T8IC b F17Ch E BEh CAPCOM timer 8 interrupt control register - - 00h
T8REL F056h E 2Bh CAPCOM timer 8 reload register 0000h
TFR b FFACh D6h Trap Flag register 0000h
WDT FEAEh 57h Watchdog timer register (read only) 0000h
WDTCON b FFAEh D7h Watchdog timer control register 00xxh 2)
XADRS3 F01Ch E 0Eh XPER address select register 3 800Bh
XP0IC b F186h E C3h See Section 9.1 - - 00h 3)
XP1IC b F18Eh E C7h See Section 9.1 - - 00h 3)
XP2IC b F196h E CBh See Section 9.1 - - 00h 3)
XP3IC b F19Eh E CFh See Section 9.1 - - 00h 3)

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ST10F272 Register set

Table 52. List of special function registers (continued)

Physical 8-bit Reset
Name Description
address address value

XPERCON b F024h E 12h XPER configuration register - - 05h

ZEROS b FF1Ch 8Eh Constant value 0’s register (read only) 0000h

Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0
x000 0000b.
2. Reset Value depends on different triggered reset event.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus
peripherals. Some software controlled interrupt requests may be generated by setting the
XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes.

23.2 X-registers
The following table lists all X-Bus registers which are implemented in the ST10F272 ordered
by their name. The FLASH control registers are listed in a separate section, in spite of they
also are physically mapped on X-Bus memory space.
Note: The X-Registers are not bit-addressable.

Table 53. List of XBus registers

Physical Reset
Name Description
address value

CAN1BRPER EF0Ch CAN1: BRP extension register 0000h

CAN1BTR EF06h CAN1: Bit timing register 2301h
CAN1CR EF00h CAN1: CAN control register 0001h
CAN1EC EF04h CAN1: error counter 0000h
CAN1IF1A1 EF18h CAN1: IF1 arbitration 1 0000h
CAN1IF1A2 EF1Ah CAN1: IF1 arbitration 2 0000h
CAN1IF1CM EF12h CAN1: IF1 command mask 0000h
CAN1IF1CR EF10h CAN1: IF1 command request 0001h
CAN1IF1DA1 EF1Eh CAN1: IF1 data A 1 0000h
CAN1IF1DA2 EF20h CAN1: IF1 data A 2 0000h
CAN1IF1DB1 EF22h CAN1: IF1 data B 1 0000h
CAN1IF1DB2 EF24h CAN1: IF1 data B 2 0000h
CAN1IF1M1 EF14h CAN1: IF1 mask 1 FFFFh
CAN1IF1M2 EF16h CAN1: IF1 mask 2 FFFFh
CAN1IF1MC EF1Ch CAN1: IF1 message control 0000h
CAN1IF2A1 EF48h CAN1: IF2 arbitration 1 0000h
CAN1IF2A2 EF4Ah CAN1: IF2 arbitration 2 0000h
CAN1IF2CM EF42h CAN1: IF2 command mask 0000h

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Register set ST10F272

Table 53. List of XBus registers (continued)

Physical Reset
Name Description
address value

CAN1IF2CR EF40h CAN1: IF2 command request 0001h

CAN1IF2DA1 EF4Eh CAN1: IF2 data A 1 0000h
CAN1IF2DA2 EF50h CAN1: IF2 data A 2 0000h
CAN1IF2DB1 EF52h CAN1: IF2 data B 1 0000h
CAN1IF2DB2 EF54h CAN1: IF2 data B 2 0000h
CAN1IF2M1 EF44h CAN1: IF2 Mask 1 FFFFh
CAN1IF2M2 EF46h CAN1: IF2 mask 2 FFFFh
CAN1IF2MC EF4Ch CAN1: IF2 message control 0000h
CAN1IP1 EFA0h CAN1: interrupt pending 1 0000h
CAN1IP2 EFA2h CAN1: interrupt pending 2 0000h
CAN1IR EF08h CAN1: interrupt register 0000h
CAN1MV1 EFB0h CAN1: message valid 1 0000h
CAN1MV2 EFB2h CAN1: message valid 2 0000h
CAN1ND1 EF90h CAN1: new data 1 0000h
CAN1ND2 EF92h CAN1: new data 2 0000h
CAN1SR EF02h CAN1: status register 0000h
CAN1TR EF0Ah CAN1: test register 00x0h
CAN1TR1 EF80h CAN1: transmission request 1 0000h
CAN1TR2 EF82h CAN1: transmission request 2 0000h
CAN2BRPER EE0Ch CAN2: BRP extension register 0000h
CAN2BTR EE06h CAN2: bit timing register 2301h
CAN2CR EE00h CAN2: CAN control register 0001h
CAN2EC EE04h CAN2: error counter 0000h
CAN2IF1A1 EE18h CAN2: IF1 arbitration 1 0000h
CAN2IF1A2 EE1Ah CAN2: IF1 arbitration 2 0000h
CAN2IF1CM EE12h CAN2: IF1 command mask 0000h
CAN2IF1CR EE10h CAN2: IF1 command request 0001h
CAN2IF1DA1 EE1Eh CAN2: IF1 data A 1 0000h
CAN2IF1DA2 EE20h CAN2: IF1 data A 2 0000h
CAN2IF1DB1 EE22h CAN2: IF1 data B 1 0000h
CAN2IF1DB2 EE24h CAN2: IF1 data B 2 0000h
CAN2IF1M1 EE14h CAN2: IF1 mask 1 FFFFh
CAN2IF1M2 EE16h CAN2: IF1 mask 2 FFFFh
CAN2IF1MC EE1Ch CAN2: IF1 message control 0000h

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Table 53. List of XBus registers (continued)

Physical Reset
Name Description
address value

CAN2IF2A1 EE48h CAN2: IF2 arbitration 1 0000h

CAN2IF2A2 EE4Ah CAN2: IF2 arbitration 2 0000h
CAN2IF2CM EE42h CAN2: IF2 command mask 0000h
CAN2IF2CR EE40h CAN2: IF2 command request 0001h
CAN2IF2DA1 EE4Eh CAN2: IF2 data A 1 0000h
CAN2IF2DA2 EE50h CAN2: IF2 data A 2 0000h
CAN2IF2DB1 EE52h CAN2: IF2 data B 1 0000h
CAN2IF2DB2 EE54h CAN2: IF2 data B 2 0000h
CAN2IF2M1 EE44h CAN2: IF2 mask 1 FFFFh
CAN2IF2M2 EE46h CAN2: IF2 mask 2 FFFFh
CAN2IF2MC EE4Ch CAN2: IF2 message control 0000h
CAN2IP1 EEA0h CAN2: interrupt pending 1 0000h
CAN2IP2 EEA2h CAN2: interrupt pending 2 0000h
CAN2IR EE08h CAN2: interrupt register 0000h
CAN2MV1 EEB0h CAN2: message valid 1 0000h
CAN2MV2 EEB2h CAN2: message valid 2 0000h
CAN2ND1 EE90h CAN2: new data 1 0000h
CAN2ND2 EE92h CAN2: new data 2 0000h
CAN2SR EE02h CAN2: status register 0000h
CAN2TR EE0Ah CAN2: test register 00x0h
CAN2TR1 EE80h CAN2: transmission request 1 0000h
CAN2TR2 EE82h CAN2: Transmission request 2 0000h
I2CCCR1 EA06h I2C clock control register 1 0000h
I2CCCR2 EA0Eh I2C clock control register 2 0000h
I2CCR EA00h I2C control register 0000h
I2CDR EA0Ch I2C data register 0000h
I2COAR1 EA08h I2C own address register 1 0000h
I2COAR2 EA0Ah I2C own address register 2 0000h
I2CSR1 EA02h I2C status register 1 0000h
I2CSR2 EA04h I2C status register 2 0000h
RTCAH ED14h RTC alarm register high byte XXXXh
RTCAL ED12h RTC alarm register low byte XXXXh
RTCCON ED00H RTC control register 000Xh
RTCDH ED0Ch RTC divider counter high byte XXXXh

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Table 53. List of XBus registers (continued)

Physical Reset
Name Description
address value

RTCDL ED0Ah RTC divider counter low byte XXXXh

RTCH ED10h RTC programmable counter high byte XXXXh
RTCL ED0Eh RTC programmable counter low byte XXXXh
RTCPH ED08h RTC prescaler register high byte XXXXh
RTCPL ED06h RTC prescaler register low byte XXXXh
XCLKOUTDIV EB02h CLKOUT divider control register - - 00h
XEMU0 EB76h XBUS emulation register 0 (write only) XXXXh
XEMU1 EB78h XBUS emulation register 1 (write only) XXXXh
XEMU2 EB7Ah XBUS emulation register 2 (write only) XXXXh
XEMU3 EB7Ch XBUS emulation register 3 (write only) XXXXh
XIR0CLR EB14h X-Interrupt 0 clear register (write only) 0000h
XIR0SEL EB10h X-Interrupt 0 selection register 0000h
XIR0SET EB12h X-Interrupt 0 set register (write only) 0000h
XIR1CLR EB24h X-Interrupt 1 clear register (write only) 0000h
XIR1SEL EB20h X-Interrupt 1 selection register 0000h
XIR1SET EB22h X-Interrupt 1 set register (write only) 0000h
XIR2CLR EB34h X-Interrupt 2 clear register (write only) 0000h
XIR2SEL EB30h X-Interrupt 2 selection register 0000h
XIR2SET EB32h X-Interrupt 2 set register (write only) 0000h
XIR3CLR EB44h X-Interrupt 3 clear selection register (write only) 0000h
XIR3SEL EB40h X-Interrupt 3 selection register 0000h
XIR3SET EB42h X-Interrupt 3 set selection register (write only) 0000h
XMISC EB46h XBUS miscellaneous features register 0000h
XP1DIDIS EB36h Port 1 digital disable register 0000h
XPEREMU EB7Eh XPERCON copy for emulation (write only) XXXXh
XPICON EB26h Extended port input threshold control register - - 00h
XPOLAR EC04h XPWM module channel polarity register 0000h
XPP0 EC20h XPWM module period register 0 0000h
XPP1 EC22h XPWM module period register 1 0000h
XPP2 EC24h XPWM module period register 2 0000h
XPP3 EC26h XPWM module period register 3 0000h
XPT0 EC10h XPWM module up/down counter 0 0000h
XPT1 EC12h XPWM module up/down counter 1 0000h
XPT2 EC14h XPWM module up/down counter 2 0000h

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ST10F272 Register set

Table 53. List of XBus registers (continued)

Physical Reset
Name Description
address value

XPT3 EC16h XPWM module up/down counter 3 0000h

XPW0 EC30h XPWM module pulse width register 0 0000h
XPW1 EC32h XPWM module pulse width register 1 0000h
XPW2 EC34h XPWM module pulse width register 2 0000h
XPW3 EC36h XPWM module pulse width register 3 0000h
XPWMCON0 EC00h XPWM module control register 0 0000h
XPWMCON0CLR EC08h XPWM module clear control reg. 0 (write only) 0000h
XPWMCON0SET EC06h XPWM module set control register 0 (write only) 0000h
XPWMCON1 EC02h XPWM module control register 1 0000h
XPWMCON1CLR EC0Ch XPWM module clear control reg. 0 (write only) 0000h
XPWMCON1SET EC0Ah XPWM module set control register 0 (write only) 0000h
XPWMPORT EC80h XPWM module port control register 0000h
XS1BG E906h XASC Baud rate generator reload register 0000h
XS1CON E900h XASC control register 0000h
XS1CONCLR E904h XASC clear control register (write only) 0000h
XS1CONSET E902h XASC set control register (write only) 0000h
XS1PORT E980h XASC port control register 0000h
XS1RBUF E90Ah XASC receive buffer register 0000h
XS1TBUF E908h XASC transmit buffer register 0000h
XSSCBR E80Ah XSSC Baud rate register 0000h
XSSCCON E800h XSSC control register 0000h
XSSCCONCLR E804h XSSC clear control register (write only) 0000h
XSSCCONSET E802h XSSC set control register (write only) 0000h
XSSCPORT E880h XSSC port control register 0000h
XSSCRB E808h XSSC receive buffer XXXXh
XSSCTB E806h XSSC transmit buffer 0000h

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Register set ST10F272

23.3 Flash registers ordered by name

The following table lists all Flash Control Registers which are implemented in the ST10F272
ordered by their name. These registers are physically mapped on the IBus, except for
XFVTAUR0, which is mapped on XBus. Note that these registers are not bit-addressable.

Table 54. List of flash registers

Physical
Name Description Reset value
address

FARH 0x0008 0012 Flash address register - high 0000h

FARL 0x0008 0010 Flash address register - low 0000h
FCR0H 0x0008 0002 Flash control register 0 - high 0000h
FCR0L 0x0008 0000 Flash control register 0 - low 0000h
FCR1H 0x0008 0006 Flash control register 1 - high 0000h
FCR1L 0x0008 0004 Flash control register 1 - low 0000h
FDR0H 0x0008 000A Flash data register 0 - high FFFFh
FDR0L 0x0008 0008 Flash data register 0 - low FFFFh
FDR1H 0x0008 000E Flash data register 1 - high FFFFh
FDR1L 0x0008 000C Flash data register 1 - low FFFFh
FER 0x0008 0014 Flash error register 0000h
FNVAPR0 0x0008 DFB8 Flash non volatile access protection reg.0 ACFFh
FNVAPR1H 0x0008 DFBE Flash non volatile access protection reg.1 - high FFFFh
FNVAPR1L 0x0008 DFBC Flash non volatile access protection reg.1 - low FFFFh
FNVWPIR 0x0008 DFB0 Flash non volatile protection I register FFFFh
XBus Flash volatile temporary access
XFVTAUR0 0x0000 EB50 0000h
unprotection register 0

23.4 Identification registers

The ST10F272 have four Identification registers, mapped in ESFR space. These registers
contain:
● A manufacturer identifier
● A chip identifier with its revision
● A internal Flash and size identifier
● Programming voltage description

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ST10F272 Register set

IDMANUF (F07Eh / 3Fh) ESFR Reset Value: 0403h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MANUF 0 0 0 1 1
R R

Table 55. IDMANUF

Bit Function

Manufacturer identifier
MANUF
020h: STMicroelectronics manufacturer (JTAG worldwide normalization).

IDCHIP (F07Ch / 3Eh) ESFR Reset Value: 110Xh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDCHIP REVID
R R

Table 56. IDCHIP

Bit Function

Device identifier
IDCHIP
110h: ST10F272 identifier (272).
Device revision identifier
REVID
Xh: According to revision number.

IDMEM (F07Ah / 3Dh) ESFR Reset Value: 3040h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMTYP MEMSIZE
R R

Table 57. IDMEM

Bit Function

Internal memory size

MEMSIZE Internal memory size is 4 x (MEMSIZE) (in Kbyte)
040h for 256 Kbytes (ST10F272)

Internal memory type

‘0h’: ROM-Less
‘1h’: (M) ROM memory
MEMTYP
‘2h’: (S) Standard Flash memory
‘3h’: (H) High performance Flash memory (ST10F272)
‘4h...Fh’: Reserved

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IDPROG (F078h / 3Ch) ESFR Reset Value: 0040h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROGVPP PROGVDD
R R

Table 58. IDPROG

Bit Function

Programming VDD voltage

PROGVDD VDD voltage when programming EPROM or FLASH devices is calculated using the
following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F272 (5V).
PROGVPP Programming VPP voltage (no need of external VPP) - 00h

Note: All identification words are read only registers.

The values written inside different Identification Register bits are valid only after the Flash
initialization phase is completed. When code execution is started from internal memory (pin
EA held high during reset), the Flash has certainly completed its initialization, so the bits of
Identification Registers are immediately ready to be read out. On the contrary, when code
execution is started from external memory (pin EA held low during reset), the Flash
initialization is not yet completed, so the bits of Identification Registers are not ready. The
user can poll bits 15 and 14 of IDMEM register: when both bits are read low, the Flash
initialization is complete, so all Identification Register bits are correct.
Before Flash initialization completion, the default setting of the different Identification
Registers are the following:
● IDMANUF 0403h
● IDCHIP 110xh (x = silicon revision)
● IDMEM F040h
● IDPROG 0040h

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ST10F272 Electrical characteristics

24 Electrical characteristics

24.1 Absolute maximum ratings

Table 59. Absolute maximum ratings
Symbol Parameter Values Unit

VDD Voltage on VDD pins with respect to ground (VSS) -0.5 to +6.5 V
VSTBY Voltage on VSTBY pin with respect to ground (VSS) -0.5 to +6.5 V
VAREF Voltage on VAREF pins with respect to ground (VSS) -0.3 to VDD V
VAGND Voltage on VAGND pins with respect to ground (VSS) VSS V
VIO Voltage on any pin with respect to ground (VSS) -0.5 to VDD + 0.5 V
IOV Input current on any pin during overload condition ± 10 mA
ITOV Absolute sum of all input currents during overload condition | 75 | mA
TST Storage temperature -65 to +150 °C
ESD ESD Susceptibility (Human Body Model) 2000 V

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.
During Power-on and Power-off transients (including Standby entering/exiting phases), the
relationships between voltages applied to the device and the main VDD shall be always
respected. In particular power-on and power-off of VAREF shall be coherent with VDD
transient, in order to avoid undesired current injection through the on-chip protection diodes.

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Electrical characteristics ST10F272

24.2 Recommended operating conditions

Table 60. Recommended operating conditions
Value
Symbol Parameter Unit
Min Max

VDD Operating supply voltage 4.5 5.5 V

(1)
VSTBY Operationg stand-by supply voltage 4.5 5.5 V
VAREF (2)
Operating analog reference voltage
TA Ambient temperature under bias -40 +125 °C
TJ Junction temperature under bias -40 +150 °C
1. The value of the VSTBY voltage is specified in the range 4.5 - 5.5 Volt. Nevertheless, it is acceptable to exceed the upper
limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device
(about 30 years). On the other hand, it is possible to exceed the lower limit (down to 4.0 Volt) whenever RTC and 32kHz
on-chip oscillator amplifier are turned off (only Stand-by RAM powered through VSTBY pin in Stand-by mode). When
VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on
VDD power supply (in the range of tenth of µA).
2. For details on operating conditions concerning the usage of A/D Converter refer to Section 24.7.

24.3 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA) (1)
Where:
TA is the Ambient Temperature in °C,
ΘJA is the Package Junction-to-Ambient Thermal Resistance, in °C/W,
PD is the sum of PINT and PI/O (PD = PINT + PI/O),
PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power,
PI/O represents the Power Dissipation on Input and Output Pins; User Determined.
Most of the time for the applications PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant if the device is configured to drive continuously external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273°C) (2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2 (3)
Where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
may be obtained by solving equations (1) and (2) iteratively for any value of TA.

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Table 61. Thermal characteristics

Symbol Description Value (typical) Unit

Thermal Resistance Junction-Ambient

PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch 30
ΘJA TQFP 144 - 20 x 20 mm / 0.5 mm pitch 40 °C/W
TQFP 144 - 20 x 20 mm / 0.5 mm pitch on four layer 35
FR4 board (2 layers signals / 2 layers power)

Based on thermal characteristics of the package and with reference to the power
consumption figures provided in next tables and diagrams, the following product
classification can be proposed. Anyhow, the exact power consumption of the device inside
the application must be computed according to different working conditions, thermal profiles,
real thermal resistance of the system (including printed circuit board or other substrata), I/O
activity, and so on.

Table 62. Package characteristics

Package Ambient temperature range CPU frequency range

PQFP 144 –40 / +125°C 1 – 64MHz

TQFP 144 –40 / +125°C 1 – 40MHz

24.4 Parameter interpretation

The parameters listed in the following tables represent the characteristics of the ST10F272
and its demands on the system.
Where the ST10F272 logic provides signals with their respective timing characteristics, the
symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where the
external system must provide signals with their respective timing characteristics to the
ST10F272, the symbol “SR” for System Requirement, is included in the “Symbol” column.

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24.5 DC characteristics
VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125°C

Table 63. DC characteristics

Limit values
Parameter Symbol Unit Test Condition
min. max.

Input low voltage (TTL mode)

(except RSTIN, EA, NMI, RPD, XTAL1, VIL SR – 0.3 0.8 V –
READY)
Input low voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1, VILS SR – 0.3 0.3 VDD V –
READY)
Input low voltage RSTIN, EA, NMI, RPD VIL1 SR – 0.3 0.3 VDD V –
Input low voltage XTAL1 (CMOS only) VIL2 SR – 0.3 0.3 VDD V Direct Drive mode
Input low voltage READY (TTL only) VIL3 SR – 0.3 0.8 V –
Input high voltage (TTL mode)
VIH SR 2.0 VDD + 0.3 V –
(except RSTIN, EA, NMI, RPD, XTAL1)
Input high voltage (CMOS mode)
VIHS SR 0.7 VDD VDD + 0.3 V –
(except RSTIN, EA, NMI, RPD, XTAL1)
Input high voltage RSTIN, EA, NMI, RPD VIH1 SR 0.7 VDD VDD + 0.3 V –
Input high voltage XTAL1 (CMOS only) VIH2 SR 0.7 VDD VDD + 0.3 V Direct Drive mode
Input high voltage READY (TTL only) VIH3 SR 2.0 VDD + 0.3 V –
Input Hysteresis (TTL mode) (1)
VHYS CC 400 700 mV
(except RSTIN, EA, NMI, XTAL1, RPD)
Input Hysteresis (CMOS mode) (1)
VHYSSCC 750 1400 mV
(except RSTIN, EA, NMI, XTAL1, RPD)
(1)
Input Hysteresis RSTIN, EA, NMI VHYS1CC 750 1400 mV
Input Hysteresis XTAL1 VHYS2CC 0 50 mV (1)

(1)
Input Hysteresis READY (TTL only) VHYS3CC 400 700 mV
(1)
Input Hysteresis RPD VHYS4CC 500 1500 mV
Output low voltage
(P6[7:0], ALE, RD, WR/WRL, 0.4 IOL = 8 mA
VOL CC – V
BHE/WRH, CLKOUT, RSTIN, 0.05 IOL = 1 mA
RSTOUT)
Output low voltage
(P0[15:0], P1[15:0], P2[15:0], 0.4 IOL1 = 4 mA
VOL1 CC – V
P3[15,13:0], P4[7:0], P7[7:0], 0.05 IOL1 = 0.5 mA
P8[7:0])
VDD IOL2 = 85 µA
Output low voltage RPD VOL2 CC – 0.5 VDD V IOL2 = 80 µA
0.3 VDD IOL2 = 60 µA

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Table 63. DC characteristics (continued)

Limit values
Parameter Symbol Unit Test Condition
min. max.

Output high voltage

VDD – 0.8 IOH = – 8 mA
(P6[7:0], ALE, RD, WR/WRL, VOH CC – V
VDD – 0.08 IOH = – 1 mA
BHE/WRH, CLKOUT, RSTOUT)
Output high voltage (2)
(P0[15:0], P1[15:0], P2[15:0], VDD – 0.8 IOH1 = – 4 mA
VOH1 CC – V
P3[15,13:0], P4[7:0], P7[7:0], VDD – 0.08 IOH1 = – 0.5 mA
P8[7:0])
0 IOH2 = – 2 mA
Output high voltage RPD VOH2 CC 0.3 VDD – V IOH2 = – 750 µA
0.5 VDD IOH2 = – 150 µA
Input leakage current (P5[15:0]) (3) |IOZ1 | CC – ±0.2 µA –
Input leakage current
(all except P5[15:0], P2[0], RPD, P3[12], |IOZ2 | CC – ±0.5 µA –
P3[15])
+1.0
Input leakage current (P2[0]) (4) |IOZ3 | CC – µA –
–0.5
Input leakage current (RPD) |IOZ4 | CC – ±3.0 µA –
Input leakage current ( P3[12], P3[15]) |IOZ5 | CC – ±1.0 µA –
(1) (5)
Overload current (all except P2[0]) |IOV1 | SR – ±5 mA
+5
Overload current (P2[0]) (4) |IOV2 | SR – mA (1) (5)
–1
RSTIN pull-up resistor RRST CC 50 250 kΩ 100 kΩ nominal
Read/Write inactive current (6) (7) IRWH – –40 µA VOUT = 2.4 V
Read/Write active current (6) (8)
IRWL –500 – µA VOUT = 0.4V
ALE inactive current (6) (7)
IALEL 20 – µA VOUT = 0.4V
ALE active current (6) (8)
IALEH – 300 µA VOUT = 2.4 V
Port 6 inactive current (P6[4:0]) (6) (7) IP6H – –40 µA VOUT = 2.4 V
Port 6 active current (P6[4:0]) (6) (8)
IP6L –500 – µA VOUT = 0.4V
IP0H 6)
– –10 µA VIN = 2.0V
PORT0 configuration current (6)
IP0L 7) –100 – µA VIN = 0.8V
Pin Capacitance (Digital inputs / outputs) CIO CC (1) (6)
– 10 pF
Run Mode Power supply current (9) 15 + 1.5
ICC1 – mA –
(Execution from Internal RAM) fCPU
Run Mode Power supply current (1) (10) 15 + 1.5
ICC2 – mA –
(Execution from Internal Flash) fCPU
15 + 0.6
Idle mode supply current (11) IID – mA –
fCPU

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Table 63. DC characteristics (continued)

Limit values
Parameter Symbol Unit Test Condition
min. max.

Power Down supply current (12)

(RTC off, Oscillators off, IPD1 – 400 µA TA = 25°C
Main Voltage Regulator off)

Power Down supply current (12) 400

(RTC on, Main Oscillator on, IPD2 – Typical µA TA = 25°C
Main Voltage Regulator off) Value
Power Down supply current (12)
(RTC on, 32kHz Oscillator on, IPD3 – 400 µA TA = 25°C
Main Voltage Regulator off)
VSTBY = 5.5 V
Stand-by supply current (12) – 120 µA
TA = TJ = 25°C
(RTC off, Oscillators off, VDD off, VSTBY ISB1
on) VSTBY = 5.5 V
– 500 µA
TA = TJ = 125°C
Stand-by supply current (12)
VSTBY = 5.5 V
(RTC on, 32kHz Oscillator on, ISB2 – 120 µA
TA = 25°C
main VDD off, VSTBY on)
Stand-by supply current (1) (12)
ISB3 – 2.5 mA –
(VDD transient condition)
1. Not 100% tested, guaranteed by design characterization.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 37 for a scheme of the input
circuitry.
5. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range (i.e. VOV > VDD + 0.3 V or VOV < –0.3 V). The absolute sum of input overload currents on all port pins may
not exceed 50mA. The supply voltage must remain within the specified limits.
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced

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10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at VIL or VIH, RSTIN pin at VIH1min.
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD
– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed.

Figure 37. Port2 test mode structure

P2.0
Output CC0IO
buffer
Clock

Alternate data input Input

latch

Fast external interrupt input

Test mode

Flash sense amplifier

and column decoder

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Figure 38. Supply current versus the operating frequency (RUN and IDLE modes)

150

ICC1 = ICC2
100
I [mA]

IID
50

0
0 10 20 30 40 50 60 70
fCPU [MHz]

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24.6 Flash characteristics

VDD = 5 V ± 10%, VSS = 0 V

Table 64. Flash characteristics

Typical Maximum

Parameter TA = 25°C TA = 125°C Unit Notes

0 cycles(1) 0 cycles(1) 100k cycles

Word Program (32-bit) (2) 35 80 290 µs –

Double Word Program (64-bit) (2))
60 150 570 µs –
Bank 0 Program (256K)
1.6 2.0 3.9 s –
(Double Word Program)
0.6 0.9 1.0 not preprogrammed
Sector Erase (8K) s
0.5 0.8 0.9 preprogrammed
1.1 2.0 2.7 not preprogrammed
Sector Erase (32K) s
0.8 1.8 2.5 preprogrammed
1.7 3.7 5.1 not preprogrammed
Sector Erase (64K) s
1.3 3.3 4.7 preprogrammed
5.6 13.6 19.2 not preprogrammed
Bank 0 Erase (256K) (3) s
4.0 11.9 17.5 preprogrammed
Recovery from Power-Down (tPD) – 40 40 µs (4)

Program Suspend Latency (4) – 10 10 µs

Erase Suspend Latency (4)
– 30 30 µs
Min delay between 2
Erase Suspend Request Rate (4) 20 20 20 ms
requests
Set Protection (4) 40 90 300 µs
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2. Word and Double Word Programming times are provided as average values derived from a full sector programming time:
absolute value of a Word or Double Word Programming time could be longer than the average value.
3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As
ST10F272 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations.
4. Not 100% tested, guaranteed by Design Characterization.

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Table 65. Flash data retention characteristics

Data retention time
Number of program / erase cycles (average ambient temperature 60°C)
(-40°C ≤ TA ≤ 125°C)
256Kbyte (code store) 64Kbyte (EEPROM emulation) (1)

0 - 100 > 20 years > 20 years

1,000 - > 20 years
10,000 - 10 years
100,000 - 1 year
1. Two 64Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16Kbyte of EEPROM. Therefore, in case of an
emulation of a 16Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM
Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document
(AN2061 - “EEPROM Emulation with ST10F2xx”). Contact your local field service, local sales person or STMicroelectronics
representative to get copy of such a guideline document.

24.7 A/D converter characteristics

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C, 4.5V ≤ VAREF ≤ VDD,
VSS ≤ VAGND ≤ VSS + 0.2V

Table 66. A/D converter characteristics

Limit Values
Parameter Symbol Unit Test Condition
min. max.

Analog Reference voltage 1) VAREF SR 4.5 VDD V

Analog Ground voltage VAGND SR VSS VSS + 0.2 V
Analog Input voltage 2) VAIN SR VAGND VAREF V
– 5 mA Running mode 3)
Reference supply current IAREF CC
– 1 µA Power Down mode

Sample time tS CC 1 – µs 4)

Conversion time tC CC 3 – µs 5)

Differential Non Linearity 6) DNL CC –1 +1 LSB No overload

6)
Integral Non Linearity INL CC –1.5 +1.5 LSB No overload
Offset Error 6) OFS CC –1.5 +1.5 LSB No overload
–2.0 +2.0 Port5
Total unadjusted error 6) TUE CC –5.0 +5.0 LSB Port1 - No overload 3)
–7.0 +7.0 Port1 - Overload 3)
Coupling Factor between inputs 3) 7) K CC – 10–6 – On both Port5 and Port1
CP1 CC – 3 pF
Input Pin Capacitance 3) 8) 4 Port5
CP2 CC – pF
6 Port1
Sampling Capacitance 3) 8) CS CC – 3.5 pF

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Table 66. A/D converter characteristics

Limit Values
Parameter Symbol Unit Test Condition
min. max.

– 600 Port5
RSW CC W
Analog Switch Resistance 3) 8) – 1600 Port1
RAD CC – 1300 W

1. VAREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200µA) on
main VDD is added due to internal analogue circuitry not completely turned off: so, it is suggested to
maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D Converter circuitry
setting bit ADOFF in ADCON register.
2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 0x000H or 0x3FFH, respectively.
3. Not 100% tested, guaranteed by design characterization.
4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample clock tS depends on programming and can be taken from Table 67: A/D converter
programming.
5. This parameter includes the sample time tS, the time for determining the digital result and the time to load
the result register with the conversion result. Values for the conversion clock tCC depend on programming
and can be taken from next Table 67.
6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design
characterization for all other voltages within the defined voltage range.
‘LSB’ has a value of VAREF/1024.
For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV
specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of
input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins:
when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input
positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static
injection), the specified TUE is degraded (± 7LSB). To get the same accuracy, the negative injection
current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection.
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
8. Refer to scheme reported in Figure 40.

24.7.1 Conversion timing control

When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
VAREF pin.
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the ST10F272 relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent
from the general speed of the controller. This allows adjusting the A/D converter of the
ST10F272 to the properties of the system:

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Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher
value, or the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. The
conversion rate in this case may be considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete
conversion time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.

Table 67. A/D converter programming

ADCTC ADSTC Sample Comparison Extra Total conversion

00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388

00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436
00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532
00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724
11 00 TCL * 240 TCL * 480 TCL * 52 TCL * 772
11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868
11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060
11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444
10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540
10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732
10 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116
10 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884

Note: The total conversion time is compatible with the formula valid for ST10F269, while the
meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum
conversion time is 388 TCL, which at 40MHz CPU frequency corresponds to 4.85µs (see
ST10F269).

24.7.2 A/D conversion accuracy

The A/D Converter compares the analog voltage sampled on the selected analog input
channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The
absolute accuracy of the A/D conversion is the deviation between the input analog value and
the output digital value. It includes the following errors:
● Offset error (OFS)
● Gain Error (GE)
● Quantization error
● Non-Linearity error (Differential and Integral)

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These four error quantities are explained below using Figure 39.

Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when
the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 39, see
OFS).

Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when
the digital output value changes from the 3FE to the maximum 3FF, once offset error is
subtracted. Gain error combined with offset error represents the so-called full-scale error
(Figure 39, OFS + GE).

Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.

Non-linearity error
Non-Linearity error is the deviation between actual and the best-fitting A/D conversion
characteristics (see Figure 39):
● Differential Non-Linearity error is the actual step dimension versus the ideal one (1
LSBIDEAL).
● Integral Non-Linearity error is the distance between the center of the actual step and
the center of the bisector line, in the actual characteristics. Note that for Integral Non-
Linearity error, the effect of offset, gain and quantization errors is not included.
Note: Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the
real characteristic, and 1/2 LSB after the last step again of the real characteristic.

24.7.3 Total unadjusted error

The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic:
the number provided in the Data Sheet represents the maximum error with respect to the
entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The
different errors may compensate each other depending on the relative sign of the Offset and
Gain errors. Refer to Figure 39, see TUE.

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Figure 39. A/D conversion characteristic

Offset Error OFS Gain Error GE

3FF

3FE
(6)
3FD
Ideal Characteristic
3FC

3FB

3FA
(2) Bisector Characteristic

Digital
Out 007
(HEX) (7)
(1)
006

005
(5) (1) Example of an actual transfer curve
004 (2) The ideal transfer curve
(4) (3) Differential Non-Linearity Error (DNL)
003 (4) Integral Non-Linearity Error (INL)
(5) Center of a step of the actual transfer curve
002 (3) (6) Quantization Error (1/2 LSB)
(7) Total Unadjusted Error (TUE)
001
1 LSB (ideal)
000
1 2 3 4 5 6 7 1018 1020 1022 1024
VAIN (LSBIDEAL)
[LSBIDEAL = VAREF / 1024]
Offset Error OFS

24.7.4 Analog reference pins

The accuracy of the A/D converter depends on how accurate is its analog reference: a noise
in the reference results in at least that much error in a conversion. A low pass filter on the
A/D converter reference source (supplied through pins VAREF and VAGND), is recommended
in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be
sufficient in most of the cases; in presence of high RF noise energy, inductors or ferrite
beads may be necessary.
In this architecture, VAREF and VAGND pins represents also the power supply of the analog
circuitry of the A/D converter: there is an effective DC current requirement from the
reference voltage by the internal resistor string in the R-C DAC array and by the rest of the
analog circuitry.
An external resistance on VAREF could introduce error under certain conditions: for this
reasons, series resistance are not advisable, and more in general any series devices in the
filter network should be designed to minimize the DC resistance.

Analog Input pins

To improve the accuracy of the A/D converter, it is definitively necessary that analog input
pins have low AC impedance. Placing a capacitor with good high frequency characteristics
at the input pin of the device, can be effective: the capacitor should be as large as possible,
ideally infinite. This capacitor contributes to attenuating the noise present on the input pin;

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besides, it sources charge during the sampling phase, when the analog signal source is a
high-impedance source.
A real filter, can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC Filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth).

Figure 40. A/D converter input pins scheme

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel
Selection Sampling
Source Filter Current Limiter

RS RF RL RSW RAD

VA CF CP1 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance

Input Leakage and external circuit

The series resistor utilized to limit the current to a pin (see RL in Figure 40), in combination
with a large source impedance can lead to a degradation of A/D converter accuracy when
input leakage is present.
Data about maximum input leakage current at each pin are provided in the Data Sheet
(Electrical Characteristics section). Input leakage is greatest at high operating temperatures,
and in general it decreases by one half for each 10° C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF = 5V),
an input leakage of 100nA acting though an RL = 50kΩ of external resistance leads to an
error of exactly one count (5mV); if the resistance were 100kΩ the error would become two
counts.
Eventual additional leakage due to external clamping diodes must also be taken into
account in computing the total leakage affecting the A/D converter measurements. Another
contribution to the total leakage is represented by the charge sharing effects with the
sampling capacitance: being CS substantially a switched capacitance, with a frequency
equal to the conversion rate of a single channel (maximum when fixed channel continuous
conversion mode is selected), it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 250kHz, with CS equal to 4pF, a resistance of 1MΩ is
obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered
channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the following relation:
R S + R F + R L + R SW + R AD
1
V A ⋅ ------------------------------------------------------------------------------ < --- LSB
R EQ 2

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The formula above provides a constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.

Figure 41. Charge sharing timing diagram during sampling phase

VCS Voltage Transient on CS

VA
VA2 ∆V < 0.5 LSB

1 2
τ1 < (RSW + RAD) CS << TS

VA1 τ2 = RL (CS + CP1 + CP2)

TS t

In particular two different transient periods can be distinguished (see Figure 41):
● A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS
are in series, and the time constant is:
CP ⋅ CS
τ 1 = ( R SW + R AD ) ⋅ -----------------------
CP + CS

This relation can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
τ 1 < ( R SW + R AD ) ⋅ C S < < T S

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to the following equation:
V A1 ⋅ ( C S + C P1 + C P2 ) = V A ⋅ ( C P1 + C P2 )

● A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
τ 2 < R L ⋅ ( C S + C P1 + C P2 )

In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraints on

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RL sizing is obtained:

10 ⋅ τ 2 = 10 ⋅ R L ⋅ ( C S + C P1 + C P2 ) ≤ TS

Of course, RL shall be sized also according to the current limitation constraints, in

combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. The following equation must be
respected (charge balance assuming now CS already charged at VA1):

VA2 ⋅( C S + C P1 + C P2 + C F ) = V A ⋅C F + V A1 ⋅( C P1 + C P2 + C S )

The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing (see
Figure 42).
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period TC is longer than the sampling time
TS, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time TS, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.

Figure 42. Anti-aliasing filter and conversion rate

Analog Source Bandwidth (VA)

TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
Noise fF = f0 (Anti-aliasing Filtering Condition)
2 f0 ≤ fC (Nyquist)

f0 f
Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate)

fF f f0 fC f

The considerations above lead to impose new constraints to the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive the following relation between the ideal and real sampled
voltage on CS:
VA C P1 + C P2 + C F
----------- = ------------------------------------------------------------
V A2 C P1 + C P2 + C F + C S

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From this formula, in the worst case (when VA is maximum, that is for instance 5V),
assuming to accept a maximum error of half a count (~2.44mV), it is immediately evident a
constraints on CF value:
C F > 2048 ⋅C S

In the next section an example of how to design the external network is provided, assuming
some reasonable values for the internal parameters and making hypothesis on the
characteristics of the analog signal to be sampled.

Example of external network sizing

The following hypothesis are formulated in order to proceed in designing the external
network on A/D Converter input pins:
● Analog Signal Source Bandwidth (f0):10kHz
● conversion Rate (fC):25kHz
● Sampling Time (TS):1µs
● Pin Input Capacitance (CP1):5pF
● Pin Input Routing Capacitance (CP2):1pF
● Sampling Capacitance (CS):4pF
● Maximum Input Current Injection (IINJ):3mA
● Maximum Analog Source Voltage (VAM):12V
● Analog Source Impedance (RS):100Ω
● Channel Switch Resistance (RSW):500Ω
● Sampling Switch Resistance (RAD):200Ω

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1. Supposing to design the filter with the pole exactly at the maximum frequency of the
signal, the time constant of the filter is:
1
R C C F = ------------ = 15.9µs
2πf 0

2. Using the relation between CF and CS and taking some margin (4000 instead of 2048),
it is possible to define CF:

⋅ S = 16nF
C F = 4000 C

3. As a consequence of step 1 and 2, RC can be chosen:

1
R F = --------------------- = 995Ω ≅ 1kΩ
2πf 0 C F

4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
V AM
R S + R F + R L = ------------- = 4kΩ
I INJ

from which is now simple to define the value of RL:

V AM
R L = ------------- – R F – R S = 2.9kΩ
I INJ

5. Now the three element of the external circuit RF, CF and RL are defined. Some
conditions discussed in the previous paragraphs have been used to size the
component, the other must now be verified. The relation which allow to minimize the
accuracy error introduced by the switched capacitance equivalent resistance is in this
case:
1
R EQ = --------------- = 10MΩ
fC CS

So the error due to the voltage partitioning between the real resistive path and CS is
less then half a count (considering the worst case when VA = 5V):
R S + R F + R L + R SW + R AD 1
V A ⋅ --------------------------------------------------------------------------- = 2.35mV < --- LSB
R EQ 2

The other conditions to be verified is the time constants of the transients are really and
significantly shorter than the sampling period duration TS:
τ 1 = ( R SW + R AD ) ⋅ C S = 2.8ns << TS = 1µs

10 ⋅τ 2 = 10 ⋅R L⋅( C S + C P1 + C P2 ) = 290ns < TS = 1µs

For complete set of parameters characterizing the ST10F272 A/D Converter equivalent
circuit, refer to Section 24.7: A/D converter characteristics on page 136.

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24.8 AC characteristics

24.8.1 Test waveforms

Figure 43. Input / output waveforms

2.4V
2.0V 2.0V

Test Points

0.4V 0.8V 0.8V

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at VIH min. for a logic ‘1’ and VIL max for a logic ‘0’.

Figure 44. Float waveforms

VOH

VOH - 0.1V
VLOAD + 0.1V
Timing
VLOAD
Reference
VLOAD - 0.1V Points
VOL + 0.1V
VOL

For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.
It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20m

24.8.2 Definition of internal timing

The internal operation of the ST10F272 is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU.
This influence must be regarded when calculating the timings for the ST10F272.
The example for PLL operation shown in Figure 45 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).

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Figure 45. Generation mechanisms for the CPU clock

Phase locked loop operation

fXTAL

fCPU
TCLTCL
Direct Clock Drive
fXTAL

fCPU
TCLTCL
Prescaler Operation
fXTAL

fCPU
TCL TCL

24.8.3 Clock generation modes

Next Table 68 associates the combinations of these three bits with the respective clock
generation mode.

Table 68. On-chip clock generator selections

P0.15-13 CPU Frequency External Clock
Notes
(P0H.7-5) fCPU = fXTAL x F Input Range 1) 3)

1 1 1 FXTAL x 4 4 to 8MHz Default configuration

1 1 0 FXTAL x 3 5.3 to 8MHz
1 0 1 FXTAL x 8 4 to 8MHz
1 0 0 FXTAL x 5 6.4 to 8MHz
Direct Drive (oscillator bypassed)
0 1 1 FXTAL x 1 1 to 64MHz 2)

0 1 0 FXTAL x 10 4 to 6.4MHz
0 0 1 FXTAL / 2 4 to 8MHz CPU clock via prescaler 3)
0 0 0 FXTAL x 16 4MHz

1. The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited
to 4-8MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the
internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external
clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can
be used).
2. The maximum depends on the duty cycle of the external clock signal: when 64MHz is used, 50% duty cycle
shall be granted (low phase = high phase = 7.8ns); when 32MHz is selected a 25% duty cycle can be
accepted (minimum phase, high or low, again equal to 7.8ns).
3. The limits on input frequency are 4-8MHz since the usage of the internal oscillator amplifier is required.
Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator
shall be used: it is not possible to force any clock though an external clock source.

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24.8.4 Prescaler operation

When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fXTAL.
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.

24.8.5 Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of CPU clock (fCPU) directly follows the frequency of fXTAL so the high and
low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the
input clock fXTAL.
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
TCL min = 1 ⁄ f XTALl xlDC min
DC = duty cycle

For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,
so the duration of 2TCL is always 1/fXTAL.
The minimum value TCLmin has to be used only once for timings that require an odd number
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TCL = 1 ⁄ f XTAL

The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of
TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin.
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.

24.8.6 Oscillator watchdog (OWD)

An on-chip watchdog oscillator is implemented in the ST10F272. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If

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an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.

24.8.7 Phase Locked Loop (PLL)

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Table 68). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU =
fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to
keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is
negligible. Refer to next Section 24.8.9: PLL Jitter for more details.

24.8.8 Voltage Controlled Oscillator

The ST10F272 implements a PLL which combines different levels of frequency dividers with
a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table,
a detailed summary of the internal settings and VCO frequency is reported.

Table 69. Internal PLL divider mechanism

PLL
P0.15-13 XTAL Input Output CPU Frequency
(P0H.7-5) Frequency Prescaler Prescaler fCPU = fXTAL x F
Multiply by Divide by

1 1 1 4 to 8MHz FXTAL / 4 64 4 – FXTAL x 4

1 1 0 5.3 to 10.6MHz 1)
FXTAL / 4 48 4 – FXTAL x 3
1 0 1 4 to 8MHz FXTAL / 4 64 2 – FXTAL x 8
1)
1 0 0 6.4 to 12MHz FXTAL / 4 40 2 – FXTAL x 5
0 1 1 1 to 64MHz – PLL bypassed – FXTAL x 1

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Table 69. Internal PLL divider mechanism (continued)

PLL
P0.15-13 XTAL Input Output CPU Frequency
(P0H.7-5) Frequency Prescaler Prescaler fCPU = fXTAL x F
Multiply by Divide by

0 1 0 4 to 6.4MHz FXTAL / 2 40 2 – FXTAL x 10

0 0 1 4 to 12MHz 1)
– PLL bypassed FPLL / 2 FXTAL / 2
0 0 0 4MHz FXTAL / 2 64 2 – FXTAL x 16

The PLL input frequency range is limited to 1 to 3.5MHz, while the VCO oscillation range is
64 to 128MHz. The CPU clock frequency range when PLL is used is 16 to 64MHz.

Example 1
● FXTAL = 4MHz
● P0(15:13) = ‘110’ (Multiplication by 3)
● PLL Input Frequency = 1MHz
● VCO frequency = 48MHz
● PLL Output Frequency = 12MHz
(VCO frequency divided by 4)
● FCPU = 12MHz (no effect of Output Prescaler)

Example 2
● FXTAL = 8MHz
● P0(15:13) = ‘100’ (Multiplication by 5)
● PLL Input Frequency = 2MHz
● VCO frequency = 80MHz
● PLL Output Frequency = 40MHz (VCO frequency divided by 2)
● FCPU = 40MHz (no effect of Output Prescaler)

24.8.9 PLL Jitter

The following terminology is hereafter defined:
● Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the Tmax and Tmin,
where Tmax is maximum time period of the PLL output clock and Tmin is the minimum
time period of the PLL output clock.
● Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where
Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter at the PLL output can be due to the following reasons:
● Jitter in the input clock
● Noise in the PLL loop.

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Jitter in the input clock

PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.

Noise in the PLL loop

This contribution again can be caused by the following sources:
● Device noise of the circuit in the PLL
● Noise in supply and substrate.

Device noise of the circuit in the PLL

The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the
loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is
practically independent on the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random noise, frequency
independent so practically white noise) and flicker (low frequency noise, 1/f). For the
frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f2
region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a noiseless
PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S. value of the
accumulated jitter is proportional to the square root of N, where N is the number of clock
periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is
dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N,
where N is the number of clock periods within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 46 the maximum jitter trend versus the number of clock periods N (for some typical
CPU frequencies) is reported: the curves represent the very worst case, computed taking
into account all corners of temperature, power supply and process variations: the real jitter
is always measured well below the given worst case values.

Noise in supply and substrate

Digital supply noise adds deterministic components to the PLL output jitter, independent on
multiplication factor. Its effects is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. Anyhow, the
contribution of the digital noise to the global jitter is widely taken into account in the curves
provided in Figure 46.

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Figure 46. ST10F272 PLL jitter

±5
16MHz 24MHz 32MHz 40MHz 64MHz

±4

±3
Jitter [ns]

±2

±1

TJIT

0
0 200 400 600 800 1000 1200 1400
N (CPU clock periods)

24.8.10 PLL lock / unlock

During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency Ffree). This feature allows to recover from a
crystal failure occurrence without risking to go in an undefined configuration: the system is
provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
Note: The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration
of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized
high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not
sufficient to get the PLL locked starting from free-running mode).

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Table 70. PLL characteristics (VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C)
Value
Symbol Parameter Conditions Unit
min. max.

TPSUP PLL Start-up time 1) Stable VDD and reference clock – 300 µs
Stable VDD and reference clock,
TLOCK PLL Lock-in time – 250 µs
starting from free-running mode
Single Period Jitter 1) 6 sigma time period variation
TJIT –500 +500 ps
(cycle to cycle = 2 TCL) (peak to peak)
Multiplication Factors: 3, 4 250 2000
Ffree PLL free running frequency kHz
Multiplication Factors: 5, 8, 10, 16 500 4000

1. Not 100% tested, guaranteed by design characterization.

24.8.11 Main oscillator specifications

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C

Table 71. Main oscillator characteristics

Value
Symbol Parameter Conditions Unit
min. typ. max.

Oscillator
gm 1.4 2.6 4.2 mA/V
Transconductance
VOSC Oscillation Amplitude 1) Peak to Peak – 1.5 – V
1)
VAV Oscillation Voltage level Sine wave middle – 0.8 – V
Stable VDD - Crystal – 6 10 ms
tSTUP Oscillator Start-up Time 1)
Stable VDD - Resonator – 1 2 ms

1. Not 100% tested, guaranteed by design characterization.

Figure 47. Crystal oscillator and resonator connection diagram

ST10F272 ST10F272
XTAL1

XTAL2

XTAL1

XTAL2

crystal Resonator

CA CA

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Table 72. Main oscillator negative resistance (module)

CA = 15pF CA = 25pF CA = 35pF

min. typ. max. min. typ. max. min. typ. max.

4 MHz 545 Ω 1035 Ω – 550 Ω 1050 Ω – 430 Ω 850 Ω –

8 MHz 240 Ω 450 Ω – 170 Ω 350 Ω – 120 Ω 250 Ω –

The given values of CA do not include the stray capacitance of the package and of the
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C0) and the package capacitance
between XTAL1 and XTAL2 pins is globally assumed equal to 10pF.
The external resistance between XTAL1 and XTAL2 is not necessary, since already present
on the silicon.

24.8.12 32 kHz oscillator specifications

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C

Table 73. 32kHz oscillator characteristics

Value
Symbol Parameter Conditions Unit
min. typ. max.

Start-up 20 31 50 µA/V
gm32 Oscillator Transconductance 1)
Normal run 8 17 30 µA/V

VOSC32 Oscillation Amplitude 2) Peak to Peak 0.5 1.0 2.4 V

VAV32 Oscillation Voltage level 2) Sine wave middle 0.7 0.9 1.2 V

tSTUP32 Oscillator Start-up Time 2) Stable VDD – 1 5 s

1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started,
the current biasing is reduced to lower the power consumption of the system.
2. Not 100% tested, guaranteed by design characterization.

Figure 48. 32kHz crystal oscillator connection diagram

ST10F272
XTAL3

XTAL4

crystal

CA CA

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Table 74. Minimum values of negative resistance (module) for 32kHz oscillator
CA = 6pF CA = 12pF CA = 15pF CA = 18pF CA = 22pF CA = 27pF CA = 33pF

32kHz - - - - 150 kΩ 120 kΩ 90 kW

The given values of CA do not include the stray capacitance of the package and of the
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C0) and the package capacitance
between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance
between XTAL3 and XTAL4 is not necessary, since already present on the silicon.

Warning: Direct driving on XTAL3 pin is not supported. Always use a

32kHz crystal oscillator.

24.8.13 External clock drive XTAL1

When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock
directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since
the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that
targets a maximum CPU frequency of 64MHz.
In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip
oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when
the on-chip oscillator is enabled it is forbidden to use any external clock source different
from crystal or ceramic resonator.

Table 75. External clock drive

Direct drive with
Direct drive PLL usage
prescaler
fCPU = fXTAL fCPU = fXTAL x F
Parameter Symbol fCPU = fXTAL / 2 Unit

min. max. min. max. min. max.

XTAL1 period 1, 2 tOSC SR 15.625 – 83.3 250 83.3 250 ns

3
High time t1 SR 6 – 3 – 6 – ns
Low time 3 t2 SR 6 – 3 – 6 – ns
Rise time 3 t3 SR – 2 – 2 – 2 ns
Fall time 3 t4 SR – 2 – 2 – 2 ns

1. The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real
minimum value depends on the duty cycle of the input clock signal.
2. 4-8 MHz is the input frequency range when using an external clock source. 64 MHz can be applied with an
external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is
bypassed so it does not limit the input frequency.
3. The input clock signal must reach the defined levels VIL2 and VIH2.

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Figure 49. External clock drive XTAL1

t1 t3 t4

VIH2

VIL2
t2
tOSC

Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: when 64MHz is
used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when for instance
32MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again
equal to 7.8ns).

24.8.14 Memory cycle variables

The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.

Table 76. Memory cycle variables

Description Symbol Values

ALE Extension tA TCL x [ALECTL]

Memory Cycle Time wait states tC 2TCL x (15 - [MCTC])
Memory Tri-state Time tF 2TCL x (1 - [MTTC])

24.8.15 External memory bus timing

The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40MHz.
Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the
timing formulas become zero or negative which, in most cases is not acceptable or not
meaningless at all. In these cases, it is necessary to relax the speed of the bus setting
properly tA, tC and tF.
Note: All External Memory Bus Timings and SSC Timings reported in the following tables are
granted by Design Characterization and not fully tested in production.

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24.8.16 Multiplexed bus

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C, CL = 50pF,
ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40MHz CPU clock without wait states)

Table 77. Multiplexed bus timings

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

t5 CC ALE high time 4 + tA – TCL – 8.5 + tA – ns

t6 CC Address setup to ALE 1.5 + tA – TCL – 11 + tA – ns
t7 CC Address hold after ALE 4 + tA – TCL – 8.5 + tA – ns
ALE falling edge to RD, WR
t8 CC 4 + tA – TCL – 8.5 + tA – ns
(with RW-delay)
ALE falling edge to RD, WR
t9 CC – 8.5 + tA – – 8.5 + tA – ns
(no RW-delay)
Address float after RD, WR
t10 CC – 6 – 6 ns
(with RW-delay)1
Address float after RD, WR
t11 CC – 18.5 – TCL + 6 ns
(no RW-delay)1
RD, WR low time
t12 CC 15.5 + tC – 2TCL – 9.5 + tC – ns
(with RW-delay)
RD, WR low time
t13 CC 28 + tC – 3TCL – 9.5 + tC – ns
(no RW-delay)
RD to valid data in
t14 SR – 6 + tC – 2TCL – 19 + tC ns
(with RW-delay)
RD to valid data in
t15 SR – 18.5 + tC – 3TCL – 19 + tC ns
(no RW-delay)
17.5 + 3TCL – 20 +
t16 SR ALE low to valid data in – – ns
+ tA + tC + tA + tC
Address/Unlatched CS to valid 20 + 2tA + 4TCL – 30 +
t17 SR – – ns
data in + tC + 2tA + tC
Data hold after RD
t18 SR 0 – 0 – ns
rising edge
t19 SR Data float after RD1 – 16.5 + tF – 2TCL – 8.5 + tF ns
t22 CC Data valid to WR 10 + tC – 2TCL – 15 + tC – ns
t23 CC Data hold after WR 4 + tF – 2TCL – 8.5 + tF – ns
t25 CC ALE rising edge after RD, WR 15 + tF – 2TCL – 10 + tF – ns
Address/Unlatched CS hold
t27 CC 10 + tF – 2TCL – 15 + tF – ns
after RD, WR
t38 CC ALE falling edge to Latched CS – 4 – tA 10 – tA – 4 – tA 10 – tA ns

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Table 77. Multiplexed bus timings (continued)

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

Latched CS low to Valid Data 16.5 + tC + 3TCL – 21 +

t39 SR – – ns
In + 2tA + tC + 2tA
t40 CC Latched CS hold after RD, WR 27 + tF – 3TCL – 10.5 + tF – ns
ALE fall. edge to RdCS, WrCS
t42 CC 7 + tA – TCL – 5.5 + tA – ns
(with RW delay)
ALE fall. edge to RdCS, WrCS
t43 CC – 5.5 + tA – – 5.5 + tA – ns
(no RW delay)
Address float after RdCS,
t44 CC – 1.5 – 1.5 ns
WrCS (with RW delay)1
Address float after RdCS,
t45 CC – 14 – TCL + 1.5 ns
WrCS (no RW delay)1
RdCS to Valid Data In
t46 SR – 4 + tC – 2TCL – 21 + tC ns
(with RW delay)
RdCS to Valid Data In
t47 SR – 16.5 + tC – 3TCL – 21 + tC ns
(no RW delay)
RdCS, WrCS Low Time
t48 CC 15.5 + tC – 2TCL – 9.5 + tC – ns
(with RW delay)
RdCS, WrCS Low Time
t49 CC 28 + tC – 3TCL – 9.5 + tC – ns
(no RW delay)
t50 CC Data valid to WrCS 10 + tC – 2TCL – 15 + tC – ns
t51 SR Data hold after RdCS 0 – 0 – ns
t52 SR Data float after RdCS1 – 16.5 + tF – 2TCL – 8.5 + tF ns
Address hold after
t54 CC 6 + tF – 2TCL – 19 + tF – ns
RdCS, WrCS
t56 CC Data hold after WrCS 6 + tF – 2TCL – 19 + tF – ns

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Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE

t5 t16 t25
ALE

t6
t38 t40
t17
t39 t27
CSx

t6
t17 t27
A23-A16
(A15-A8) Address
BHE

t16
t6
Read cycle t7 t1
Address/data
bus (P0) Address Data in Address

t10 t19
t8
t14

RD
t12
t13
t9
t1

t15
Write cycle t23
Address/data
bus (P0) Address Data out

t8 t22
WR
WRL
t9
WRH t12
t13

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Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE

t5 t16 t25

ALE
t6
t38
t40
t17
t39 t27
CSx
t6
t17
A23-A16
(A15-A8) Address
BHE
t27

Read cycle t6 t7
Address/Data Address Data in
Bus (P0)
t18
t8 t10 t19
t9 t11
t14
RD
t15
t12
t13
Write cycle

Address/Data Address Data out

Bus (P0)
t23

t8 t10
t9 t11 t22
WR
WRL
WRH
t12
t13

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Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS

CLKOUT

t5 t16 t25

ALE

t6
t17 t27
A23-A16
(A15-A8) Address
BHE

t16
t6
Read Cycle t7 t51
Address/Data Address
Address Data In
Bus (P0)

t42 t44 t52

t46

RdCSx
t48
t49
t43 t45

t47
Write Cycle t55
Address/Data
Bus (P0) Address Data Out

t42 t50

WrCSx
t43 t48
t49

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Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS

CLKOUT

t5 t16 t25
ALE

t6
t17
A23-A16
(A15-A8) Address
BHE
t54

Read cycle t6 t7
Address/Data
Bus (P0) Address Data in

t42 t44 t18

t43 t45 t19
t46

RdCSx
t48
t47
t49

Write cycle
Address/data
bus (P0) Address Data out

t42 t44 t56

t43 t45 t50

WrCSx

t48
t49

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24.8.17 Demultiplexed bus

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C, CL = 50pF,
ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40MHz CPU clock without wait states).

Table 78. Demultiplexed bus timings

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

t5 CC ALE high time 4 + tA – TCL – 8.5 + tA – ns

t6 CC Address setup to ALE 1.5 + tA – TCL – 11 + tA – ns
Address/Unlatched CS setup
2TCL – 12.5 +
t80 CC to RD, WR 12.5 + 2tA – – ns
+ 2tA
(with RW-delay)
Address/Unlatched CS setup
t81 CC to RD, WR 0.5 + 2tA – TCL – 12 + 2tA – ns
(no RW-delay)
RD, WR low time
t12 CC 15.5 + tC – 2TCL – 9.5 + tC – ns
(with RW-delay)
RD, WR low time
t13 CC 28 + tC – 3TCL – 9.5 + tC – ns
(no RW-delay)
RD to valid data in
t14 SR – 6 + tC – 2TCL – 19 + tC ns
(with RW-delay)
RD to valid data in
t15 SR – 18.5 + tC – 3TCL – 19 + tC ns
(no RW-delay)
17.5 + tA + 3TCL – 20 +
t16 SR ALE low to valid data in – – ns
+ tC + tA + tC
Address/Unlatched CS to 20 + 2tA + 4TCL – 30 +
t17 SR – – ns
valid data in + tC + 2tA + tC
Data hold after RD
t18 SR 0 – 0 – ns
rising edge
Data float after RD rising 2TCL – 8.5 +
t20 SR – 16.5 + tF – ns
edge (with RW-delay)31 + tF + 2tA
Data float after RD rising TCL – 8.5 +
t21 SR – 4 + tF – ns
edge (no RW-delay) 1 + tF + 2tA
t22 CC Data valid to WR 10 + tC – 2TCL – 15 + tC – ns
t24 CC Data hold after WR 4 + tF – TCL – 8.5 + tF – ns
ALE rising edge after RD,
t26 CC –10 + tF – –10 + tF – ns
WR
Address/Unlatched CS hold
t28 CC 0 + tF – 0 + tF – ns
after RD, WR 2
Address/Unlatched CS hold
t28h CC – 5 + tF – – 5 + tF – ns
after WRH

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Table 78. Demultiplexed bus timings (continued)

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

ALE falling edge to Latched

t38 CC – 4 – tA 6 – tA – 4 – tA 6 – tA ns
CS
Latched CS low to Valid Data 16.5 + 3TCL – 21 +
t39 SR – – ns
In + tC + 2tA + tC + 2tA
Latched CS hold after RD,
t41 CC 2 + tF – TCL – 10.5 + tF – ns
WR
Address setup to RdCS,
t82 CC WrCS 14 + 2tA – 2TCL – 11 + 2tA – ns
(with RW-delay)
Address setup to RdCS,
t83 CC WrCS 2 + 2tA – TCL –10.5 + 2tA – ns
(no RW-delay)
RdCS to Valid Data In
t46 SR – 4 + tC – 2TCL – 21 + tC ns
(with RW-delay)
RdCS to Valid Data In
t47 SR – 16.5 + tC – 3TCL – 21 + tC ns
(no RW-delay)
RdCS, WrCS Low Time
t48 CC 15.5 + tC – 2TCL – 9.5 + tC – ns
(with RW-delay)
RdCS, WrCS Low Time
t49 CC 28 + tC – 3TCL – 9.5 + tC – ns
(no RW-delay)
t50 CC Data valid to WrCS 10 + tC – 2TCL – 15 + tC – ns
t51 SR Data hold after RdCS 0 – 0 – ns
Data float after RdCS
t53 SR – 16.5 + tF – 2TCL – 8.5 + tF ns
(with RW-delay) 3
Data float after RdCS
t68 SR – 4 + tF – TCL – 8.5 + tF ns
(no RW-delay) 3
Address hold after
t55 CC – 8.5 + tF – – 8.5 + tF – ns
RdCS, WrCS
t57 CC Data hold after WrCS 2 + tF – TCL – 10.5 + tF – ns

1. RW-delay and tA refer to the next following bus cycle.

2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.

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Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE

CLKOUT

t5 t9 t26

ALE
t6
t38 t41
t17
t41u
t39
CSx

t6
t17 t28 (or t28h)
A23-A16
A15-A0 (P1) Address
BHE

t18
Read cycle
Data bus (P0)
Data in
(D15-D8) D7-D0

t80 t14 t20

t81 t15 t21

RD

t12
t13
Write cycle
Data bus (P0) Data out
(D15-D8) D7-D0

t80
t22 t24
t81

WR
WRL
WRH t12
t13

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Figure 55. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE

CLKOUT
t5 t16 t26
ALE
t6
t38
t41
t17
t28
t39

CSx
t6
t17 t28

A23-A16
A15-A0 (P1) Address
BHE

t18
Read cycle
Data bus (P0)
(D15-D8) D7-D0 Data in

t80 t14 t20

t81 t15 t21

RD
t12

t13
Write cycle
Data bus (P0)
(D15-D8) D7-D0 Data out

t80
t81 t22 t24

WR
WRL
WRH t12

t13

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Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS

CLKOUT

t5 t16 t26

ALE

t6
t17 t55
A23-A16
A15-A0 (P1) Address
BHE

t5
Read cycle
Data bus (P0) Data in
(D15-D8) D7-D0

t82 t46 t53

t83 t47 t68

RdCSx
t48
t49
Write cycle
Data bus (P0)
Data out
(D15-D8) D7-D0

t82
t50 t57
t83

WrCSx

t48
t49

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Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS

CLKOUT
t5 t26
t16
ALE

t6
t17 t55
A23-A16
A15-A0 (P1) Address
BHE

t51
Read cycle
Data bus (P0)
(D15-D8) D7-D0 Data in

t82 t46 t53

t83 t47 t68

RdCSx
t48

t49
Write cycle
Data bus (P0)
Data out
(D15-D8) D7-D0

t82
t83 t50 t57

WrCSx

t48
t49

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ST10F272 Electrical characteristics

24.8.18 CLKOUT and READY

VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF

Table 79. CLKOUT and READY timings

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns

t30 CC CLKOUT high time 9 – TCL – 3.5 – ns
t31 CC CLKOUT low time 10 – TCL – 2.5 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
CLKOUT rising edge to
t34 CC – 2 + tA 8 + tA – 2 + tA 8 + tA ns
ALE falling edge
Synchronous READY
t35 SR 17 – 17 – ns
setup time to CLKOUT
Synchronous READY
t36 SR 2 – 2 – ns
hold time after CLKOUT
Asynchronous READY
t37 SR 35 – 2TCL + 10 – ns
low time
Asynchronous READY
t58 SR 17 – 17 – ns
setup time 1
Asynchronous READY
t59 SR 2 – 2 – ns
hold time 1
Async. READY hold time after
t60 SR RD, WR high (Demultiplexed 0 2tA + tC + tF 0 2tA + tC + tF ns
Bus) 2

1. These timings are given for characterization purposes only, in order to assure recognition at a specific
clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers
to the current bus cycle.

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Figure 58. CLKOUT and READY

READY
Running cycle 1) wait state MUX / Tri-state 6)

t32 t33
CLKOUT
t30
t29
t31
t34
ALE
7)

RD, WR 2)

t35 t36 t35 t36

Synchronous

READY 3)
3)

t58 t59 t58 t59 t60 4)

Asynchronous

READY 3) 3)

t37 5) 6)

1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is
guaranteed, if READY is removed in response to the command (see Note 4).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
7. The next external bus cycle may start here.

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24.8.19 External bus arbitration

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Table 80. External bus arbitration timings

FCPU = 40 MHz Variable CPU Clock
TCL = 12.5 ns 1/2 TCL = 1 to 64MHz

Unit
Symbol Parameter
min. max. min. max.

HOLD input setup time

t61 SR 18.5 – 18.5 – ns
to CLKOUT
CLKOUT to HLDA high
t62 CC – 12.5 – 12.5 ns
or BREQ low delay
CLKOUT to HLDA low
t63 CC – 12.5 – 12.5 ns
or BREQ high delay
t64 CC CSx release 1) – 20 – 20 ns
t65 CC CSx drive –4 15 –4 15 ns
t66 1)
CC Other signals release – 20 – 20 ns
t67 CC Other signals drive –4 15 –4 15 ns

1. Partially tested, guaranteed by design characterization.

Figure 59. External bus arbitration (releasing the bus)

CLKOUT
t61

HOLD
t63

HLDA 1)
t62

BREQ 2)
t64 3)
CSx
(P6.x)
t66
1)
Others

1. The ST10F272 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t64.

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Figure 60. External bus arbitration (regaining the bus)

2)
CLKOUT

t61

HOLD
t62

HLDA
t62 t62 t63

BREQ 1)

t65
CSx
(On P6.x)
t67
Other
signals

1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated
earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be
deactivated without the ST10F272 requesting the bus.
2. The next ST10F272 driven bus cycle may start here.

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24.8.20 High-speed synchronous serial interface (SSC) timing

24.8.20.1 Master mode
VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Table 81. SSC master mode timings

Max. Baudrate 6.6MBd Variable Baudrate
(1)
@FCPU = 40MHz (<SSCBR> = 0001h -
Symbol Parameter (<SSCBR> = 0002h) FFFFh) Unit

min. max. min. max.

t300 CC SSC clock cycle time(2)) 150 150 8TCL 262144 TCL ns
t301 CC SSC clock high time 63 – t300 / 2 – 12 – ns
t302 CC SSC clock low time 63 – t300 / 2 – 12 – ns
t303 CC SSC clock rise time – 10 – 10 ns
t304 CC SSC clock fall time – 10 – 10 ns
t305 CC Write data valid after shift edge – 15 – 15 ns
t306 CC Write data hold after shift edge(3) –2 – –2 – ns
Read data setup time before latch
t307p SR edge, phase error detection on 37.5 – 2TCL + 12.5 – ns
(SSCPEN = 1)
Read data hold time after latch
t308p SR edge, phase error detection on 50 – 4TCL – ns
(SSCPEN = 1)
Read data setup time before latch
t307 SR edge, phase error detection off 25 – 2TCL – ns
(SSCPEN = 0)
Read data hold time after latch
t308 SR edge, phase error detection off 0 – 0 – ns
(SSCPEN = 0)
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only
with CPU clock equal to (or lower than) 32MHz.
2. Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud).
3. Partially tested, guaranteed by design characterization.

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Figure 61. SSC master timing

1) t300 t301 t302 2)

SCLK

t304 t303
t305 t305 t306 t305

MTSR 1st out bit 2nd out bit Last out bit

t307 t308 t307 t308

MRST 1st in bit 2nd In bit Last in bit

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.

24.8.20.2 Slave mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Table 82. SSC slave mode timings

Max. Baudrate
Variable Baudrate
6.6 MBd (1))
(<SSCBR> = 0001h -
@FCPU = 40MHz
Symbol Parameter FFFFh) Unit
(<SSCBR> = 0002h)

min. max. min. max.

t310 SR SSC clock cycle time(2) 150 150 8TCL 262144 TCL ns
t311 SR SSC clock high time 63 – t310 / 2 – 12 – ns
t312 SR SSC clock low time 63 – t310 / 2 – 12 – ns
t313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 55 – 2TCL + 30 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
Read data setup time before latch
t317p SR edge, phase error detection on 62 – 4TCL + 12 – ns
(SSCPEN = 1)
Read data hold time after latch
t318p SR edge, phase error detection on 87 – 6TCL + 12 – ns
(SSCPEN = 1)

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Table 82. SSC slave mode timings (continued)

Max. Baudrate
Variable Baudrate
6.6 MBd (1))
(<SSCBR> = 0001h -
@FCPU = 40MHz
Symbol Parameter FFFFh) Unit
(<SSCBR> = 0002h)

min. max. min. max.

Read data setup time before latch

t317 SR edge, phase error detection off 6 – 6 – ns
(SSCPEN = 0)
Read data hold time after latch
t318 SR edge, phase error detection off 31 – 2TCL + 6 – ns
(SSCPEN = 0)
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only
with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).
2. Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).

Figure 62. SSC slave timing

t310 t311 t312 2)

1)

SCLK
t314 t313
t315 t315 t316 t315

MRST 1st out bit 2nd out bit Last out bit

t317 t318 t317 t318

MTSR 1st in bit 2nd in bit Last in bit

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.

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Package information ST10F272

25 Package information

Figure 63. PQFP144 mechanical data and package dimension

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 4.07 0.160

A1 0.25 0.010

A2 3.17 3.42 3.67 0.125 0.135 0.144

B 0.22 0.38 0.009 0.015

C 0.13 0.23 0.005 0.009

D 30.95 31.20 31.45 1.219 1.228 1.238

D1 27.90 28.00 28.10 1.098 1.102 1.106

D3 22.75 0.896

e 0.65 0.026

E 30.95 31.20 31.45 1.219 1.228 1.238

E1 27.90 28.00 28.10 1.098 1.102 1.106

E3 22.75 0.896

L 0.65 0.80 0.95 0.026 0.031 0.037

L1 1.60 0.063
PQFP144
K 0°(min.), 7°(max.)

D1
A
D3
A2
A1

108 73
109 72
0.10mm
.004
Seating Plane
B
B

E3

E1

144 37

1 36
C
e
L1

K
PQFP144

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ST10F272 Package information

Figure 64. 144-pin low profile quad flat package (10x10)

mm inches(1)
Dim.
D Min Typ Max Min Typ Max
D1 A 1.60 0.063
A
D3 A2
A1
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.057
108 73
109 72 b 0.17 0.22 0.27 0.007 0.011
0.08 mm
.003 in. b c 0.09 0.20 0.004 0.008
Seating Plane
b
D 21.80 22.00 22.20 0.858 0.867 0.874
E3 E1 E D1 19.80 20.00 20.20 0.780 0.787 0.795
D3 17.50 0.689
E 21.80 22.00 22.20 0.858 0.867 0.874
144 37 E1 19.80 20.00 20.20 0.780 0.787 0.795
1 36
c E3 17.50 0.689
e e 0.50 0.020
L1
L K 0° 3.5° 7° 0° 3.5° 7°
h L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of Pins
N 144
1.Values in inches are converted from mm and
rounded to 3 decimal digits.

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Revision history ST10F272

26 Revision history

Table 83. Document revision history

Date Revision Changes

29-Jun-2006 1 Initial release on www.st.com

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ST10F272

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