ST72F521, ST72521B

80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,

FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

■ Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
■ Clock, Reset And Supply Management TQFP64
– Enhanced low voltage supervisor (LVD) for 14 x 14
TQFP64
main supply and auxiliary voltage detector TQFP80 10 x 10
(AVD) with interrupt capability 14 x 14
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator and bypass for
external clock
– PLL for 2x frequency multiplication
– Four power saving modes: Halt, Active-Halt, ■ 4 Communications Interfaces
Wait and Slow
■ Interrupt Management – SPI synchronous serial interface
– SCI asynchronous serial interface
– Nested interrupt controller
– I2C multimaster interface
– 14 interrupt vectors plus TRAP and RESET (SMbus V1.1 compliant)
– Top Level Interrupt (TLI) pin – CAN interface (2.0B Passive)
– 15 external interrupt lines (on 4 vectors) ■ Analog periperal (low current coupling)
■ Up to 64 I/O Ports – 10-bit ADC with 16 input robust input ports
– 48 multifunctional bidirectional I/O lines
– 34 alternate function lines
■ Instruction Set
– 16 high sink outputs
■ 5 Timers – 8-bit Data Manipulation
– 63 Basic Instructions
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities – 17 main Addressing Modes
– Configurable watchdog timer – 8 x 8 Unsigned Multiply Instruction
– Two 16-bit timers with: 2 input captures, 2 out- ■ Development Tools
put compares, external clock input on one tim- – Full hardware/software development package
er, PWM and pulse generator modes
– In-Circuit Testing capability
– 8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
and time base interrupt, external clock with
event detector
Device Summary
Features ST72F521(M/R/AR)9 ST72F521(R/AR)6 ST72521B(M/R/AR)9 ST72521B(R/AR)6
Program memory - bytes Flash 60K Flash 32K ROM 60K ROM 32K
RAM (stack) - bytes 2048 (256) 1024 (256) 2048 (256) 1024 (256)
Operating Voltage 3.8V to 5.5V
Temp. Range up to -40°C to +125 °C
TQFP80 14x14 (M), TQFP80 14x14 (M),
TQFP64 14x14 (R), TQFP64 TQFP64 14x14 (R), TQFP64
Package TQFP64 14x14 (R), TQFP64 14x14 (R),
10x10 (AR) 10x10 (AR)
TQFP64 10x10 (AR) TQFP64 10x10 (AR)

Rev. 5

May 2005 1/215

1
 Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
. . . . 42
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 58
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.5 List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.9 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215. . . 165
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

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 Table of Contents
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 168
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.4.1 CURRENT CONSUMPTION ..................................... 169
12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 179
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 181
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 189
12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.11.3 CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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 Table of Contents
12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 201
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 203
14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.2 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.3 Reset pin protection with LVD Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.8 CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.9 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.2 ALL FLASH DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.1 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.2 I/O behaviour during ICC mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.3 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

215

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 ST72F521, ST72521B

1 INTRODUCTION reducing power consumption when the application

is in idle or stand-by state.
The ST72F521 and ST72521B devices are mem-
bers of the ST7 microcontroller family designed for The enhanced instruction set and addressing
mid-range applications with a CAN bus interface modes of the ST7 offer both power and flexibility to
(Controller Area Network). software developers, enabling the design of highly
efficient and compact application code. In addition
All devices are based on a common industry- to standard 8-bit data management, all ST7 micro-
standard 8-bit core, featuring an enhanced instruc- controllers feature true bit manipulation, 8x8 un-
tion set and are available with FLASH or ROM pro- signed multiplication and indirect addressing
gram memory. modes.
Under software control, all devices can be placed Related Documentation
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
AN1131: Migrating applications from ST72511/
311/314 to ST72521/321/324
Figure 1. Device Block Diagram

8-BIT CORE PROGRAM

ALU MEMORY
(32K - 60K Bytes)
RESET
CONTROL
VPP
RAM
TLI
VSS (1024-2048 Bytes)
VDD LVD

EVD AVD
WATCHDOG
OSC1
OSC
OSC2
I2C
ADDRESS AND DATA BUS

PA7:0
MCC/RTC/BEEP (8-bits)
PORT A

PORT F
PF7:0 PORT B
(8-bits) PB7:0
TIMER A (8-bits)
PWM ART

BEEP
PORT C

PORT E
TIMER B PC7:0
PE7:0 (8-bits)
(8-bits)
CAN
SPI

SCI

PORT G1 PG7:0
PORT D (8-bits)
PD7:0
(8-bits)
10-BIT ADC PORT H1 PH7:0
(8-bits)
VAREF
VSSA

1On some devices only, see Device Summary on page 1

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ST72F521, ST72521B

2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout

PA6 (HS) / SDAI

PA7 (HS) / SCLI
PE3 / CANRX

VPP / ICCSEL
PE2 / CANTX

PE0 / TDO
PE1 / RDI

PA5 (HS)
PA4 (HS)
RESET
VDD_2

VSS_2
OSC1
OSC2

EVD
PH7
PH6
PH5
PH4
TLI
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(HS) PE4 1 60 VSS_1
(HS) PE5 2 59 VDD_1
(HS) PE6 3 58 PA3 (HS)
(HS) PE7 4 ei0 57 PA2
PWM3 / PB0 5 56 PA1
PWM2 / PB1 6 55 PA0
ei2
PWM1 / PB2 7 54 PC7 / SS / AIN15
PWM0 / PB3 8 53 PC6 / SCK /ICCCLK
PG0 9 52 PH3
PG1 10 51 PH2
PG2 11 50 PH1
PG3 12 49 PH0
ARTCLK / (HS) PB4 13 48 PC5 / MOSI / AIN14
ARTIC1 / PB5 14 47 PC4 / MISO / ICCDATA
ARTIC2 / PB6 15 ei3 46 PC3 (HS) /ICAP1_B
PB7 16 45 PC2(HS) / ICAP2_B
AIN0 / PD0 17 44 PC1 / OCMP1_B / AIN13
AIN1 / PD1 18 43 PC0 / OCMP2_B /AIN12
AIN2 / PD2 19 42 VSS_0
ei1
AIN3 / PD3 20 41 VDD_0
21
22
23
24
25
26
27
28
29
30

32

34
35
36
37
38
39
40
31

33
VAREF

EXTCLK_A / (HS) PF7

VSSA

BEEP / (HS) PF1

(HS) PF2
OCMP2_A / AIN9 /PF3

ICAP1_A / (HS) / PF6

PG6
PG7
AIN4/PD4

VDD3
VSS3
PG4
PG5
MCO /AIN8 / PF0
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7

OCMP1_A/AIN10 /PF4
ICAP2_A/ AIN11 /PF5

(HS) 20mA high sink capability

eix associated external interrupt vector

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 ST72F521, ST72521B

PIN DESCRIPTION (Cont’d)

Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout

PA6 (HS) / SDAI

PA7 (HS) / SCLI
PE3 / CANRX

VPP / ICCSEL
PE2 / CANTX

PE0 / TDO
PE1 / RDI

PA5 (HS)
PA4 (HS)
RESET
VDD_2

VSS_2
OSC1
OSC2

EVD
TLI
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
(HS) PE4 1 48 VSS_1
(HS) PE5 2 47 VDD_1
(HS) PE6 3 46 PA3 (HS)
(HS) PE7 4 45 PA2
ei0
PWM3 / PB0 5 44 PA1
PWM2 / PB1 6 43 PA0
PWM1 / PB2 ei2 42 PC7 / SS / AIN15
7
PWM0 / PB3 8 41 PC6 / SCK / ICCCLK
ARTCLK / (HS) PB4 9 40 PC5 / MOSI / AIN14
ARTIC1 / PB5 10 39 PC4 / MISO / ICCDATA
ARTIC2 / PB6 11 ei3 38 PC3 (HS) / ICAP1_B
PB7 12 37 PC2 (HS) / ICAP2_B
AIN0 / PD0 13 36 PC1 / OCMP1_B / AIN13
AIN1 / PD1 14 35 PC0 / OCMP2_B / AIN12
AIN2 / PD2 15 ei1 34 VSS_0
AIN3 / PD3 16 33 VDD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ICAP1_A / (HS) PF6
BEEP / (HS) PF1

EXTCLK_A / (HS) PF7

OCMP2_A / AIN9 / PF3
VSSA
VDD_3
VSS_3
MCO / AIN8 / PF0
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7

(HS) PF2

OCMP1_A / AIN10 / PF4

VAREF

ICAP2_A / AIN11 / PF5

(HS) 20mA high sink capability

eix associated external interrupt vector

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ST72F521, ST72521B

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 165.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
TT= TTL 0.8V / 2V with Schmitt trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output: OD = open drain 2), PP = push-pull
Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n° Level Port
Main
Type

function
TQFP80

TQFP64

Input Output
Output

Pin Name Alternate function

Input

(after
float
wpu

ana

reset)
OD

PP
int

1 1 PE4 (HS) I/O CT HS X X X X Port E4

2 2 PE5 (HS) I/O CT HS X X X X Port E5
3 3 PE6 (HS) I/O CT HS X X X X Port E6
4 4 PE7 (HS) I/O CT HS X X X X Port E7
5 5 PB0/PWM3 I/O CT X ei2 X X Port B0 PWM Output 3
6 6 PB1/PWM2 I/O CT X ei2 X X Port B1 PWM Output 2
7 7 PB2/PWM1 I/O CT X ei2 X X Port B2 PWM Output 1
8 8 PB3/PWM0 I/O CT X ei2 X X Port B3 PWM Output 0
9 - PG0 I/O TT X X X X Port G0
10 - PG1 I/O TT X X X X Port G1
11 - PG2 I/O TT X X X X Port G2
12 - PG3 I/O TT X X X X Port G3
13 9 PB4 (HS)/ARTCLK I/O CT HS X ei3 X X Port B4 PWM-ART External Clock
14 10 PB5/ARTIC1 I/O CT X ei3 X X Port B5 PWM-ART Input Capture 1
15 11 PB6/ARTIC2 I/O CT X ei3 X X Port B6 PWM-ART Input Capture 2
16 12 PB7 I/O CT X ei3 X X Port B7
17 13 PD0 /AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
18 14 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
19 15 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
20 16 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3
21 - PG6 I/O TT X X X X Port G6
22 - PG7 I/O TT X X X X Port G7
23 17 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4

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 ST72F521, ST72521B

Pin n° Level Port

Main

Type
function
TQFP80

TQFP64

Input Output

Output
Pin Name Alternate function

Input
(after

float
wpu

ana
reset)

OD

PP
int
24 18 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5
25 19 PD6/AIN6 I/O CT X X X X X Port D6 ADC Analog Input 6
26 20 PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7
27 21 VAREF I Analog Reference Voltage for ADC
28 22 VSSA S Analog Ground Voltage
29 23 VDD_3 S Digital Main Supply Voltage
30 24 VSS_3 S Digital Ground Voltage
31 - PG4 I/O TT X X X X Port G4
32 - PG5 I/O TT X X X X Port G5
Main clock ADC Analog
33 25 PF0/MCO/AIN8 I/O CT X ei1 X X X Port F0
out (fCPU) Input 8
34 26 PF1 (HS)/BEEP I/O CT HS X ei1 X X Port F1 Beep signal output
35 27 PF2 (HS) I/O CT HS X ei1 X X Port F2
Timer A Out-
ADC Analog
36 28 PF3/OCMP2_A/AIN9 I/O CT X X X X X Port F3 put Compare
Input 9
2
Timer A Out-
ADC Analog
37 29 PF4/OCMP1_A/AIN10 I/O CT X X X X X Port F4 put Compare
Input 10
1
Timer A Input ADC Analog
38 30 PF5/ICAP2_A/AIN11 I/O CT X X X X X Port F5
Capture 2 Input 11
39 31 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
Timer A External Clock
40 32 PF7 (HS)/EXTCLK_A I/O CT HS X X X X Port F7
Source
41 33 VDD_0 S Digital Main Supply Voltage
42 34 VSS_0 S Digital Ground Voltage
Timer B Out-
ADC Analog
43 35 PC0/OCMP2_B/AIN12 I/O CT X X X X X Port C0 put Compare
Input 12
2
Timer B Out-
ADC Analog
44 36 PC1/OCMP1_B/AIN13 I/O CT X X X X X Port C1 put Compare
Input 13
1
45 37 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
46 38 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
SPI Master In
ICC Data In-
47 39 PC4/MISO/ICCDATA I/O CT X X X X Port C4 / Slave Out
put
Data
SPI Master
ADC Analog
48 40 PC5/MOSI/AIN14 I/O CT X X X X X Port C5 Out / Slave In
Input 14
Data
49 - PH0 I/O TT X X X X Port H0
50 - PH1 I/O TT X X X X Port H1
51 - PH2 I/O TT X X X X Port H2

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ST72F521, ST72521B

Pin n° Level Port

Main

Type
function
TQFP80

TQFP64

Input Output

Output
Pin Name Alternate function

Input
(after

float
wpu

ana
reset)

OD

PP
int
52 - PH3 I/O TT X X X X Port H3
SPI Serial ICC Clock
Clock Output
53 41 PC6/SCK/ICCCLK I/O CT X X X X Port C6 Caution: Negative current
injection not allowed on this
pin5)
SPI Slave
ADC Analog
54 42 PC7/SS/AIN15 I/O CT X X X X X Port C7 Select (active
Input 15
low)
55 43 PA0 I/O CT X ei0 X X Port A0
56 44 PA1 I/O CT X ei0 X X Port A1
57 45 PA2 I/O CT X ei0 X X Port A2
58 46 PA3 (HS) I/O CT HS X ei0 X X Port A3
59 47 VDD_1 S Digital Main Supply Voltage
60 48 VSS_1 S Digital Ground Voltage
61 49 PA4 (HS) I/O CT HS X X X X Port A4
62 50 PA5 (HS) I/O CT HS X X X X Port A5
63 51 PA6 (HS)/SDAI I/O CT HS X T Port A6 I2C Data 1)
64 52 PA7 (HS)/SCLI I/O CT HS X T Port A7 I2C Clock 1)
Must be tied low. In flash programming
mode, this pin acts as the programming
65 53 VPP/ ICCSEL I voltage input VPP. See Section 12.9.2
for more details. High voltage must not
be applied to ROM devices
66 54 RESET I/O CT Top priority non maskable interrupt.
67 55 EVD External voltage detector
68 56 TLI I CT X X Top level interrupt input pin
69 - PH4 I/O TT X X X X Port H4
70 - PH5 I/O TT X X X X Port H5
71 - PH6 I/O TT X X X X Port H6
72 - PH7 I/O TT X X X X Port H7
73 57 VSS_2 S Digital Ground Voltage
74 58 OSC23) I/O Resonator oscillator inverter output
External clock input or Resonator oscil-
75 59 OSC13) I
lator inverter input
76 60 VDD_2 S Digital Main Supply Voltage
77 61 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
78 62 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In
79 63 PE2/CANTX I/O CT X Port E2 CAN Transmit Data Output
80 64 PE3/CANRX I/O CT X X X X Port E3 CAN Receive Data Input

Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

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 ST72F521, ST72521B

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 47. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input
pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid add-
ed current consumption.

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ST72F521, ST72521B

3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of ad- IMPORTANT: Memory locations marked as “Re-
dressing 64K bytes of memories and I/O registers. served” must never be accessed. Accessing a re-
The available memory locations consist of 128 seved area can have unpredictable effects on the
bytes of register locations, up to 2Kbytes of RAM device.
and up to 60Kbytes of user program memory. The Related Documentation
RAM space includes up to 256 bytes for the stack AN 985: Executing Code in ST7 RAM
from 0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map

0000h 0080h
HW Registers
Short Addressing
(see Table 2)
007Fh RAM (zero page)
0080h 00FFh
0100h
RAM 256 Bytes Stack
(2048 or 1024 Bytes)
01FFh
0200h 1000h
087Fh 16-bit Addressing 60 KBytes
0880h
Reserved RAM
or 047Fh
0FFFh or 067Fh
1000h or 087Fh 8000h
Program Memory 32 KBytes
(60K or 32K)
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 7) FFFFh
FFFFh

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 ST72F521, ST72521B

Table 2. Hardware Register Map

Register Reset
Address Block Register Name Remarks
Label Status

0000h PADR Port A Data Register 00h1) R/W

0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W

0003h PBDR Port B Data Register 00h1) R/W

0004h Port B PBDDR Port B Data Direction Register 00h R/W
0005h PBOR Port B Option Register 00h R/W

0006h PCDR Port C Data Register 00h1) R/W

0007h Port C PCDDR Port C Data Direction Register 00h R/W
0008h PCOR Port C Option Register 00h R/W

0009h PDDR Port D Data Register 00h1) R/W

000Ah Port D PDDDR Port D Data Direction Register 00h R/W
000Bh PDOR Port D Option Register 00h R/W

000Ch PEDR Port E Data Register 00h1) R/W

000Dh Port E PEDDR Port E Data Direction Register 00h R/W2)
000Eh PEOR Port E Option Register 00h R/W2)

000Fh PFDR Port F Data Register 00h1) R/W

0010h Port F PFDDR Port F Data Direction Register 00h R/W
0011h PFOR Port F Option Register 00h R/W

0012h PGDR Port G Data Register 00h1) R/W

2)
0013h Port G PGDDR Port G Data Direction Register 00h R/W
0014h PGOR Port G Option Register 00h R/W

0015h PHDR Port H Data Register 00h1) R/W

0016h Port H 2) PHDDR Port H Data Direction Register 00h R/W
0017h PHOR Port H Option Register 00h R/W

0018h I2CCR I2C Control Register 00h R/W

0019h I2CSR1 I2C Status Register 1 00h Read Only
001Ah I2CSR2 I2C Status Register 2 00h Read Only
001Bh I2C I2CCCR I2C Clock Control Register 00h R/W
001Ch I2COAR1 I2C Own Address Register 1 00h R/W
001Dh I2COAR2 I2C Own Address Register2 00h R/W
001Eh I2CDR I2C Data Register 00h R/W

001Fh
Reserved Area (2 Bytes)
0020h

0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPICSR SPI Control/Status Register 00h R/W

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ST72F521, ST72521B

Register Reset
Address Block Register Name Remarks
Label Status

0024h ISPR0 Interrupt Software Priority Register 0 FFh R/W

0025h ISPR1 Interrupt Software Priority Register 1 FFh R/W
0026h ISPR2 Interrupt Software Priority Register 2 FFh R/W
ITC
0027h ISPR3 Interrupt Software Priority Register 3 FFh R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W

002Ch MCCSR Main Clock Control / Status Register 00h R/W

MCC
002Dh MCCBCR Main Clock Controller: Beep Control Register 00h R/W

002Eh
to Reserved Area (3 Bytes)
0030h

0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TACSR Timer A Control/Status Register xxxx x0xx b R/W
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register xxh Read Only
003Dh TAIC2LR Timer A Input Capture 2 Low Register xxh Read Only
003Eh TAOC2HR Timer A Output Compare 2 High Register 80h R/W
003Fh TAOC2LR Timer A Output Compare 2 Low Register 00h R/W

0040h Reserved Area (1 Byte)

0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBCSR Timer B Control/Status Register xxxx x0xx b R/W
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W

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 ST72F521, ST72521B

Register Reset
Address Block Register Name Remarks
Label Status

0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00h R/W
0053h SCICR1 SCI Control Register 1 x000 0000b R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0056h Reserved area ---
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W

0058h
Reserved Area (2 Bytes)
0059h

005Ah CANISR CAN Interrupt Status Register 00h R/W

005Bh CANICR CAN Interrupt Control Register 00h R/W
005Ch CANCSR CAN Control / Status Register 00h R/W
005Dh CANBRPR CAN Baud Rate Prescaler Register 00h R/W
005Eh CAN CANBTR CAN Bit Timing Register 23h R/W
005Fh CANPSR CAN Page Selection Register 00h R/W
0060h First address -- See CAN
to to Description
006Fh Last address of CAN page x

0070h ADCCSR Control/Status Register 00h R/W

0071h ADC ADCDRH Data High Register 00h Read Only
0072h ADCDRL Data Low Register 00h Read Only

0073h PWMDCR3 PWM AR Timer Duty Cycle Register 3 00h R/W

0074h PWMDCR2 PWM AR Timer Duty Cycle Register 2 00h R/W
0075h PWMDCR1 PWM AR Timer Duty Cycle Register 1 00h R/W
0076h PWMDCR0 PWM AR Timer Duty Cycle Register 0 00h R/W
0077h PWMCR PWM AR Timer Control Register 00h R/W
0078h PWM ART ARTCSR Auto-Reload Timer Control/Status Register 00h R/W
0079h ARTCAR Auto-Reload Timer Counter Access Register 00h R/W
007Ah ARTARR Auto-Reload Timer Auto-Reload Register 00h R/W
007Bh ARTICCSR AR Timer Input Capture Control/Status Reg. 00h R/W
007Ch ARTICR1 AR Timer Input Capture Register 1 00h Read Only
007Dh ARTICR2 AR Timer Input Capture Register 1 00h Read Only

007Eh
Reserved Area (2 Bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.

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ST72F521, ST72521B

4 FLASH PROGRAM MEMORY

4.1 Introduction sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
The ST7 dual voltage High Density Flash erasing of the whole Flash memory when only a
(HDFlash) is a non-volatile memory that can be partial erasing is required.
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba- The first two sectors have a fixed size of 4 Kbytes
sis using an external VPP supply. (see Figure 5). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
The HDFlash devices can be programmed and terrupt vectors are located in Sector 0 (F000h-
erased off-board (plugged in a programming tool) FFFFh).
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming). Table 3. Sectors available in Flash devices
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting Flash Size (bytes) Available Sectors
other sectors. 4K Sector 0
8K Sectors 0,1
4.2 Main Features > 8K Sectors 0,1, 2
■ Three Flash programming modes:
– Insertion in a programming tool. In this mode, 4.3.1 Read-out Protection
all sectors including option bytes can be pro- Read-out protection, when selected, provides a
grammed or erased. protection against Program Memory content ex-
– ICP (In-Circuit Programming). In this mode, all traction and against write access to Flash memo-
sectors including option bytes can be pro-
grammed or erased without removing the de- ry. Even if no protection can be considered as to-
vice from the application board. tally unbreakable, the feature provides a very high
– IAP (In-Application Programming) In this level of protection for a general purpose microcon-
mode, all sectors except Sector 0, can be pro- troller.
grammed or erased without removing the de- In flash devices, this protection is removed by re-
vice from the application board and while the
application is running. programming the option. In this case, the entire
■ ICT (In-Circuit Testing) for downloading and program memory is first automatically erased and
executing user application test patterns in RAM the device can be reprogrammed.
■ Read-out protection Read-out protection selection depends on the de-
vice type:
■ Register Access Security System (RASS) to
prevent accidental programming or erasing – In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
4.3 Structure – In ROM devices it is enabled by mask option
specified in the Option List.
The Flash memory is organised in sectors and can
be used for both code and data storage. Note: In flash devices, the LVD is not supported if
read-out protection is enabled.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
Figure 5. Memory Map and Sector Address
4K 8K 10K 16K 24K 32K 48K 60K FLASH
1000h MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
DFFFh
EFFFh
4 Kbytes SECTOR 1
FFFFh
4 Kbytes SECTOR 0

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 ST72F521, ST72521B

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface – ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 6). – ICCSEL/VPP: programming voltage
These pins are: – OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset – VDD: application board power supply (option-
– VSS: device power supply ground al, see Figure 6, Note 3)
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR

ICC Cable
APPLICATION BOARD

(See Note 3) ICC CONNECTOR

OPTIONAL HE10 CONNECTOR TYPE
(See Note 4) 9 7 5 3 1

10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2

10kΩ

APPLICATION CL2 CL1

POWER SUPPLY See Note 1

APPLICATION
RESET

ICCCLK

ICCDATA
OSC1

ICCSEL/VPP
OSC2

VSS
VDD

I/O

ST7

Notes:
1. If the ICCCLK or ICCDATA pins are only used agement IC with open drain output and pull-up re-
as outputs in the application, no signal isolation is sistor>1K, no additional components are needed.
necessary. As soon as the Programming Tool is In all cases the user must ensure that no external
plugged to the board, even if an ICC session is not reset is generated by the application during the
in progress, the ICCCLK and ICCDATA pins are ICC session.
not available for the application. If they are used as 3. The use of Pin 7 of the ICC connector depends
inputs by the application, isolation such as a serial on the Programming Tool architecture. This pin
resistor has to implemented in case another de- must be connected when using most ST Program-
vice forces the signal. Refer to the Programming ming Tools (it is used to monitor the application
Tool documentation for recommended resistor val- power supply). Please refer to the Programming
ues. Tool manual.
2. During the ICC session, the programming tool 4. Pin 9 has to be connected to the OSC1 or OS-
must control the RESET pin. This can lead to con- CIN pin of the ST7 when the clock is not available
flicts between the programming tool and the appli- in the application or if the selected clock option is
cation reset circuit if it drives more than 5mA at not programmed in the option byte. ST7 devices
high level (push pull output or pull-up resistor<1K). with multi-oscillator capability need to have OSC2
A schottky diode can be used to isolate the appli- grounded in this case.
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-

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ST72F521, ST72521B

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming) possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
To perform ICP the microcontroller must be mode can be used to program any of the Flash
switched to ICC (In-Circuit Communication) mode sectors except Sector 0, which is write/erase pro-
by an external controller or programming tool. tected to allow recovery in case errors occur dur-
Depending on the ICP code downloaded in RAM, ing the programming operation.
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca- 4.7 Related Documentation
tions, or selection serial communication interface
for downloading). For details on Flash programming and ICC proto-
When using an STMicroelectronics or third-party col, refer to the ST7 Flash Programming Refer-
programming tool that supports ICP and the spe- ence Manual and to the ST7 ICC Protocol Refer-
cific microcontroller device, the user needs only to ence Manual.
implement the ICP hardware interface on the ap- 4.7.1 Register Description
plication board (see Figure 6). For more details on FLASH CONTROL/STATUS REGISTER (FCSR)
the pin locations, refer to the device pinout de-
scription. Read/Write
Reset Value: 0000 0000 (00h)
4.6 IAP (In-Application Programming)
7 0
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
0 0 0 0 0 0 0 0
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us- This register is reserved for use by Programming
er-defined strategy for entering programming Tool software. It controls the Flash programming
mode, choice of communications protocol used to and erasing operations.
fetch the data to be stored, etc.). For example, it is
Figure 7. Flash Control/Status Register Address and Reset Value
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
FCSR
0029h
Reset Value 0 0 0 0 0 0 0 0

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 ST72F521, ST72521B

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION 5.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains The 6 CPU registers shown in Figure 8 are not
six internal registers allowing efficient 8-bit data present in the memory mapping and are accessed
manipulation. by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES The Accumulator is an 8-bit general purpose reg-
■ Enable executing 63 basic instructions ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
■ Fast 8-bit by 8-bit multiply data.
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
■ Two 8-bit index registers These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
■ 16-bit stack pointer manipulation. (The Cross-Assembler generates a
■ Low power HALT and WAIT modes precede instruction (PRE) to indicate that the fol-
■ Priority maskable hardware interrupts lowing instruction refers to the Y register.)
■ Non-maskable software/hardware interrupts The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers

7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 I1 H I0 N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

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ST72F521, ST72521B

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC) Bit 1 = Z Zero.
Read/Write This bit is set and cleared by hardware. This bit in-
Reset Value: 111x1xxx dicates that the result of the last arithmetic, logical
or data manipulation is zero.
7 0 0: The result of the last operation is different from
zero.
1 1 I1 H I0 N Z C 1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
The 8-bit Condition Code register contains the in- instructions.
terrupt masks and four flags representative of the
Bit 0 = C Carry/borrow.
result of the instruction just executed. This register
can also be handled by the PUSH and POP in- This bit is set and cleared by hardware and soft-
structions. ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
These bits can be individually tested and/or con- 0: No overflow or underflow has occurred.
trolled by specific instructions. 1: An overflow or underflow has occurred.
Arithmetic Management Bits This bit is driven by the SCF and RCF instructions
Bit 4 = H Half carry. and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
This bit is set by hardware when a carry occurs be- rotate instructions.
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during Interrupt Management Bits
the same instructions.
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred. The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou- Interrupt Software Priority I1 I0
tines. Level 0 (main) 1 0
Bit 2 = N Negative. Level 1 0 1
Level 2 0 0
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic, Level 3 (= interrupt disable) 1 1
logical or data manipulation. It’s a copy of the re- These two bits are set/cleared by hardware when
sult 7th bit. entering in interrupt. The loaded value is given by
0: The result of the last operation is positive or null. the corresponding bits in the interrupt software pri-
1: The result of the last operation is negative ority registers (IxSPR). They can be also set/
(i.e. the most significant bit is a logic 1). cleared by software with the RIM, SIM, IRET,
This bit is accessed by the JRMI and JRPL instruc- HALT, WFI and PUSH/POP instructions.
tions. See the interrupt management chapter for more
details.

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 ST72F521, ST72521B

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
0 0 0 0 0 0 0 1 fore lost. The stack also wraps in case of an under-
flow.
7 0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the
ways pointing to the next free location in the stack. other registers are stored in the next locations as
It is then decremented after data has been pushed shown in Figure 9.
onto the stack and incremented before data is
popped from the stack (see Figure 9). – When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an – On return from interrupt, the SP is incremented
MCU Reset, or after a Reset Stack Pointer instruc- and the context is popped from the stack.
tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in-
ue (the SP7 to SP0 bits are set) which is the stack terrupt five locations in the stack area.
higher address.
Figure 9. Stack Manipulation Example
CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for 6.1 PHASE LOCKED LOOP
securing the application in critical situations (for
example in case of a power brown-out), and re- If the clock frequency input to the PLL is in the
ducing the number of external components. An range 2 to 4 MHz, the PLL can be used to multiply
overview is shown in Figure 11. the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
For more details, refer to dedicated parametric is disabled, then fOSC2 = fOSC/2.
section.
Caution: The PLL is not recommended for appli-
Main features cations where timing accuracy is required. See
■ Optional PLL for multiplying the frequency by 2 “PLL Characteristics” on page 177.
(not to be used with internal RC oscillator)
Figure 10. PLL Block Diagram
■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

PLL x 2 0
– 5 Crystal/Ceramic resonator oscillators fOSC
fOSC2
– 1 Internal RC oscillator
/2 1
■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) PLL OPTION BIT

– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply or
the EVD pin
Figure 11. Clock, Reset and Supply Block Diagram

OSC2 MULTI- fOSC fOSC2 MAIN CLOCK fCPU

CONTROLLER
OSCILLATOR PLL WITH REALTIME
OSC1 (option)
(MO) CLOCK (MCC/RTC)

SYSTEM INTEGRITY MANAGEMENT

RESET SEQUENCE AVD Interrupt Request WATCHDOG
RESET MANAGER SICSR TIMER (WDG)
(RSM) AVD AVD AVD LVD WDG
0 0 0
S IE F RF RF

LOW VOLTAGE
VSS DETECTOR
VDD (LVD)

0 AUXILIARY VOLTAGE
DETECTOR
EVD 1
(AVD)

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by Internal RC Oscillator
three different source types coming from the multi- This oscillator allows a low cost solution for the
oscillator block: main clock of the ST7 using only an internal resis-
■ an external source tor and capacitor. Internal RC oscillator mode has
■ 4 crystal or ceramic resonator oscillators the drawback of a lower frequency accuracy and
■ an internal high frequency RC oscillator
should not be used in applications that require ac-
curate timing.
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable In this mode, the two oscillator pins have to be tied
through the option byte. The associated hardware to ground.
configurations are shown in Table 4. Refer to the Table 4. ST7 Clock Sources
electrical characteristics section for more details.
Hardware Configuration
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected, ST7

External Clock
the ST7 main oscillator may start and, in this con- OSC1 OSC2
figuration, could generate an fOSC clock frequency
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered EXTERNAL
undefined when the OSC pins are left unconnect- SOURCE
ed.
Crystal/Ceramic Resonators

External Clock Source

ST7
In this external clock mode, a clock signal (square, OSC1 OSC2
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of CL1 CL2
the ST7. The selection within a list of 4 oscillators LOAD
CAPACITORS
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 14.1 on page 201 for more details on the
Internal RC Oscillator

frequency ranges). In this mode of the multi-oscil- ST7

lator, the resonator and the load capacitors have OSC1 OSC2
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction The RESET vector fetch phase duration is 2 clock
The reset sequence manager includes three RE- cycles.
SET sources as shown in Figure 13: Figure 12. RESET Sequence Phases
■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET RESET

These sources act on the RESET pin and it is al- INTERNAL RESET FETCH
Active Phase
ways kept low during the delay phase. 256 or 4096 CLOCK CYCLES VECTOR

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of 3 phases
as shown in Figure 12: The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
■ Active Phase depending on the RESET source
This pull-up has no fixed value but varies in ac-
■ 256 or 4096 CPU clock cycle delay (selected by cordance with the input voltage. It can be pulled
option byte) low by external circuitry to reset the device. See
■ RESET vector fetch “CONTROL PIN CHARACTERISTICS” on
page 185 for more details.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery A RESET signal originating from an external
has taken place from the Reset state. The shorter source must have a duration of at least th(RSTL)in in
or longer clock cycle delay should be selected by order to be recognized (see Figure 14). This de-
option byte to correspond to the stabilization time tection is asynchronous and therefore the MCU
of the external oscillator used in the application can enter reset state even in HALT mode.
(see section 14.1 on page 201).
Figure 13. Reset Block Diagram

VDD

RON

Filter INTERNAL
RESET
RESET

PULSE
WATCHDOG RESET
GENERATOR
LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which A proper reset signal for a slow rising VDD supply
plays a major role in EMS performance. In a noisy can generally be provided by an external RC net-
environment, it is recommended to follow the work connected to the RESET pin.
guidelines mentioned in the electrical characteris-
tics section. 6.3.4 Internal Low Voltage Detector (LVD)
RESET
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 14), the Two different RESET sequences caused by the in-
signal on the RESET pin may be stretched. Other- ternal LVD circuitry can be distinguished:
wise the delay will not be applied (see long ext. ■ Power-On RESET
Reset in Figure 14). Starting from the external RE- ■ Voltage Drop RESET
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least The device RESET pin acts as an output that is
tw(RSTL)out. pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 14.
6.3.3 External Power-On RESET
The LVD filters spikes on VDD larger than tg(VDD) to
If the LVD is disabled by option byte, to start up the avoid parasitic resets.
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset 6.3.5 Internal Watchdog RESET
signal is held low until VDD is over the minimum The RESET sequence generated by a internal
level specified for the selected fOSC frequency. Watchdog counter overflow is shown in Figure 14.
(see “OPERATING CONDITIONS” on page 167)
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD

VIT+(LVD)
VIT-(LVD)

LVD SHORT EXT. LONG EXT. WATCHDOG

RESET RESET RESET RESET
RUN RUN ACTIVE
RUN ACTIVE
RUN ACTIVE
RUN
ACTIVE PHASE PHASE PHASE PHASE

tw(RSTL)out tw(RSTL)out

th(RSTL)in th(RSTL)in tw(RSTL)out

DELAY
EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains – under full software control
the Low Voltage Detector (LVD) and Auxiliary Volt- – in static safe reset
age Detector (AVD) functions. It is managed by In these conditions, secure operation is always en-
the SICSR register. sured for the application without the need for ex-
6.4.1 Low Voltage Detector (LVD) ternal reset hardware.
The Low Voltage Detector function (LVD) gener- During a Low Voltage Detector Reset, the RESET
ates a static reset when the VDD supply voltage is pin is held low, thus permitting the MCU to reset
below a VIT- reference value. This means that it other devices.
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order The LVD allows the device to be used without any
to avoid a parasitic reset when the MCU starts run- external RESET circuitry.
ning and sinks current on the supply (hysteresis). If the medium or low thresholds are selected, the
The LVD Reset circuitry generates a reset when detection may occur outside the specified operat-
VDD is below: ing voltage range. Below 3.8V, device operation is
not guaranteed.
– VIT+ when VDD is rising
– VIT- when VDD is falling The LVD is an optional function which can be se-
lected by option byte.
The LVD function is illustrated in Figure 15.
It is recommended to make sure that the VDD sup-
The voltage threshold can be configured by option ply voltage rises monotonously when the device is
byte to be low, medium or high. exiting from Reset, to ensure the application func-
tions properly.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
Figure 15. Low Voltage Detector vs Reset

VDD

Vhys
VIT+
VIT-

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD) In the case of a drop in voltage, the AVD interrupt
The Voltage Detector function (AVD) is based on acts as an early warning, allowing software to shut
an analog comparison between a VIT-(AVD) and down safely before the LVD resets the microcon-
VIT+(AVD) reference value and the VDD main sup- troller. See Figure 16.
ply or the external EVD pin voltage level (VEVD). The interrupt on the rising edge is used to inform
The VIT- reference value for falling voltage is lower the application that the VDD warning state is over.
than the VIT+ reference value for rising voltage in If the voltage rise time trv is less than 256 or 4096
order to avoid parasitic detection (hysteresis). CPU cycles (depending on the reset delay select-
The output of the AVD comparator is directly read- ed by option byte), no AVD interrupt will be gener-
able by the application software through a real ated when VIT+(AVD) is reached.
time status bit (AVDF) in the SICSR register. This If trv is greater than 256 or 4096 cycles then:
bit is read only.
– If the AVD interrupt is enabled before the
Caution: The AVD function is active only if the
LVD is enabled through the option byte. VIT+(AVD) threshold is reached, then 2 AVD inter-
rupts will be received: the first when the AVDIE
6.4.2.1 Monitoring the VDD Main Supply bit is set, and the second when the threshold is
This mode is selected by clearing the AVDS bit in reached.
the SICSR register. – If the AVD interrupt is enabled after the VIT+(AVD)
The AVD voltage threshold value is relative to the threshold is reached then only one AVD interrupt
selected LVD threshold configured by option byte will occur.
(see section 14.1 on page 201).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
Figure 16. Using the AVD to Monitor VDD (AVDS bit=0)

VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)

VIT-(AVD)
VIT+(LVD)

VIT-(LVD) trv VOLTAGE RISE TIME

AVDF bit 0 1 RESET VALUE 1 0

AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS INTERRUPT PROCESS

LVD RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin of the comparator output. This means it is generat-
This mode is selected by setting the AVDS bit in ed when either one of these two events occur:
the SICSR register. – VEVD rises up to VIT+(EVD)
The AVD circuitry can generate an interrupt when – VEVD falls down to VIT-(EVD)
the AVDIE bit of the SICSR register is set. This in- The EVD function is illustrated in Figure 17.
terrupt is generated on the rising and falling edges For more details, refer to the Electrical Character-
istics section.
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

Vhyst
VIT+(EVD)

VIT-(EVD)

AVDF 0 1 0

AVD INTERRUPT
REQUEST
IF AVDIE = 1
INTERRUPT PROCESS INTERRUPT PROCESS

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Low Power Modes set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode Description
Enable Exit Exit
No effect on SI. AVD interrupts cause the Event
WAIT Interrupt Event Control from from
device to exit from Wait mode. Flag
Bit Wait Halt
HALT The CRSR register is frozen.
AVD event AVDF AVDIE Yes No
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write ed by the LVD block. It is set by hardware (LVD re-
Reset Value: 000x 000x (00h) set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
7 0 the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
AVD AVD AVD LVD WDG
0 0 0
S IE F RF RF
Bits 3:1 = Reserved, must be kept cleared.

Bit 7 = AVDS Voltage Detection selection

This bit is set and cleared by software. Voltage De- Bit 0 = WDGRF Watchdog reset flag
tection is available only if the LVD is enabled by This bit indicates that the last Reset was generat-
option byte. ed by the Watchdog peripheral. It is set by hard-
0: Voltage detection on VDD supply ware (watchdog reset) and cleared by software
1: Voltage detection on EVD pin (writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Bit 6 = AVDIE Voltage Detector interrupt enable Combined with the LVDRF flag information, the
This bit is set and cleared by software. It enables flag description is given by the following table.
an interrupt to be generated when the AVDF flag
RESET Sources LVDRF WDGRF
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters External RESET pin 0 0
the AVD interrupt routine. Watchdog 0 1
0: AVD interrupt disabled LVD 1 X
1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag Application notes

This read-only bit is set and cleared by hardware. The LVDRF flag is not cleared when another RE-
If the AVDIE bit is set, an interrupt request is gen- SET type occurs (external or watchdog), the
erated when the AVDF bit changes value. Refer to LVDRF flag remains set to keep trace of the origi-
Figure 16 and to Section 6.4.2.1 for additional de- nal failure.
tails. In this case, a watchdog reset can be detected by
0: VDD or VEVD over VIT+(AVD) threshold software while an external reset can not.
1: VDD or VEVD under VIT-(AVD) threshold
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
Bit 4 = LVDRF LVD reset flag be used in the application.
This bit indicates that the last Reset was generat-

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7 INTERRUPTS

7.1 INTRODUCTION each interrupt vector (see Table 5). The process-
ing flow is shown in Figure 18
The ST7 enhanced interrupt management pro-
vides the following features: When an interrupt request has to be serviced:
■ Hardware interrupts – Normal processing is suspended at the end of
■ Software interrupt (TRAP)
the current instruction execution.
■ Nested or concurrent interrupt management
– The PC, X, A and CC registers are saved onto
with flexible interrupt priority and level the stack.
management: – I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
– Up to 4 software programmable nesting levels of the serviced interrupt vector.
– Up to 16 interrupt vectors fixed by hardware
– The PC is then loaded with the interrupt vector of
– 2 non maskable events: RESET, TRAP the interrupt to service and the first instruction of
– 1 maskable Top Level event: TLI the interrupt service routine is fetched (refer to
This interrupt management is based on: “Interrupt Mapping” table for vector addresses).
– Bit 5 and bit 3 of the CPU CC register (I1:0), The interrupt service routine should end with the
IRET instruction which causes the contents of the
– Interrupt software priority registers (ISPRx), saved registers to be recovered from the stack.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to Note: As a consequence of the IRET instruction,
FFFFh) sorted by hardware priority order. the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level I1 I0
7.2 MASKING AND PROCESSING FLOW Level 0 (main) Low 1 0
The interrupt masking is managed by the I1 and I0 Level 1 0 1
bits of the CC register and the ISPRx registers Level 2 0 0
which give the interrupt software priority level of Level 3 (= interrupt disable) High 1 1

Figure 18. Interrupt Processing Flowchart

PENDING Y Y
RESET TRAP
INTERRUPT

Interrupt has the same or a N

N lower software priority
than current one
I1:0
Interrupt has a higher

FETCH NEXT THE INTERRUPT

than current one
software priority

INSTRUCTION STAYS PENDING

Y
“IRET”

RESTORE PC, X, A, CC EXECUTE

FROM STACK INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont’d)
Servicing Pending Interrupts ■ TRAP (Non Maskable Software Interrupt)
As several interrupts can be pending at the same This software interrupt is serviced when the TRAP
time, the interrupt to be taken into account is deter- instruction is executed. It will be serviced accord-
mined by the following two-step process: ing to the flowchart in Figure 18.
– the highest software priority interrupt is serviced, Caution: TRAP can be interrupted by a TLI.
– if several interrupts have the same software pri- ■ RESET
ority then the interrupt with the highest hardware The RESET source has the highest priority in the
priority is serviced first. ST7. This means that the first current routine has
Figure 19 describes this decision process. the highest software priority (level 3) and the high-
est hardware priority.
Figure 19. Priority Decision Process See the RESET chapter for more details.
PENDING Maskable Sources
INTERRUPTS
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
Same SOFTWARE Different
and I0 in CC register). If any of these two condi-
PRIORITY tions is false, the interrupt is latched and thus re-
mains pending.
■ TLI (Top Level Hardware Interrupt)
HIGHEST SOFTWARE
PRIORITY SERVICED This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. It will be
serviced according to the flowchart in Figure 18 as
HIGHEST HARDWARE
a trap.
PRIORITY SERVICED
Caution: A TRAP instruction must not be used in a
TLI service routine.
When an interrupt request is not serviced immedi- ■ External Interrupts
ately, it is latched and then processed when its External interrupts allow the processor to exit from
software priority combined with the hardware pri- HALT low power mode. External interrupt sensitiv-
ority becomes the highest one. ity is software selectable through the External In-
Note 1: The hardware priority is exclusive while terrupt Control register (EICR).
the software one is not. This allows the previous External interrupt triggered on edge will be latched
process to succeed with only one interrupt. and the interrupt request automatically cleared
Note 2: TLI, RESET and TRAP can be considered upon entering the interrupt service routine.
as having the highest software priority in the deci- If several input pins of a group connected to the
sion process. same interrupt line are selected simultaneously,
these will be logically ORed.
Different Interrupt Vector Sources
■ Peripheral Interrupts
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type Usually the peripheral interrupts cause the MCU to
(RESET, TRAP) and the maskable type (external exit from HALT mode except those mentioned in
or from internal peripherals). the “Interrupt Mapping” table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
Non-Maskable Sources ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
These sources are processed regardless of the
The general sequence for clearing an interrupt is
state of the I1 and I0 bits of the CC register (see
based on an access to the status register followed
Figure 18). After stacking the PC, X, A and CC
by a read or write to an associated register.
registers (except for RESET), the corresponding
Note: The clearing sequence resets the internal
vector is loaded in the PC register and the I1 and
latch. A pending interrupt (i.e. waiting for being
I0 bits of the CC are set to disable interrupts (level
serviced) will therefore be lost if the clear se-
3). These sources allow the processor to exit
quence is executed.
HALT mode.

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES 7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT The following Figure 20 and Figure 21 show two
low power mode. On the contrary, only external different interrupt management modes. The first is
and other specified interrupts allow the processor called concurrent mode and does not allow an in-
to exit from the HALT modes (see column “Exit terrupt to be interrupted, unlike the nested mode in
from HALT” in “Interrupt Mapping” table). When Figure 21. The interrupt hardware priority is given
several pending interrupts are present while exit- in this order from the lowest to the highest: MAIN,
ing HALT mode, the first one serviced can only be IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
an interrupt with exit from HALT mode capability given for each interrupt.
and it is selected through the same decision proc- Warning: A stack overflow may occur without no-
ess shown in Figure 19. tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
TRAP

SOFTWARE
I1 I0
IT2

IT1

IT4

IT3

IT0

PRIORITY
LEVEL
HARDWARE PRIORITY

USED STACK = 10 BYTES

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 3 1 1
IT2 3 1 1
IT3 3 1 1
RIM
IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

Figure 21. Nested Interrupt Management

TRAP

SOFTWARE
I1 I0
IT0
IT2

IT1

IT4

IT3

PRIORITY
LEVEL
USED STACK = 20 BYTES
HARDWARE PRIORITY

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 2 0 0
IT2 IT2 1 0 1
IT3 3 1 1
RIM
IT4 IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

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INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write (bit 7:4 of ISPR3 are read only)
Read/Write
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh) 7 0

7 0
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

1 1 I1 H I0 N Z C
ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

Bit 5, 3 = I1, I0 Software Interrupt Priority

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level I1 I0
Level 0 (main) Low 1 0
These four registers contain the interrupt software
Level 1 0 1 priority of each interrupt vector.
Level 2 0 0
– Each interrupt vector (except RESET and TRAP)
Level 3 (= interrupt disable*) High 1 1 has corresponding bits in these registers where
its own software priority is stored. This corre-
These two bits are set/cleared by hardware when spondance is shown in the following table.
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri- Vector address ISPRx bits
ority registers (ISPRx).
FFFBh-FFFAh I1_0 and I0_0 bits*
They can be also set/cleared by software with the FFF9h-FFF8h I1_1 and I0_1 bits
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
... ...
structions (see “Interrupt Dedicated Instruction
Set” table). FFE1h-FFE0h I1_13 and I0_13 bits

*Note: TLI, TRAP and RESET events can interrupt – Each I1_x and I0_x bit value in the ISPRx regis-
a level 3 program. ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The TLI, RESET, and TRAP vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).

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INTERRUPTS (Cont’d)

Table 6. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 (level 3) I1:0=11 ?
JRNM Jump if I1:0<>11 I1:0<>11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.

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INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
Exit
from
Source Register Priority Address
N° Description HALT/
Block Label Order Vector
ACTIVE
HALT3)
RESET Reset yes FFFEh-FFFFh
N/A
TRAP Software interrupt no FFFCh-FFFDh
0 TLI External top level interrupt EICR yes FFFAh-FFFBh
1 MCC/RTC Main clock controller time base interrupt MCCSR Higher yes FFF8h-FFF9h
2 ei0 External interrupt port A3..0 Priority yes FFF6h-FFF7h
3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h
N/A
4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h
5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h
6 CAN CAN peripheral interrupts CANISR yes FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR yes1 FFECh-FFEDh
8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh
9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h
10 SCI SCI Peripheral interrupts SCISR Lower no FFE6h-FFE7h
11 AVD Auxiliary Voltage detector interrupt SICSR Priority no FFE4h-FFE5h
12 I2C I2C Peripheral interrupts (see periph) no FFE2h-FFE3h
13 PWM ART PWM ART interrupt ARTCSR yes2 FFE0h-FFE1h

Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity ■ Falling edge and low level
The external interrupt sensitivity is controlled by ■ Rising edge and high level (only for ei0 and ei2)
the IPA, IPB and ISxx bits of the EICR register To guarantee correct functionality, the sensitivity
(Figure 22). This control allows to have up to 4 fully bits in the EICR register can be modified only
independent external interrupt source sensitivities. when the I1 and I0 bits of the CC register are both
Each external interrupt source can be generated set to 1 (level 3). This means that interrupts must
on four (or five) different events on the pin: be disabled before changing sensitivity.
■ Falling edge The pending interrupts are cleared by writing a dif-
■ Rising edge ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
■ Falling and rising edge

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INTERRUPTS (Cont’d)
Figure 22. External Interrupt Control bits

PORT A [3:0] INTERRUPTS EICR

IS20 IS21
PAOR.3
PADDR.3
SENSITIVITY PA3
PA3 ei0 INTERRUPT SOURCE
CONTROL PA2
PA1
PA0
IPA BIT

PORT F [2:0] INTERRUPTS EICR

IS20 IS21
PFOR.2
PFDDR.2
SENSITIVITY PF2
PF2 PF1 ei1 INTERRUPT SOURCE
CONTROL
PF0

PORT B [3:0] INTERRUPTS EICR

IS10 IS11
PBOR.3
PBDDR.3
SENSITIVITY PB3
PB3 ei2 INTERRUPT SOURCE
CONTROL PB2
PB1
PB0
IPB BIT

PORT B [7:4] INTERRUPTS EICR

IS10 IS11
PBOR.7
PBDDR.7
SENSITIVITY PB7
PB7 PB6 ei3 INTERRUPT SOURCE
CONTROL
PB5
PB4

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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write - ei0 (port A3..0)
Reset Value: 0000 0000 (00h)
External Interrupt Sensitivity
IS21 IS20
7 0 IPA bit =0 IPA bit =1
Falling edge & Rising edge
IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE 0 0
low level & high level
0 1 Rising edge only Falling edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity 1 0 Falling edge only Rising edge only
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts: 1 1 Rising and falling edge
- ei2 (port B3..0)
External Interrupt Sensitivity - ei1 (port F2..0)
IS11 IS10
IPB bit =0 IPB bit =1 IS21 IS20 External Interrupt Sensitivity
Falling edge & Rising edge 0 0 Falling edge & low level
0 0
low level & high level
0 1 Rising edge only
0 1 Rising edge only Falling edge only
1 0 Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
1 1 Rising and falling edge
These 2 bits can be written only when I1 and I0 of
- ei3 (port B7..4) the CC register are both set to 1 (level 3).
IS11 IS10 External Interrupt Sensitivity
0 0 Falling edge & low level Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
0 1 Rising edge only
[3:0] external interrupts. It can be set and cleared
1 0 Falling edge only by software only when I1 and I0 of the CC register
1 1 Rising and falling edge are both set to 1 (level 3).
0: No sensitivity inversion
These 2 bits can be written only when I1 and I0 of 1: Sensitivity inversion
the CC register are both set to 1 (level 3).
Bit 1 = TLIS TLI sensitivity
Bit 5 = IPB Interrupt polarity for port B This bit allows to toggle the TLI edge sensitivity. It
This bit is used to invert the sensitivity of the port B can be set and cleared by software only when
[3:0] external interrupts. It can be set and cleared TLIE bit is cleared.
by software only when I1 and I0 of the CC register 0: Falling edge
are both set to 1 (level 3). 1: Rising edge
0: No sensitivity inversion
1: Sensitivity inversion
Bit 0 = TLIE TLI enable
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity This bit allows to enable or disable the TLI capabil-
The interrupt sensitivity, defined using the IS2[1:0] ity on the dedicated pin. It is set and cleared by
bits, is applied to the following external interrupts: software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.

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INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
ei1 ei0 MCC TLI
0024h ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1
Reset Value 1 1 1 1 1 1 1 1
SPI CAN ei3 ei2
0025h ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Reset Value 1 1 1 1 1 1 1 1
AVD SCI TIMER B TIMER A
0026h ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Reset Value 1 1 1 1 1 1 1 1
PWMART I2C
0027h ISPR3 I1_13 I0_13 I1_12 I0_12
Reset Value 1 1 1 1 1 1 1 1
EICR IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE
0028h
Reset Value 0 0 0 0 0 0 0 0

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8 POWER SAVING MODES

8.1 INTRODUCTION 8.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, four main – To reduce power consumption by decreasing the
power saving modes are implemented in the ST7 internal clock in the device,
(see Figure 23): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT. – To adapt the internal clock frequency (fCPU) to
the available supply voltage.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives SLOW mode is controlled by three bits in the
the device (CPU and embedded peripherals) by MCCSR register: the SMS bit which enables or
means of a master clock which is based on the disables Slow mode and two CPx bits which select
main oscillator frequency divided or multiplied by 2 the internal slow frequency (fCPU).
(fOSC2). In this mode, the master clock frequency (fOSC2)
From RUN mode, the different power saving can be divided by 2, 4, 8 or 16. The CPU and pe-
modes may be selected by setting the relevant ripherals are clocked at this lower frequency
register bits or by calling the specific ST7 software (fCPU).
instruction whose action depends on the oscillator Note: SLOW-WAIT mode is activated when enter-
status. ing the WAIT mode while the device is already in
SLOW mode.
Figure 23. Power Saving Mode Transitions
Figure 24. SLOW Mode Clock Transitions
High
fOSC2/2 fOSC2/4 fOSC2

RUN fCPU

SLOW fOSC2
MCCSR

CP1:0 00 01
WAIT
SMS

SLOW WAIT
NORMAL RUN MODE
NEW SLOW REQUEST
FREQUENCY
ACTIVE HALT REQUEST

HALT

Low
POWER CONSUMPTION

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POWER SAVING MODES (Cont’d)

8.3 WAIT MODE Figure 25. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I[1:0] BITS 10
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in N
RESET
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the Y
starting address of the interrupt or Reset service N
INTERRUPT
routine.
The MCU will remain in WAIT mode until a Reset Y
or an Interrupt occurs, causing it to wake up. OSCILLATOR ON
Refer to Figure 25. PERIPHERALS OFF
CPU ON
I[1:0] BITS 10

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining tDELAY peri-
ACTIVE-HALT and HALT modes are the two low- od.
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc- Figure 26. ACTIVE-HALT Timing Overview
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt ACTIVE 256 OR 4096 CPU
enable flag (OIE bit in MCCSR register). RUN HALT CYCLE DELAY 1) RUN

MCCSR Power Saving Mode entered when HALT

RESET
OIE bit instruction is executed OR
HALT INTERRUPT
0 HALT mode INSTRUCTION FETCH
[MCCSR.OIE=1] VECTOR
1 ACTIVE-HALT mode

Figure 27. ACTIVE-HALT Mode Flow-chart

8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con- OSCILLATOR ON
sumption mode of the MCU with a real time clock HALT INSTRUCTION PERIPHERALS 2) OFF
available. It is entered by executing the ‘HALT’ in- (MCCSR.OIE=1) CPU OFF
I[1:0] BITS 10
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see section
10.2 on page 58 for more details on the MCCSR N
RESET
register).
N Y
The MCU can exit ACTIVE-HALT mode on recep- INTERRUPT 4)
tion of an MCC/RTC interrupt or a RESET. In ROM OSCILLATOR ON
devices, external interrupts can be used to wake- PERIPHERALS OFF
Y
up the MCU. When exiting ACTIVE-HALT mode CPU ON
by means of an interrupt, no 256 or 4096 CPU cy- I[1:0] BITS XX 3)
cle delay occurs. The CPU resumes operation by
servicing the interrupt or by fetching the reset vec-
256 OR 4096 CPU CLOCK
tor which woke it up (see Figure 27).
CYCLE DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
OSCILLATOR ON
terrupts. Therefore, if an interrupt is pending, the
PERIPHERALS ON
MCU wakes up immediately.
CPU ON
In ACTIVE-HALT mode, only the main oscillator I[1:0] BITS XX 3)
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph- FETCH RESET VECTOR
erals are not clocked except those which get their OR SERVICE INTERRUPT
clock supply from another clock generator (such
as external or auxiliary oscillator). Notes:
The safeguard against staying locked in ACTIVE- 1. This delay occurs only if the MCU exits ACTIVE-
HALT mode is provided by the oscillator interrupt. HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
Note: As soon as the interrupt capability of one of can still be active.
the oscillators is selected (MCCSR.OIE bit set), 3. Before servicing an interrupt, the CC register is
entering ACTIVE-HALT mode while the Watchdog pushed on the stack. The I[1:0] bits of the CC reg-
is active does not generate a RESET. ister are set to the current software priority level of
This means that the device cannot spend more the interrupt routine and restored when the CC
than a defined delay in this power saving mode. register is popped.
CAUTION: When exiting ACTIVE-HALT mode fol- 4. In flash devices only the MCC/RTC interrupt can
lowing an MCC/RTC interrupt, OIE bit of MCCSR exit the MCU from ACTIVE-HALT mode.
register must not be cleared before tDELAY after
the interrupt occurs (tDELAY = 256 or 4096 tCPU de-

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POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE Figure 29. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the HALT INSTRUCTION
‘HALT’ instruction when the OIE bit of the Main (MCCSR.OIE=0)
Clock Controller Status register (MCCSR) is ENABLE
cleared (see section 10.2 on page 58 for more de- WATCHDOG
tails on the MCCSR register).
0 DISABLE
The MCU can exit HALT mode on reception of ei- WDGHALT 1)
ther a specific interrupt (see Table 7, “Interrupt
1
Mapping,” on page 38) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, WATCHDOG
the oscillator is immediately turned on and the 256 OSCILLATOR OFF
RESET PERIPHERALS 2) OFF
or 4096 CPU cycle delay is used to stabilize the
CPU OFF
oscillator. After the start up delay, the CPU
I[1:0] BITS 10
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the N
RESET
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU Y
wakes up immediately. N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in- Y OSCILLATOR ON
cluding the operation of the on-chip peripherals. PERIPHERALS OFF
All peripherals are not clocked except the ones CPU ON
which get their clock supply from another clock I[1:0] BITS XX 4)
generator (such as an external or auxiliary oscilla-
tor). 256 OR 4096 CPU CLOCK
The compatibility of Watchdog operation with CYCLE DELAY
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
OSCILLATOR ON
when executed while the Watchdog system is en- PERIPHERALS ON
abled, can generate a Watchdog RESET (see sec- CPU ON
tion 14.1 on page 201 for more details). I[1:0] BITS XX 4)
Figure 28. HALT Timing Overview
FETCH RESET VECTOR
256 OR 4096 CPU OR SERVICE INTERRUPT
RUN HALT CYCLE DELAY RUN
Notes:
RESET 1. WDGHALT is an option bit. See option byte sec-
OR tion for more details.
HALT INTERRUPT 2. Peripheral clocked with an external clock source
INSTRUCTION FETCH can still be active.
[MCCSR.OIE=0] VECTOR 3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 38 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations ry. For example, avoid defining a constant in
– Make sure that an external event is available to ROM with the value 0x8E.
wake up the microcontroller from Halt mode. – As the HALT instruction clears the interrupt mask
– When using an external interrupt to wake up the in the CC register to allow interrupts, the user
microcontroller, reinitialize the corresponding I/O may choose to clear all pending interrupt bits be-
as “Input Pull-up with Interrupt” before executing fore executing the HALT instruction. This avoids
the HALT instruction. The main reason for this is entering other peripheral interrupt routines after
that the I/O may be wrongly configured due to ex- executing the external interrupt routine corre-
ternal interference or by an unforeseen logical sponding to the wake-up event (reset or external
condition. interrupt).
– For the same reason, reinitialize the level sensi- Related Documentation
tiveness of each external interrupt as a precau- AN 980: ST7 Keypad Decoding Techniques, Im-
tionary measure. plementing Wake-Up on Keystroke
– The opcode for the HALT instruction is 0x8E. To AN1014: How to Minimize the ST7 Power Con-
avoid an unexpected HALT instruction due to a sumption
program counter failure, it is advised to clear all AN1605: Using an active RC to wakeup the
occurrences of the data value 0x8E from memo- ST7LITE0 from power saving mode

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9 I/O PORTS

9.1 INTRODUCTION Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently
The I/O ports offer different functional modes: programmable using the sensitivity bits in the
– transfer of data through digital inputs and outputs EICR register.
and for specific pins: Each external interrupt vector is linked to a dedi-
– external interrupt generation cated group of I/O port pins (see pinout description
– alternate signal input/output for the on-chip pe- and interrupt section). If several input pins are se-
ripherals. lected simultaneously as interrupt sources, these
An I/O port contains up to 8 pins. Each pin can be are first detected according to the sensitivity bits in
programmed independently as digital input (with or the EICR register and then logically ORed.
without interrupt generation) or digital output. The external interrupts are hardware interrupts,
which means that the request latch (not accessible
9.2 FUNCTIONAL DESCRIPTION directly by the application) is automatically cleared
when the corresponding interrupt vector is
Each port has 2 main registers: fetched. To clear an unwanted pending interrupt
– Data Register (DR) by software, the sensitivity bits in the EICR register
– Data Direction Register (DDR) must be modified.
and one optional register: 9.2.2 Output Modes
– Option Register (OR) The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
Each I/O pin may be programmed using the corre- ing the DR register applies this digital value to the
sponding register bits in the DDR and OR regis- I/O pin through the latch. Then reading the DR reg-
ters: bit X corresponding to pin X of the port. The ister returns the previously stored value.
same correspondence is used for the DR register.
Two different output modes can be selected by
The following description takes into account the software through the OR register: Output push-pull
OR register, (for specific ports which do not pro- and open-drain.
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is DR register value and output pin status:
shown in Figure 30 DR Push-pull Open-drain
9.2.1 Input Modes 0 VSS Vss
The input configuration is selected by clearing the 1 VDD Floating
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin. When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
Different input modes can be selected by software ed. This alternate function takes priority over the
through the OR register. standard I/O programming.
Notes: When the signal is coming from an on-chip periph-
1. Writing the DR register modifies the latch value
but does not affect the pin status. eral, the I/O pin is automatically configured in out-
2. When switching from input to output mode, the put mode (push-pull or open drain according to the
DR register has to be written first to drive the cor- peripheral).
rect level on the pin as soon as the port is config- When the signal is going to an on-chip peripheral,
ured as an output. the I/O pin must be configured in input mode. In
3. Do not use read/modify/write instructions (BSET this case, the pin state is also digitally readable by
or BRES) to modify the DR register addressing the DR register.
External interrupt function Note: Input pull-up configuration can cause unex-
When an I/O is configured as Input with Interrupt, pected value at the input of the alternate peripheral
an event on this I/O can generate an external inter- input. When an on-chip peripheral use a pin as in-
rupt request to the CPU. put and output, this pin has to be configured in in-
put floating mode.

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I/O PORTS (Cont’d)

Figure 30. I/O Port General Block Diagram

ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS
(see table below)
0
ALTERNATE PULL-UP
ENABLE (see table below)

DR VDD

DDR

PULL-UP
PAD
CONDITION
OR
DATA BUS

If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)

Table 9. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend: NI - not implemented Note: The diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.

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I/O PORTS (Cont’d)

Table 10. I/O Port Configurations
Hardware Configuration

NOT IMPLEMENTED IN DR REGISTER ACCESS

VDD
TRUE OPEN DRAIN
I/O PORTS
RPU PULL-UP
CONDITION DR W
REGISTER DATA BUS
PAD R
INPUT 1)

ALTERNATE INPUT

EXTERNAL INTERRUPT
SOURCE (eix)

INTERRUPT
CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
OPEN-DRAIN OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
PUSH-PULL OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac- Figure 31. Interrupt I/O Port State Transitions
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts. 01 00 10 11
Analog alternate function INPUT INPUT OUTPUT OUTPUT
When the pin is used as an ADC input, the I/O floating/pull-up floating open-drain push-pull
must be configured as floating input. The analog interrupt (reset state)
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select- XX = DDR, OR

ed pin to the common analog rail which is connect-

ed to the ADC input.
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in Mode Description
progress. Furthermore it is recommended not to No effect on I/O ports. External interrupts
have clocking pins located close to a selected an- WAIT
cause the device to exit from WAIT mode.
alog pin.
No effect on I/O ports. External interrupts
WARNING: The analog input voltage level must HALT
cause the device to exit from HALT mode.
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION The external interrupt event generates an interrupt
if the corresponding configuration is selected with
The hardware implementation on each I/O port de- DDR and OR registers and the interrupt mask in
pends on the settings in the DDR and OR registers the CC register is not active (RIM instruction).
and specific feature of the I/O port such as ADC In-
put or true open drain. Enable Exit Exit
Event
Switching these I/O ports from one state to anoth- Interrupt Event Control from from
Flag
er should be done in a sequence that prevents un- Bit Wait Halt
wanted side effects. Recommended safe transi- External interrupt on
tions are illustrated in Figure 31 Other transitions DDRx
selected external - Yes Yes
are potentially risky and should be avoided, since ORx
event
they are likely to present unwanted side-effects
such as spurious interrupt generation.

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I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation
The I/O port register configurations are summa- PA3, PB7, PB3, PF2 (without pull-up)
rised as follows.
MODE DDR OR
Standard Ports floating input 0 0
PA5:4, PC7:0, PD7:0, PE7:34, floating interrupt input 0 1
PE1:0, PF7:3, PG7:0, PH7:0 open drain output 1 0
push-pull output 1 1
MODE DDR OR
floating input 0 0
pull-up input 0 1 True Open Drain Ports
open drain output 1 0 PA7:6
push-pull output 1 1
MODE DDR
Interrupt Ports floating input 0
PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up) open drain (high sink ports) 1

MODE DDR OR Pull-up Input Port (CANTX requirement)

floating input 0 0 PE2
pull-up interrupt input 0 1
open drain output 1 0 MODE
push-pull output 1 1 pull-up input

Table 11. Port Configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
PA7:6 floating true open-drain
PA5:4 floating pull-up open drain push-pull
Port A
PA3 floating floating interrupt open drain push-pull
PA2:0 floating pull-up interrupt open drain push-pull
PB7, PB3 floating floating interrupt open drain push-pull
Port B PB6:5, PB4,
floating pull-up interrupt open drain push-pull
PB2:0
Port C PC7:0 floating pull-up open drain push-pull
Port D PD7:0 floating pull-up open drain push-pull
PE7:3, PE1:0 floating pull-up open drain push-pull
Port E
PE2 pull-up input only *
PF7:3 floating pull-up open drain push-pull
Port F PF2 floating floating interrupt open drain push-pull
PF1:0 floating pull-up interrupt open drain push-pull
Port G PG7:0 floating pull-up open drain push-pull
Port H PH7:0 floating pull-up open drain push-pull
* Note: when the CANTX alternate function is selected the I/O port operates in output push-pull mode.

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I/O PORTS (Cont’d)

Table 12. I/O Port Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Reset Value
0 0 0 0 0 0 0 0
of all I/O port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR
0003h PBDR
0004h PBDDR MSB LSB
0005h PBOR
0006h PCDR
0007h PCDDR MSB LSB
0008h PCOR
0009h PDDR
000Ah PDDDR MSB LSB
000Bh PDOR
000Ch PEDR
000Dh PEDDR MSB LSB
000Eh PEOR
000Fh PFDR
0010h PFDDR MSB LSB
0011h PFOR
0012h PGDR
0013h PGDDR MSB LSB
0014h PGOR
0015h PHDR
0016h PHDDR MSB LSB
0017h PHOR

Related Documentation AN1045: S/W implementation of I2C bus master

AN 970: SPI Communication between ST7 and AN1048: Software LCD driver
EEPROM

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 ST72F521, ST72521B

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction If the watchdog is activated (the WDGA bit is set)
The Watchdog timer is used to detect the occur- and when the 7-bit timer (bits T[6:0]) rolls over
rence of a software fault, usually generated by ex- from 40h to 3Fh (T6 becomes cleared), it initiates
ternal interference or by unforeseen logical condi- a reset cycle pulling low the reset pin for typically
tions, which causes the application program to 500ns.
abandon its normal sequence. The Watchdog cir- The application program must write in the
cuit generates an MCU reset on expiry of a pro- WDGCR register at regular intervals during normal
grammed time period, unless the program refresh- operation to prevent an MCU reset. This down-
es the counter’s contents before the T6 bit be- counter is free-running: it counts down even if the
comes cleared. watchdog is disabled. The value to be stored in the
10.1.2 Main Features WDGCR register must be between FFh and C0h:
■ Programmable free-running downcounter – The WDGA bit is set (watchdog enabled)
■ Programmable reset – The T6 bit is set to prevent generating an imme-
■ Reset (if watchdog activated) when the T6 bit
diate reset
reaches zero – The T[5:0] bits contain the number of increments
■ Optional reset on HALT instruction which represents the time delay before the
(configurable by option byte) watchdog produces a reset (see Figure 33. Ap-
proximate Timeout Duration). The timing varies
■ Hardware Watchdog selectable by option byte
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
10.1.3 Functional Description ing to the WDGCR register (see Figure 34).
The counter value stored in the Watchdog Control Following a reset, the watchdog is disabled. Once
register (WDGCR bits T[6:0]), is decremented activated it cannot be disabled, except by a reset.
every 16384 fOSC2 cycles (approx.), and the The T6 bit can be used to generate a software re-
length of the timeout period can be programmed set (the WDGA bit is set and the T6 bit is cleared).
by the user in 64 increments. If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 32. Watchdog Block Diagram

RESET
fOSC2

MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)

DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0

6-BIT DOWNCOUNTER (CNT)

12-BIT MCC
RTC COUNTER WDG PRESCALER
TB[1:0] bits DIV 4
MSB LSB
(MCCSR
11 6 5 0
Register)

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WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout more precision is needed, use the formulae in Fig-
Figure 33 shows the linear relationship between ure 34.
the 6-bit value to be loaded in the Watchdog Coun- Caution: When writing to the WDGCR register, al-
ter (CNT) and the resulting timeout duration in mil- ways write 1 in the T6 bit to avoid generating an
liseconds. This can be used for a quick calculation immediate reset.
without taking the timing variations into account. If
Figure 33. Approximate Timeout Duration

3F

38

30

28
CNT Value (hex.)

20

18

10

08

00
1.5 18 34 50 65 82 98 114 128
Watchdog timeout (ms) @ 8 MHz. fOSC2

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WATCHDOG TIMER (Cont’d)

Figure 34. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit TB0 Bit Selected MCCSR
MSB LSB
(MCCSR Reg.) (MCCSR Reg.) Timebase
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54

To calculate the minimum Watchdog Timeout (tmin):

IF CNT < MSB

------------- THEN t min = t min0 + 16384 × CNT × tosc2
4

ELSE t min = t min0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB

To calculate the maximum Watchdog Timeout (tmax):

IF CNT ≤ MSB
------------- THEN t max = t max0 + 16384 × CNT × t osc2
4

ELSE t max = t max0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB

Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog Max. Watchdog
Value of T[5:0] Bits in
Timeout (ms) Timeout (ms)
WDGCR Register (Hex.)
tmin tmax
00 1.496 2.048
3F 128 128.552

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WATCHDOG TIMER (Cont’d)

10.1.5 Low Power Modes
Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in WDGHALT bit
MCCSR in Option
register Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0 0
If an external interrupt is received, the Watchdog restarts counting after 256
HALT or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.7 below.
0 1 A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
1 x oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.

10.1.6 Hardware Watchdog Option 10.1.9 Register Description

If Hardware Watchdog is selected by option byte, CONTROL REGISTER (WDGCR)
the watchdog is always active and the WDGA bit in Read/Write
the WDGCR is not used. Refer to the Option Byte
description. Reset Value: 0111 1111 (7Fh)
10.1.7 Using Halt Mode with the WDG 7 0
(WDGHALT option)
WDGA T6 T5 T4 T3 T2 T1 T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh Bit 7 = WDGA Activation bit.
the WDG counter, to avoid an unexpected WDG This bit is set by software and only cleared by
reset immediately after waking up the microcon- hardware after a reset. When WDGA = 1, the
troller. watchdog can generate a reset.
10.1.8 Interrupts 0: Watchdog disabled
1: Watchdog enabled
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cy-
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).

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Table 13. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Ah
Reset Value 0 1 1 1 1 1 1 1

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ST72F521, ST72521B

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ- external devices. It is controlled by the MCO bit in
ent functions: the MCCSR register.
■ a programmable CPU clock prescaler CAUTION: When selected, the clock out pin sus-
■ a clock-out signal to supply external devices
pends the clock during ACTIVE-HALT mode.
■ a real time clock timer with interrupt capability
10.2.3 Real Time Clock Timer (RTC)
Each function can be used independently and si- The counter of the real time clock timer allows an
multaneously. interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
10.2.1 Programmable CPU Clock Prescaler ing directly on fOSC2 are available. The whole
The programmable CPU clock prescaler supplies functionality is controlled by four bits of the MCC-
the clock for the ST7 CPU and its internal periph- SR register: TB[1:0], OIE and OIF.
erals. It manages SLOW power saving mode (See When the RTC interrupt is enabled (OIE bit set),
Section 8.2 SLOW MODE for more details). the ST7 enters ACTIVE-HALT mode when the
The prescaler selects the fCPU main clock frequen- HALT instruction is executed. See Section 8.4 AC-
cy and is controlled by three bits in the MCCSR TIVE-HALT AND HALT MODES for more details.
register: CP[1:0] and SMS. 10.2.4 Beeper
10.2.2 Clock-out Capability The beep function is controlled by the MCCBCR
The clock-out capability is an alternate function of register. It can output three selectable frequencies
an I/O port pin that outputs a fCPU clock to drive on the BEEP pin (I/O port alternate function).

Figure 35. Main Clock Controller (MCC/RTC) Block Diagram

BC1 BC0

MCCBCR
BEEP
BEEP SIGNAL
SELECTION
MCO

12-BIT MCC RTC TO

DIV 64
COUNTER WATCHDOG
TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR MCC/RTC INTERRUPT

fOSC2
DIV 2, 4, 8, 16 1
fCPU CPU CLOCK
TO CPU AND
0 PERIPHERALS

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5 Low Power Modes
Mode Description
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is
WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These
from WAIT mode. two bits are set and cleared by software
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen. fCPU in SLOW mode CP1 CP0
HALT MCC/RTC interrupt cause the device to exit fOSC2 / 2 0 0
from ACTIVE-HALT mode.
fOSC2 / 4 0 1
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the fOSC2 / 8 1 0
HALT
MCU is woken up by an interrupt with “exit fOSC2 / 16 1 1
from HALT” capability.

10.2.6 Interrupts Bit 4 = SMS Slow mode select

The MCC/RTC interrupt event generates an inter- This bit is set and cleared by software.
rupt if the OIE bit of the MCCSR register is set and 0: Normal mode. fCPU = fOSC2
the interrupt mask in the CC register is not active 1: Slow mode. fCPU is given by CP1, CP0
(RIM instruction). See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
Enable Exit Exit CLOCK AND BEEPER (MCC/RTC) for more de-
Event tails.
Interrupt Event Control from from
Flag
Bit Wait Halt
Time base overflow Bit 3:2 = TB[1:0] Time base control
OIF OIE Yes No 1)
event
These bits select the programmable divider time
Note: base. They are set and cleared by software.
The MCC/RTC interrupt wakes up the MCU from Time Base
Counter
ACTIVE-HALT mode, not from HALT mode. TB1 TB0
Prescaler f
OSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

10.2.7 Register Description 32000 8ms 4ms 0 1

MCC CONTROL/STATUS REGISTER (MCCSR) 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1
Read/Write
Reset Value: 0000 0000 (00h) A modification of the time base is taken into ac-
count at the end of the current period (previously
7 0 set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
Bit 7 = MCO Main clock out selection This bit set and cleared by software.
This bit enables the MCO alternate function on the 0: Oscillator interrupt disabled
PF0 I/O port. It is set and cleared by software. 1: Oscillator interrupt enabled
0: MCO alternate function disabled (I/O pin free for This interrupt can be used to exit from ACTIVE-
general-purpose I/O) HALT mode.
1: MCO alternate function enabled (fCPU on I/O When this bit is set, calling the ST7 software HALT
port) instruction enters the ACTIVE-HALT power saving
Note: To reduce power consumption, the MCO mode.
function is not active in ACTIVE-HALT mode.

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag MCC BEEP CONTROL REGISTER (MCCBCR)
This bit is set by hardware and cleared by software Read/Write
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected Reset Value: 0000 0000 (00h)
elapsed time (TB1:0).
0: Timeout not reached 7 0
1: Timeout reached
0 0 0 0 0 0 BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit. Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with fOSC2=8MHz

0 0 Off
0 1 ~2-KHz
Output
1 0 ~1-KHz Beep signal
~50% duty cycle
1 1 ~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SICSR AVDS AVDIE AVDF LVDRF WDGRF
002Bh
Reset Value 0 0 0 x 0 0 0 x
MCCSR MCO CP1 CP0 SMS TB1 TB0 OIE OIF
002Ch
Reset Value 0 0 0 0 0 0 0 0
MCCBCR BC1 BC0
002Dh
Reset Value 0 0 0 0 0 0 0 0

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 ST72F521, ST72521B

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer – Up to two input capture functions
on-chip peripheral consists of an 8-bit auto reload – External event detector
counter with compare/capture capabilities and of a
7-bit prescaler clock source. – Up to two external interrupt sources
These resources allow five possible operating The three first modes can be used together with a
modes: single counter frequency.
– Generation of up to 4 independent PWM signals The timer can be used to wake up the MCU from
WAIT and HALT modes.
– Output compare and Time base interrupt
Figure 36. PWM Auto-Reload Timer Block Diagram

PWMCR OEx OPx OCRx DCRx

REGISTER REGISTER

LOAD
PORT
POLARITY
PWMx ALTERNATE COMPARE
FUNCTION CONTROL

ARR 8-BIT COUNTER LOAD

REGISTER (CAR REGISTER)

INPUT CAPTURE LOAD ICRx

ARTICx
CONTROL REGISTER

ICSx ICIEx ICFx ICCSR

ICx INTERRUPT
fEXT
ARTCLK
fCOUNTER
fCPU

MUX

fINPUT PROGRAMMABLE
PRESCALER

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR

OVF INTERRUPT

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PWM AUTO-RELOAD TIMER (Cont’d)

10.3.2 Functional Description
Counter Counter and Prescaler Initialization
The free running 8-bit counter is fed by the output After RESET, the counter and the prescaler are
of the prescaler, and is incremented on every ris- cleared and fINPUT = fCPU.
ing edge of the clock signal. The counter can be initialized by:
It is possible to read or write the contents of the – Writing to the ARTARR register and then setting
counter on the fly by reading or writing the Counter the FCRL (Force Counter Re-Load) and the TCE
Access register (ARTCAR). (Timer Counter Enable) bits in the ARTCSR reg-
When a counter overflow occurs, the counter is ister.
automatically reloaded with the contents of the – Writing to the ARTCAR counter access register,
ARTARR register (the prescaler is not affected).
In both cases the 7-bit prescaler is also cleared,
Counter clock and prescaler whereupon counting will start from a known value.
The counter clock frequency is given by: Direct access to the prescaler is not possible.
fCOUNTER = fINPUT / 2CC[2:0] Output compare control
The timer counter’s input clock (fINPUT) feeds the The timer compare function is based on four differ-
7-bit programmable prescaler, which selects one ent comparisons with the counter (one for each
of the 8 available taps of the prescaler, as defined PWMx output). Each comparison is made be-
by CC[2:0] bits in the Control/Status Register tween the counter value and an output compare
(ARTCSR). Thus the division factor of the prescal- register (OCRx) value. This OCRx register can not
er can be set to 2n (where n = 0, 1,..7). be accessed directly, it is loaded from the duty cy-
This fINPUT frequency source is selected through cle register (PWMDCRx) at each overflow of the
the EXCL bit of the ARTCSR register and can be counter.
either the fCPU or an external input frequency fEXT. This double buffering method avoids glitch gener-
The clock input to the counter is enabled by the ation when changing the duty cycle on the fly.
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 37. Output compare control

fCOUNTER

ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh FFh

OCRx FDh FEh

PWMDCRx FDh FEh

PWMx

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PWM AUTO-RELOAD TIMER (Cont’d)

Independent PWM signal generation When the counter reaches the value contained in
This mode allows up to four Pulse Width Modulat- one of the output compare register (OCRx) the
ed signals to be generated on the PWMx output corresponding PWMx pin level is restored.
pins with minimum core processing overhead. It should be noted that the reload values will also
This function is stopped during HALT mode. affect the value and the resolution of the duty cycle
Each PWMx output signal can be selected inde- of the PWM output signal. To obtain a signal on a
pendently using the corresponding OEx bit in the PWMx pin, the contents of the OCRx register must
PWM Control register (PWMCR). When this bit is be greater than the contents of the ARTARR reg-
set, the corresponding I/O pin is configured as out- ister.
put push-pull alternate function. The maximum available resolution for the PWMx
The PWM signals all have the same frequency duty cycle is:
which is controlled by the counter period and the Resolution = 1 / (256 - ARTARR)
ARTARR register value. Note: To get the maximum resolution (1/256), the
fPWM = fCOUNTER / (256 - ARTARR) ARTARR register must be 0. With this maximum
When a counter overflow occurs, the PWMx pin resolution, 0% and 100% can be obtained by
level is changed depending on the corresponding changing the polarity.
OPx (output polarity) bit in the PWMCR register.
Figure 38. PWM Auto-reload Timer Function

255
DUTY CYCLE
REGISTER
COUNTER

(PWMDCRx)

AUTO-RELOAD
REGISTER
(ARTARR)
000
t
PWMx OUTPUT

WITH OEx=1
AND OPx=0

WITH OEx=1
AND OPx=1

Figure 39. PWM Signal from 0% to 100% Duty Cycle

fCOUNTER

ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh
PWMx OUTPUT
WITH OEx=1
AND OPx=0

OCRx=FDh

OCRx=FEh

OCRx=FFh

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PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt External clock and event detector mode
On overflow, the OVF flag of the ARTCSR register Using the fEXT external prescaler input clock, the
is set and an overflow interrupt request is generat- auto-reload timer can be used as an external clock
ed if the overflow interrupt enable bit, OIE, in the event detector. In this mode, the ARTARR register
ARTCSR register, is set. The OVF flag must be re- is used to select the nEVENT number of events to
set by the user software. This interrupt can be be counted before setting the OVF flag.
used as a time base in the application. nEVENT = 256 - ARTARR
Caution: The external clock function is not availa-
ble in HALT mode. If HALT mode is used in the ap-
plication, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious coun-
ter increments.
Figure 40. External Event Detector Example (3 counts)

fEXT=fCOUNTER

ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh

OVF

ARTCSR READ ARTCSR READ

INTERRUPT INTERRUPT
IF OIE=1 IF OIE=1

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PWM AUTO-RELOAD TIMER (Cont’d)

Input capture function
This mode allows the measurement of external External interrupt capability
signal pulse widths through ARTICRx registers. This mode allows the Input capture capabilities to
Each input capture can generate an interrupt inde- be used as external interrupt sources. The inter-
pendently on a selected input signal transition. rupts are generated on the edge of the ARTICx
This event is flagged by a set of the corresponding signal.
CFx bits of the Input Capture Control/Status regis- The edge sensitivity of the external interrupts is
ter (ARTICCSR). programmable (CSx bit of ARTICCSR register)
These input capture interrupts are enabled and they are independently enabled through CIEx
through the CIEx bits of the ARTICCSR register. bits of the ARTICCSR register. After fetching the
The active transition (falling or rising edge) is soft- interrupt vector, the CFx flags can be read to iden-
ware programmable through the CSx bits of the tify the interrupt source.
ARTICCSR register. During HALT mode, the external interrupts can be
The read only input capture registers (ARTICRx) used to wake up the micro (if the CIEx bit is set).
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/fCOUNTER).

Note: During HALT mode, if both input capture

and external clock are enabled, the ARTICRx reg-
ister value is not guaranteed if the input capture
pin and the external clock change simultaneously.
Figure 41. Input Capture Timing Diagram

fCOUNTER

COUNTER
01h 02h 03h 04h 05h 06h 07h

ARTICx PIN INTERRUPT

CFx FLAG

xxh 04h
ICRx REGISTER
t

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PWM AUTO-RELOAD TIMER (Cont’d)

10.3.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR) 0: New transition not yet reached
Read/Write 1: Transition reached
Reset Value: 0000 0000 (00h) COUNTER ACCESS REGISTER (ARTCAR)
7 0
Read/Write
Reset Value: 0000 0000 (00h)
EXCL CC2 CC1 CC0 TCE FCRL OIE OVF
7 0

Bit 7 = EXCL External Clock CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock. Bit 7:0 = CA[7:0] Counter Access Data
1: External clock. These bits can be set and cleared either by hard-
Bit 6:4 = CC[2:0] Counter Clock Control ware or by software. The ARTCAR register is used
These bits are set and cleared by software. They to read or write the auto-reload counter “on the fly”
determine the prescaler division ratio from fINPUT. (while it is counting).

fCOUNTER With fINPUT=8 MHz CC2 CC1 CC0

fINPUT 8 MHz 0 0 0
fINPUT / 2 4 MHz 0 0 1 AUTO-RELOAD REGISTER (ARTARR)
fINPUT / 4 2 MHz 0 1 0 Read/Write
fINPUT / 8 1 MHz 0 1 1
fINPUT / 16 500 KHz 1 0 0 Reset Value: 0000 0000 (00h)
fINPUT / 32 250 KHz 1 0 1
7 0
fINPUT / 64 125 KHz 1 1 0
fINPUT / 128 62.5 KHz 1 1 1 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the Bit 7:0 = AR[7:0] Counter Auto-Reload Data
timer in the lowest power consumption mode. These bits are set and cleared by software. They
0: Counter stopped (prescaler and counter frozen). are used to hold the auto-reload value which is au-
1: Counter running. tomatically loaded in the counter when an overflow
Bit 2 = FCRL Force Counter Re-Load occurs. At the same time, the PWM output levels
This bit is write-only and any attempt to read it will are changed according to the corresponding OPx
yield a logical zero. When set, it causes the contents bit in the PWMCR register.
of ARTARR register to be loaded into the counter, This register has two PWM management func-
and the content of the prescaler register to be tions:
cleared in order to initialize the timer before starting
– Adjusting the PWM frequency
to count.
– Setting the PWM duty cycle resolution
Bit 1 = OIE Overflow Interrupt Enable
This bit is set and cleared by software. It allows to PWM Frequency vs. Resolution:
enable/disable the interrupt which is generated
when the OVF bit is set. ARTARR fPWM
0: Overflow Interrupt disable. Resolution
value Min Max
1: Overflow Interrupt enable.
Bit 0 = OVF Overflow Flag 0 8-bit ~0.244-KHz 31.25-KHz
This bit is set by hardware and cleared by software [ 0..127 ] > 7-bit ~0.244-KHz 62.5-KHz
reading the ARTCSR register. It indicates the tran- [ 128..191 ] > 6-bit ~0.488-KHz 125-KHz
sition of the counter from FFh to the ARTARR val- [ 192..223 ] > 5-bit ~0.977-KHz 250-KHz
ue.
[ 224..239 ] > 4-bit ~1.953-KHz 500-KHz

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 ST72F521, ST72521B

PWM AUTO-RELOAD TIMER (Cont’d)

PWM CONTROL REGISTER (PWMCR) DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 7:4 = OE[3:0] PWM Output Enable Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software. They These bits are set and cleared by software.
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin. A PWMDCRx register is associated with the OCRx
0: PWM output disabled. register of each PWM channel to determine the
1: PWM output enabled. second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
Bit 3:0 = OP[3:0] PWM Output Polarity ters allow the duty cycle to be set independently
These bits are set and cleared by software. They for each PWM channel.
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx Counter > OCRx
1 0 0
0 1 1

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

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ST72F521, ST72521B

PWM AUTO-RELOAD TIMER (Cont’d)

INPUT CAPTURE INPUT CAPTURE REGISTERS (ARTICRx)
CONTROL / STATUS REGISTER (ARTICCSR) Read only
Read/Write Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7 0
7 0
IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0
0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

Bit 7:0 = IC[7:0] Input Capture Data

Bit 7:6 = Reserved, always read as 0. These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
Bit 5:4 = CS[2:1] Capture Sensitivity auto-reload counter value transferred by the input
These bits are set and cleared by software. They capture channel x event.
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occured on channel x.

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 ST72F521, ST72521B

PWM AUTO-RELOAD TIMER (Cont’d)

Table 15. PWM Auto-Reload Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

PWMDCR3 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0073h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR2 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0074h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR1 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0075h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0076h
Reset Value 0 0 0 0 0 0 0 0

PWMCR OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

0077h
Reset Value 0 0 0 0 0 0 0 0

ARTCSR EXCL CC2 CC1 CC0 TCE FCRL RIE OVF

0078h
Reset Value 0 0 0 0 0 0 0 0

ARTCAR CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

0079h
Reset Value 0 0 0 0 0 0 0 0

ARTARR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

007Ah
Reset Value 0 0 0 0 0 0 0 0

ARTICCSR CS2 CS1 CIE2 CIE1 CF2 CF1

007Bh
Reset Value 0 0 0 0 0 0 0 0

ARTICR1 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

007Ch
Reset Value 0 0 0 0 0 0 0 0

ARTICR2 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

007Dh
Reset Value 0 0 0 0 0 0 0 0

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ST72F521, ST72521B

10.4 16-BIT TIMER

10.4.1 Introduction When reading an input signal on a non-bonded
The timer consists of a 16-bit free-running counter pin, the value will always be ‘1’.
driven by a programmable prescaler. 10.4.3 Functional Description
It may be used for a variety of purposes, including 10.4.3.1 Counter
pulse length measurement of up to two input sig- The main block of the Programmable Timer is a
nals (input capture) or generation of up to two out- 16-bit free running upcounter and its associated
put waveforms (output compare and PWM). 16-bit registers. The 16-bit registers are made up
Pulse lengths and waveform periods can be mod- of two 8-bit registers called high & low.
ulated from a few microseconds to several milli- Counter Register (CR):
seconds using the timer prescaler and the CPU
clock prescaler. – Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not – Counter Low Register (CLR) is the least sig-
share any resources. They are synchronized after nificant byte (LS Byte).
a MCU reset as long as the timer clock frequen- Alternate Counter Register (ACR)
cies are not modified. – Alternate Counter High Register (ACHR) is the
This description covers one or two 16-bit timers. In most significant byte (MS Byte).
ST7 devices with two timers, register names are – Alternate Counter Low Register (ACLR) is the
prefixed with TA (Timer A) or TB (Timer B). least significant byte (LS Byte).
10.4.2 Main Features These two read-only 16-bit registers contain the
■ Programmable prescaler: fCPU divided by 2, 4 or 8. same value but with the difference that reading the
■ Overflow status flag and maskable interrupt
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
■ External clock input (must be at least 4 times
(see note at the end of paragraph titled 16-bit read
slower than the CPU clock speed) with the choice sequence).
of active edge
Writing in the CLR register or ACLR register resets
■ 1 or 2 Output Compare functions each with:
the free running counter to the FFFCh value.
– 2 dedicated 16-bit registers Both counters have a reset value of FFFCh (this is
– 2 dedicated programmable signals the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
– 2 dedicated status flags FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
The timer clock depends on the clock control bits
– 2 dedicated 16-bit registers of the CR2 register, as illustrated in Table 16 Clock
– 2 dedicated active edge selection signals Control Bits. The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
– 2 dedicated status flags cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt The timer frequency can be fCPU/2, fCPU/4, fCPU/8
■ Pulse width modulation mode (PWM) or an external frequency.
■ One pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 42.

*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Figure 42. Timer Block Diagram

ST7 INTERNAL BUS

fCPU
MCU-PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer
high

high

high

high
low

low

low

low
EXEDG
16

1/2 OUTPUT OUTPUT INPUT INPUT

COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16

OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2 pin

LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register) LATCH2 OCMP2
CSR pin

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 1) CR1 (Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)

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ST72F521, ST72521B

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS Byte Notes: The TOF bit is not cleared by accesses to
At t0 MS Byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +∆t LS Byte LS Byte value at t0 The timer is not affected by WAIT mode.
Sequence completed In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS previous count (MCU awakened by an interrupt) or
Byte value is buffered automatically. from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the 10.4.3.2 External Clock
user reads the MS Byte several times.
The external clock (where available) is selected if
After a complete reading sequence, if only the CC0=1 and CC1=1 in the CR2 register.
CLR register or ACLR register are read, they re-
The status of the EXEDG bit in the CR2 register
turn the LS Byte of the count value at the time of
determines the type of level transition on the exter-
the read.
nal clock pin EXTCLK that will trigger the free run-
Whatever the timer mode used (input capture, out- ning counter.
put compare, one pulse mode or PWM mode) an
The counter is synchronized with the falling edge
overflow occurs when the counter rolls over from
of the internal CPU clock.
FFFFh to 0000h then:
A minimum of four falling edges of the CPU clock
– The TOF bit of the SR register is set.
must occur between two consecutive active edges
– A timer interrupt is generated if: of the external clock; thus the external clock fre-
– TOIE bit of the CR1 register is set and quency must be less than a quarter of the CPU
clock frequency.
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Figure 43. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 44. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

TIMER OVERFLOW FLAG (TOF)

Figure 45. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

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ST72F521, ST72521B

16-BIT TIMER (Cont’d)

10.4.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – ICFi bit is set.
there are 2 input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two 16-bit input capture registers (IC1R and ICAPi pin (see Figure 47).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition is detected on the and the I bit is cleared in the CC register. Other-
ICAPi pin (see figure 5). wise, the interrupt remains pending until both
MS Byte LS Byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function select the follow- read.
ing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 16 counter value which corresponds to the most
Clock Control Bits). recent input capture.
– Select the edge of the active transition on the 3. The 2 input capture functions can be used
ICAP2 pin with the IEDG2 bit (the ICAP2 pin together even if the timer also uses the 2 output
must be configured as floating input or input with compare functions.
pull-up without interrupt if this configuration is 4. In One pulse Mode and PWM mode only Input
available). Capture 2 can be used.
And select the following in the CR1 register: 5. The alternate inputs (ICAP1 & ICAP2) are
– Set the ICIE bit to generate an interrupt after an always directly connected to the timer. So any
input capture coming from either the ICAP1 pin transitions on these pins activates the input
or the ICAP2 pin capture function.
– Select the edge of the active transition on the Moreover if one of the ICAPi pins is configured
ICAP1 pin with the IEDG1 bit (the ICAP1pin must as an input and the second one as an output,
be configured as floating input or input with pull- an interrupt can be generated if the user tog-
up without interrupt if this configuration is availa- gles the output pin and if the ICIE bit is set.
ble). This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Figure 46. Input Capture Block Diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

(Control Register 2) CR2

16-BIT
16-BIT FREE RUNNING CC1 CC0 IEDG2
COUNTER

Figure 47. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: The rising edge is the active edge.

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ST72F521, ST72521B

16-BIT TIMER (Cont’d)

10.4.3.4 Output Compare – The OCMPi pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are 2 output compare functions in the 16-bit – A timer interrupt is generated if the OCIE bit is
timer. set in the CR1 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the ∆t * fCPU
OCiE bit is set ∆ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
∆t = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 16
MS Byte LS Byte
Clock Control Bits)
OCiR OCiHR OCiLR
If the timer clock is an external clock, the formula
These registers are readable and writable and are is:
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h. ∆ OCiR = ∆t * fEXT
Timing resolution is one count of the free running Where:
counter: (fCPU/CC[1:0]).
∆t = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register: Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i 1. Reading the SR register while the OCFi bit is
signal. set.
– Select the timer clock (CC[1:0]) (see Table 16 2. An access (read or write) to the OCiLR register.
Clock Control Bits). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Notes:
1. After a processor write cycle to the OCiHR reg- Forced Compare Output capability
ister, the output compare function is inhibited When the FOLVi bit is set by software, the OLVLi
until the OCiLR register is also written. bit is copied to the OCMPi pin. The OLVi bit has to
2. If the OCiE bit is not set, the OCMPi pin is a be toggled in order to toggle the OCMPi pin when
general I/O port and the OLVLi bit will not it is enabled (OCiE bit=1). The OCFi bit is then not
appear when a match is found but an interrupt set by hardware, and thus no interrupt request is
could be generated if the OCIE bit is set. generated.
3. When the timer clock is fCPU/2, OCFi and The FOLVLi bits have no effect in both one pulse
OCMPi are set while the counter value equals mode and PWM mode.
the OCiR register value (see Figure 49 on page
78). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 50 on page 78).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 48. Output Compare Block Diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2 OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

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ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Figure 49. Output Compare Timing Diagram, fTIMER =fCPU/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode Clearing the Input Capture interrupt request (i.e.
One Pulse mode enables the generation of a clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use one pulse mode: t * fCPU -5
OCiR Value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
– Using the OLVL2 bit, select the level to be ap- Clock Control Bits)
plied to the OCMP1 pin during the pulse. If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin OCiR = t * fEXT -5
must be configured as floating input).
Where:
3. Select the following in the CR2 register:
t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function. fEXT = External timer clock frequency (in hertz)
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 16 When the value of the counter is equal to the value
Clock Control Bits). of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 51).

One pulse mode cycle

Notes:
ICR1 = Counter 1. The OCF1 bit cannot be set by hardware in one
When pulse mode but the OCF2 bit can generate an
event occurs OCMP1 = OLVL2
on ICAP1 Output Compare interrupt.
Counter is reset
to FFFCh 2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
ICF1 bit is set PWM mode is the only active one.
When 3. If OLVL1=OLVL2 a continuous signal will be
Counter seen on the OCMP1 pin.
= OC1R OCMP1 = OLVL1
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
Then, on a valid event on the ICAP1 pin, the coun- loaded) but the user must take care that the
ter is initialized to FFFCh and OLVL2 bit is loaded counter is reset each time a valid edge occurs
on the OCMP1 pin, the ICF1 bit is set and the val- on the ICAP1 pin and ICF1 can also generates
ue FFFDh is loaded in the IC1R register. interrupt if ICIE is set.
Because the ICF1 bit is set when an active edge 5. When one pulse mode is used OC1R is dedi-
occurs, an interrupt can be generated if the ICIE cated to this mode. Nevertheless OC2R and
bit is set. OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.

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ST72F521, ST72521B

16-BIT TIMER (Cont’d)

Figure 51. One Pulse Mode Timing Example

IC1R 01F8 2ED3

01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3

ICAP1

OCMP1 OLVL2 OLVL1 OLVL2

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OLVL2 OLVL1 OLVL2

OCMP1
compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated us-
ing the output compare and the counter overflow to define the pulse length.

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 ST72F521, ST72521B

16-BIT TIMER (Cont’d)

10.4.3.6 Pulse Width Modulation Mode If OLVL1=1 and OLVL2=0 the length of the posi-
Pulse Width Modulation (PWM) mode enables the tive pulse is the difference between the OC2R and
generation of a signal with a frequency and pulse OC1R registers.
length determined by the value of the OC1R and If OLVL1=OLVL2 a continuous signal will be seen
OC2R registers. on the OCMP1 pin.
Pulse Width Modulation mode uses the complete The OCiR register value required for a specific tim-
Output Compare 1 function plus the OC2R regis- ing application can be calculated using the follow-
ter, and so this functionality can not be used when ing formula:
PWM mode is activated. t * fCPU
OCiR Value =
-5
In PWM mode, double buffering is implemented on
PRESC
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken Where:
into account only at the end of the PWM period t = Signal or pulse period (in seconds)
(OC2) to avoid spikes on the PWM output pin fCPU = CPU clock frequency (in hertz)
(OCMP1).
PRESC = Timer prescaler factor (2, 4 or 8 depend-
Procedure ing on CC[1:0] bits, see Table 16 Clock
To use pulse width modulation mode: Control Bits)
1. Load the OC2R register with the value corre- If the timer clock is an external clock the formula is:
sponding to the period of the signal using the
formula in the opposite column. OCiR = t * fEXT -5
2. Load the OC1R register with the value corre- Where:
sponding to the period of the pulse if (OLVL1=0 t = Signal or pulse period (in seconds)
and OLVL2=1) using the formula in the oppo-
site column. fEXT = External timer clock frequency (in hertz)
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap- The Output Compare 2 event causes the counter
plied to the OCMP1 pin after a successful to be initialized to FFFCh (See Figure 52)
comparison with the OC1R register. Notes:
– Using the OLVL2 bit, select the level to be ap- 1. After a write instruction to the OCiHR register,
plied to the OCMP1 pin after a successful the output compare function is inhibited until the
comparison with the OC2R register. OCiLR register is also written.
4. Select the following in the CR2 register: 2. The OCF1 and OCF2 bits cannot be set by
– Set OC1E bit: the OCMP1 pin is then dedicat- hardware in PWM mode therefore the Output
ed to the output compare 1 function. Compare interrupt is inhibited.
– Set the PWM bit. 3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits). timer interrupt if the ICIE bit is set and the I bit is
cleared.
Pulse Width Modulation cycle 4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
When nected to the timer. The ICAP2 pin can be used
Counter OCMP1 = OLVL1 to perform input capture (ICF2 can be set and
= OC1R IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When OCMP1 = OLVL2 5. When the Pulse Width Modulation (PWM) and
Counter Counter is reset One Pulse Mode (OPM) bits are both set, the
= OC2R to FFFCh PWM mode is the only active one.
ICF1 bit is set

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16-BIT TIMER (Cont’d)

10.4.4 Low Power Modes
Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.

10.4.5 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 Yes No
ICIE
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer modes

TIMER RESOURCES
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Yes Yes Yes
Output Compare (1 and/or 2) Yes Yes Yes Yes
One Pulse Mode No Not Recommended1) No Partially 2)
PWM Mode No Not Recommended 3) No No

1) See note 4 in Section 10.4.3.5 One Pulse Mode

2) See note 5 in Section 10.4.3.5 One Pulse Mode
3) See note 4 in Section 10.4.3.6 Pulse Width Modulation Mode

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16-BIT TIMER (Cont’d)

10.4.7 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

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16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 16. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0 0
mains active. fCPU / 2 0 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 1 0
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled. External Clock (where
1 1
available)

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the Note: If the external clock pin is not available, pro-
timer on the OCMP2 pin (OLV2 in Output Com- gramming the external clock configuration stops
pare mode). Whatever the value of the OC2E bit, the counter.
the Output Compare 2 function of the timer re-
mains active. Bit 1 = IEDG2 Input Edge 2.
0: OCMP2 pin alternate function disabled (I/O pin This bit determines which type of level transition
free for general-purpose I/O). on the ICAP2 pin will trigger the capture.
1: OCMP2 pin alternate function enabled. 0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active. Bit 0 = EXEDG External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be This bit determines which type of level transition
used to trigger one pulse on the OCMP1 pin; the on the external clock pin EXTCLK will trigger the
active transition is given by the IEDG1 bit. The counter register.
length of the generated pulse depends on the 0: A falling edge triggers the counter register.
contents of the OC1R register. 1: A rising edge triggers the counter register.

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16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR) Note: Reading or writing the ACLR register does
Read/Write (bits 7:3 read only) not clear TOF.
Reset Value: xxxx x0xx (xxh)
7 0 Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
Bit 7 = ICF1 Input Capture Flag 1. (IC2LR) register.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin Bit 3 = OCF2 Output Compare Flag 2.
or the counter has reached the OC2R value in 0: No match (reset value).
PWM mode. To clear this bit, first read the SR 1: The content of the free running counter has
register, then read or write the low byte of the matched the content of the OC2R register. To
IC1R (IC1LR) register. clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
Bit 6 = OCF1 Output Compare Flag 1. ister.
0: No match (reset value).
1: The content of the free running counter has Bit 2 = TIMD Timer disable.
matched the content of the OC1R register. To This bit is set and cleared by software. When set, it
clear this bit, first read the SR register, then read freezes the timer prescaler and counter and disa-
or write the low byte of the OC1R (OC1LR) reg- bled the output functions (OCMP1 and OCMP2
ister. pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
Bit 5 = TOF Timer Overflow Flag. configuration to be changed, or the counter reset,
0: No timer overflow (reset value). while it is disabled.
1: The free running counter rolled over from FFFFh 0: Timer enabled
to 0000h. To clear this bit, first read the SR reg- 1: Timer prescaler, counter and outputs disabled
ister, then read or write the low byte of the CR
(CLR) register. Bits 1:0 = Reserved, must be kept cleared.

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16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR) OUTPUT COMPARE 1 HIGH REGISTER
Read Only (OC1HR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 1000 0000 (80h)
high part of the counter value (transferred by the This is an 8-bit register that contains the high part
input capture 1 event). of the value to be compared to the CHR register.
7 0 7 0

MSB LSB MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR) OUTPUT COMPARE 1 LOW REGISTER

Read Only (OC1LR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 0000 0000 (00h)
low part of the counter value (transferred by the in- This is an 8-bit register that contains the low part of
put capture 1 event). the value to be compared to the CLR register.
7 0 7 0

MSB LSB MSB LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER ALTERNATE COUNTER HIGH REGISTER
(OC2HR) (ACHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

OUTPUT COMPARE 2 LOW REGISTER ALTERNATE COUNTER LOW REGISTER

(OC2LR) (ACLR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to CSR register does not clear the TOF bit in the
CSR register.
MSB LSB
7 0

COUNTER HIGH REGISTER (CHR) MSB LSB

Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

COUNTER LOW REGISTER (CLR) MSB LSB

Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of INPUT CAPTURE 2 LOW REGISTER (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the CSR register clears the TOF bit. Reset Value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

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16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Timer A: 32 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer B: 41 Reset Value 0 0 0 0 0 0 0 0
Timer A: 33 CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD - -
Timer B: 43 Reset Value x x x x x 0 x x
Timer A: 34 IC1HR MSB LSB
Timer B: 44 Reset Value x x x x x x x x
Timer A: 35 IC1LR MSB LSB
Timer B: 45 Reset Value x x x x x x x x
Timer A: 36 OC1HR MSB LSB
Timer B: 46 Reset Value 1 0 0 0 0 0 0 0
Timer A: 37 OC1LR MSB LSB
Timer B: 47 Reset Value 0 0 0 0 0 0 0 0
Timer A: 3E OC2HR MSB LSB
Timer B: 4E Reset Value 1 0 0 0 0 0 0 0
Timer A: 3F OC2LR MSB LSB
Timer B: 4F Reset Value 0 0 0 0 0 0 0 0
Timer A: 38 CHR MSB LSB
Timer B: 48 Reset Value 1 1 1 1 1 1 1 1
Timer A: 39 CLR MSB LSB
Timer B: 49 Reset Value 1 1 1 1 1 1 0 0
Timer A: 3A ACHR MSB LSB
Timer B: 4A Reset Value 1 1 1 1 1 1 1 1
Timer A: 3B ACLR MSB LSB
Timer B: 4B Reset Value 1 1 1 1 1 1 0 0
Timer A: 3C IC2HR MSB LSB
Timer B: 4C Reset Value x x x x x x x x
Timer A: 3D IC2LR MSB LSB
Timer B: 4D Reset Value x x x x x x x x

Related Documentation AN1041: Using ST7 PWM signal to generate ana-

AN 973: SCI software communications using 16- log input (sinusoid)
bit timer AN1046: UART emulation software
AN 974: Real Time Clock with ST7 Timer Output AN1078: PWM duty cycle switch implementing
Compare true 0 or 100 per cent duty cycle
AN 976: Driving a buzzer through the ST7 Timer AN1504: Starting a PWM signal directly at high
PWM function level using the ST7 16-Bit timer

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10.5 SERIAL PERIPHERAL INTERFACE (SPI)

10.5.1 Introduction Note: In slave mode, continuous transmission is
The Serial Peripheral Interface (SPI) allows full- not possible at maximum frequency due to the
duplex, synchronous, serial communication with software overhead for clearing status flags and to
external devices. An SPI system may consist of a initiate the next transmission sequence.
master and one or more slaves however the SPI 10.5.3 General Description
interface can not be a master in a multi-master Figure 53 shows the serial peripheral interface
system. (SPI) block diagram. There are 3 registers:
10.5.2 Main Features – SPI Control Register (SPICR)
■ Full duplex synchronous transfers (on 3 lines)
– SPI Control/Status Register (SPICSR)
■ Simplex synchronous transfers (on 2 lines)
– SPI Data Register (SPIDR)
■ Master or slave operation
The SPI is connected to external devices through
■ Six master mode frequencies (fCPU/4 max.)
4 pins:
■ fCPU/2 max. slave mode frequency (see note)
– MISO: Master In / Slave Out data
■ SS Management by software or hardware
– MOSI: Master Out / Slave In data
■ Programmable clock polarity and phase
– SCK: Serial Clock out by SPI masters and in-
■ End of transfer interrupt flag
put by SPI slaves
■ Write collision, Master Mode Fault and Overrun
flags
Figure 53. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR Read
Interrupt
request
Read Buffer

MOSI
7 SPICSR 0
MISO 8-Bit Shift Register
SPIF WCOL OVR MODF 0 SOD SSM SSI

Write
SOD
bit 1
SS
SPI 0
SCK STATE
CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL CLOCK
GENERATOR
SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

– SS: Slave select: The communication is always initiated by the mas-
This input signal acts as a ‘chip select’ to let ter. When the master device transmits data to a
the SPI master communicate with slaves indi- slave device via MOSI pin, the slave device re-
vidually and to avoid contention on the data sponds by sending data to the master device via
lines. Slave SS inputs can be driven by stand- the MISO pin. This implies full duplex communica-
ard I/O ports on the master MCU. tion with both data out and data in synchronized
10.5.3.1 Functional Description with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in To use a single data line, the MISO and MOSI pins
Figure 54. must be connected at each node ( in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way Four possible data/clock timing relationships may
data is transferred serially between master and be chosen (see Figure 57) but master and slave
slave (most significant bit first). must be programmed with the same timing mode.

Figure 54. Single Master/ Single Slave Application

MASTER SLAVE
MSBit LSBit MSBit LSBit
MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS SS
+5V
Not used if SS is managed
by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.2 Slave Select Management In Slave Mode:
As an alternative to using the SS pin to control the There are two cases depending on the data/clock
Slave Select signal, the application can choose to timing relationship (see Figure 55):
manage the Slave Select signal by software. This If CPHA=1 (data latched on 2nd clock edge):
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 56) – SS internal must be held low during the entire
transmission. This implies that in single slave
In software management, the external SS pin is applications the SS pin either can be tied to
free for other application uses and the internal SS VSS, or made free for standard I/O by manag-
signal level is driven by writing to the SSI bit in the ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
SPICSR register.
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
– SS internal must be held high continuously transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.5.5.3).
Figure 55. Generic SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(if CPHA=0)

Slave SS
(if CPHA=1)

Figure 56. Hardware/Software Slave Select Management

SSM bit

SSI bit 1
SS internal
SS external pin 0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.3 Master Mode Operation Note: While the SPIF bit is set, all writes to the
In master mode, the serial clock is output on the SPIDR register are inhibited until the SPICSR reg-
SCK pin. The clock frequency, polarity and phase ister is read.
are configured by software (refer to the description 10.5.3.5 Slave Mode Operation
of the SPICSR register). In slave mode, the serial clock is received on the
Note: The idle state of SCK must correspond to SCK pin from the master device.
the polarity selected in the SPICSR register (by To operate the SPI in slave mode:
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0). 1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is – Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
not written first, the SPICR register setting (MSTR Figure 57).
bit) may be not taken into account): Note: The slave must have the same CPOL
1. Write to the SPICR register: and CPHA settings as the master.
– Manage the SS pin as described in Section
– Select the clock frequency by configuring the 10.5.3.2 and Figure 55. If CPHA=1 SS must
SPR[2:0] bits. be held low continuously. If CPHA=0 SS must
– Select the clock polarity and clock phase by be held low during byte transmission and
configuring the CPOL and CPHA bits. Figure pulled up between each byte to let the slave
57 shows the four possible configurations. write in the shift register.
Note: The slave must have the same CPOL 2. Write to the SPICR register to clear the MSTR
and CPHA settings as the master.
bit and set the SPE bit to enable the SPI I/O
2. Write to the SPICSR register: functions.
– Either set the SSM bit and set the SSI bit or 10.5.3.6 Slave Mode Transmit Sequence
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence. When software writes to the SPIDR register, the
3. Write to the SPICR register: data byte is loaded into the 8-bit shift register and
– Set the MSTR and SPE bits then shifted out serially to the MISO pin most sig-
Note: MSTR and SPE bits remain set only if nificant bit first.
SS is high). The transmit sequence begins when the slave de-
The transmit sequence begins when software vice receives the clock signal and the most signifi-
writes a byte in the SPIDR register. cant bit of the data on its MOSI pin.
10.5.3.4 Master Mode Transmit Sequence When data transfer is complete:
When software writes to the SPIDR register, the – The SPIF bit is set by hardware
data byte is loaded into the 8-bit shift register and
– An interrupt request is generated if SPIE bit is
then shifted out serially to the MOSI pin most sig-
set and interrupt mask in the CCR register is
nificant bit first.
cleared.
When data transfer is complete: Clearing the SPIF bit is performed by the following
– The SPIF bit is set by hardware software sequence:
– An interrupt request is generated if the SPIE 1. An access to the SPICSR register while the
bit is set and the interrupt mask in the CCR SPIF bit is set.
register is cleared.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
Notes: While the SPIF bit is set, all writes to the
software sequence:
SPIDR register are inhibited until the SPICSR reg-
1. An access to the SPICSR register while the ister is read.
SPIF bit is set
The SPIF bit can be cleared during a second
2. A read to the SPIDR register. transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.5.5.2).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4 Clock Phase and Clock Polarity Figure 57, shows an SPI transfer with the four
Four possible timing relationships may be chosen combinations of the CPHA and CPOL bits. The di-
by software, using the CPOL and CPHA bits (See agram may be interpreted as a master or slave
Figure 57). timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
Note: The idle state of SCK must correspond to master and the slave device.
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if Note: If CPOL is changed at the communication
CPOL=0). byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA =0
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5 Error Flags not cleared the SPIF bit issued from the previously
10.5.5.1 Master Mode Fault (MODF) transmitted byte.
Master mode fault occurs when the master device When an Overrun occurs:
has its SS pin pulled low. – The OVR bit is set and an interrupt request is
When a Master mode fault occurs: generated if the SPIE bit is set.
– The MODF bit is set and an SPI interrupt re- In this case, the receiver buffer contains the byte
quest is generated if the SPIE bit is set. sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
– The SPE bit is reset. This blocks all output bytes are lost.
from the device and disables the SPI periph-
eral. The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode. 10.5.5.3 Write Collision Error (WCOL)
Clearing the MODF bit is done through a software A write collision occurs when the software tries to
sequence: write to the SPIDR register while a data transfer is
taking place with an external device. When this
1. A read access to the SPICSR register while the happens, the transfer continues uninterrupted;
MODF bit is set. and the software write will be unsuccessful.
2. A write to the SPICR register. Write collisions can occur both in master and slave
Notes: To avoid any conflicts in an application mode. See also Section 10.5.3.2 Slave Select
with multiple slaves, the SS pin must be pulled Management.
high during the MODF bit clearing sequence. The Note: a "read collision" will never occur since the
SPE and MSTR bits may be restored to their orig- received data byte is placed in a buffer in which
inal state during or after this clearing sequence. access is always synchronous with the MCU oper-
Hardware does not allow the user to set the SPE ation.
and MSTR bits while the MODF bit is set except in The WCOL bit in the SPICSR register is set if a
the MODF bit clearing sequence. write collision occurs.
10.5.5.2 Overrun Condition (OVR) No SPI interrupt is generated when the WCOL bit
An overrun condition occurs, when the master de- is set (the WCOL bit is a status flag only).
vice has sent a data byte and the slave device has Clearing the WCOL bit is done through a software
sequence (see Figure 58).
Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step

RESULT
2nd Step Read SPIDR SPIF =0
WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR
1st Step
RESULT Note: Writing to the SPIDR regis-
ter instead of reading it does not
2nd Step Read SPIDR WCOL=0 reset the WCOL bit

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10.5.5.4 Single Master Systems Note: To prevent a bus conflict on the MISO line
A typical single master system may be configured, the master allows only one active slave device
using an MCU as the master and four MCUs as during a transmission.
slaves (see Figure 59). For more security, the slave device may respond
The master device selects the individual slave de- to the master with the received data byte. Then the
vices by using four pins of a parallel port to control master will receive the previous byte back from the
the four SS pins of the slave devices. slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
The SS pins are pulled high during reset since the register.
master device ports will be forced to be inputs at
that time, thus disabling the slave devices. Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 59. Single Master / Multiple Slave Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
MCU MCU MCU MCU

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
MCU
5V SS

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10.5.6 Low Power Modes Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
Mode Description
form an extra communications cycle to bring the
No effect on SPI. SPI from Halt mode state to normal state. If the
WAIT SPI interrupt events cause the device to exit SPI exits from Slave mode, it returns to normal
from WAIT mode. state immediately.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
Caution: The SPI can wake up the ST7 from Halt
ation resumes when the MCU is woken up by
mode only if the Slave Select signal (external SS
an interrupt with “exit from HALT mode” ca- pin or the SSI bit in the SPICSR register) is low
pability. The data received is subsequently when the ST7 enters Halt mode. So if Slave selec-
HALT read from the SPIDR register when the soft- tion is configured as external (see Section
ware is running (interrupt vector fetching). If 10.5.3.2), make sure the master drives a low level
several data are received before the wake- on the SS pin when the slave enters Halt mode.
up event, then an overrun error is generated. 10.5.7 Interrupts
This error can be detected after the fetch of
the interrupt routine that woke up the device. Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
10.5.6.1 Using the SPI to wakeup the MCU from
Halt mode SPI End of Transfer
SPIF Yes Yes
Event
In slave configuration, the SPI is able to wakeup Master Mode Fault SPIE
the ST7 device from HALT mode through a SPIF MODF Yes No
Event
interrupt. The data received is subsequently read
Overrun Error OVR Yes No
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
Note: The SPI interrupt events are connected to
fers have been performed before software clears
the same interrupt vector (see Interrupts chapter).
the SPIF bit, then the OVR bit is set by hardware.
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in

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10.5.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write Bit 3 = CPOL Clock Polarity.
Reset Value: 0000 xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
7 0
CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
Bit 7 = SPIE Serial Peripheral Interrupt Enable. byte boundaries, the SPI must be disabled by re-
This bit is set and cleared by software. setting the SPE bit.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever Bit 2 = CPHA Clock Phase.
SPIF=1, MODF=1 or OVR=1 in the SPICSR This bit is set and cleared by software.
register 0: The first clock transition is the first data capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable. 1: The second clock transition is the first capture
This bit is set and cleared by software. It is also edge.
cleared by hardware when, in master mode, SS=0 Note: The slave must have the same CPOL and
(see Section 10.5.5.1 Master Mode Fault CPHA settings as the master.
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins. Bits 1:0 = SPR[1:0] Serial Clock Frequency.
0: I/O pins free for general purpose I/O These bits are set and cleared by software. Used
1: SPI I/O pin alternate functions enabled with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Bit 5 = SPR2 Divider Enable. Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to Table 18. SPI Master mode SCK Frequency
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency. Serial Clock SPR2 SPR1 SPR0
0: Divider by 2 enabled fCPU/4 1 0 0
1: Divider by 2 disabled
fCPU/8 0 0 0
Note: This bit has no effect in slave mode.
fCPU/16 0 0 1
fCPU/32 1 1 0
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also fCPU/64 0 1 0
cleared by hardware when, in master mode, SS=0 fCPU/128 0 1 1
(see Section 10.5.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.

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CONTROL/STATUS REGISTER (SPICSR) Bit 3 = Reserved, must be kept cleared.
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable.
7 0 This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
SPIF WCOL OVR MODF - SOD SSM SSI (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has Bit 1 = SSM SS Management.
been completed. An interrupt is generated if This bit is set and cleared by software. When set, it
SPIE=1 in the SPICR register. It is cleared by a disables the alternate function of the SPI SS pin
software sequence (an access to the SPICSR and uses the SSI bit value instead. See Section
register followed by a write or a read to the 10.5.3.2 Slave Select Management.
SPIDR register). 0: Hardware management (SS managed by exter-
0: Data transfer is in progress or the flag has been nal pin)
cleared. 1: Software management (internal SS signal con-
1: Data transfer between the device and an exter- trolled by SSI bit. External SS pin free for gener-
nal device has been completed. al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg- Bit 0 = SSI SS Internal Mode.
ister is read. This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
Bit 6 = WCOL Write Collision status (Read only). 0 : Slave selected
This bit is set by hardware when a write to the 1 : Slave deselected
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 58). DATA I/O REGISTER (SPIDR)
0: No write collision occurred Read/Write
1: A write collision has been detected Reset Value: Undefined
7 0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently D7 D6 D5 D4 D3 D2 D1 D0
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.5.5.2). An interrupt is generated if The SPIDR register is used to transmit and receive
SPIE = 1 in SPICR register. The OVR bit is cleared data on the serial bus. In a master device, a write
by software reading the SPICSR register. to this register will initiate transmission/reception
0: No overrun error of another byte.
1: Overrun error detected Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
Bit 4 = MODF Mode Fault flag (Read only). the serial peripheral data I/O register, the buffer is
This bit is set by hardware when the SS pin is actually being read.
pulled low in master mode (see Section 10.5.5.1
Master Mode Fault (MODF)). An SPI interrupt can While the SPIF bit is set, all writes to the SPIDR
be generated if SPIE=1 in the SPICSR register. register are inhibited until the SPICSR register is
This bit is cleared by a software sequence (An ac- read.
cess to the SPICR register while MODF=1 fol- Warning: A write to the SPIDR register places
lowed by a write to the SPICR register). data directly into the shift register for transmission.
0: No master mode fault detected
A read to the SPIDR register returns the value lo-
1: A fault in master mode has been detected
cated in the buffer and not the content of the shift
register (see Figure 53).

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Table 19. SPI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SPIDR MSB LSB
0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OR MODF SOD SSM SSI
0023h
Reset Value 0 0 0 0 0 0 0 0

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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.6.1 Introduction 10.6.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 61):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous serial data format. The SCI of- ter and the receiver are disabled, the output pin
fers a very wide range of baud rates using two returns to its I/O port configuration. When the
baud rate generator systems. transmitter and/or the receiver are enabled and
10.6.2 Main Features nothing is to be transmitted, the TDO pin is at
■ Full duplex, asynchronous communications high level.
■ NRZ standard format (Mark/Space) – RDI: Receive Data Input is the serial data input.
■ Dual baud rate generator systems
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
■ Independently programmable transmit and data and noise.
receive baud rates up to 500K baud.
Through these pins, serial data is transmitted and
■ Programmable data word length (8 or 9 bits)
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
End of Transmission flags
■ Two receiver wake-up modes:
– A start bit
– Address bit (MSB) – A data word (8 or 9 bits) least significant bit first
– Idle line – A Stop bit indicating that the frame is complete.
■ Muting function for multiprocessor configurations This interface uses two types of baud rate generator:
■ Separate enable bits for Transmitter and – A conventional type for commonly-used baud
Receiver rates,
■ Four error detection flags: – An extended type with a prescaler offering a very
– Overrun error wide range of baud rates even with non-standard
oscillator frequencies.
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:

– Transmits parity bit

– Checks parity of received data byte
■ Reduced power consumption mode

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Figure 60. SCI Block Diagram

Write Read (DATA REGISTER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI
CR1
R8 T8 SCID M WAKE PCE PS PIE

WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK

CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE

SCI
INTERRUPT
CONTROL

TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/16 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4 Functional Description 10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 60. It contains 6 dedicated reg- bits by programming the M bit in the SCICR1 reg-
isters: ister (see Figure 60).
– Two control registers (SCICR1 & SCICR2) The TDO pin is in low state during the start bit.
– A status register (SCISR) The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register (SCIER- of “1”s followed by the start bit of the next frame
PR) which contains data.
– An extended prescaler transmitter register (SCI- A Break character is interpreted on receiving “0”s
ETPR) for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
Refer to the register descriptions in Section tra “1” bit to acknowledge the start bit.
10.6.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 61. Word Length Programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

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10.6.4.2 Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit or after the break frame) the TC bit is set
9 bits depending on the M bit status. When the M and an interrupt is generated if the TCIE is set and
bit is set, word length is 9 bits and the 9th bit (the the I bit is cleared in the CCR register.
MSB) has to be stored in the T8 bit in the SCICR1 Clearing the TC bit is performed by the following
register. software sequence:
Character Transmission 1. An access to the SCISR register
2. A write to the SCIDR register
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the SCIDR register consists of a buffer (TDR) be- same software sequence.
tween the internal bus and the transmit shift regis- Break Characters
ter (see Figure 60). Setting the SBK bit loads the shift register with a
Procedure break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 61).
– Select the desired baud rate using the SCIBRR As long as the SBK bit is set, the SCI send break
and the SCIETPR registers. frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
– Set the TE bit to assign the TDO pin to the alter- the last break frame to guarantee the recognition
nate function and to send a idle frame as first of the start bit of the next frame.
transmission.
Idle Characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears Setting the TE bit drives the SCI to send an idle
the TDRE bit). Repeat this sequence for each frame before the first data frame.
data to be transmitted. Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence: Note: Resetting and setting the TE bit causes the
1. An access to the SCISR register data in the TDR register to be lost. Therefore the
2. A write to the SCIDR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set i.e. before writing the next byte in the SCIDR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.

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10.6.4.3 Receiver RDR register as long as the RDRF bit is not
The SCI can receive data words of either 8 or 9 cleared.
bits. When the M bit is set, word length is 9 bits When a overrun error occurs:
and the MSB is stored in the R8 bit in the SCICR1 – The OR bit is set.
register.
– The RDR content will not be lost.
Character reception
– The shift register will be overwritten.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the – An interrupt is generated if the RIE bit is set and
SCIDR register consists or a buffer (RDR) be- the I bit is cleared in the CCR register.
tween the internal bus and the received shift regis- The OR bit is reset by an access to the SCISR reg-
ter (see Figure 60). ister followed by a SCIDR register read operation.
Procedure Noise Error
– Select the M bit to define the word length. Oversampling techniques are used for data recov-
– Select the desired baud rate using the SCIBRR ery by discriminating between valid incoming data
and the SCIERPR registers. and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
– Set the RE bit, this enables the receiver which the same bit value, otherwise the NF flag is set. In
begins searching for a start bit. the case of start bit detection, the NF flag is set on
When a character is received: the basis of an algorithm combining both valid
– The RDRF bit is set. It indicates that the content edge detection and three samples (8th, 9th, 10th).
of the shift register is transferred to the RDR. Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
– An interrupt is generated if the RIE bit is set and tection as well as three valid samples.
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – The NF flag is set at the rising edge of the RDRF
ception. bit.
Clearing the RDRF bit is performed by the following – Data is transferred from the Shift register to the
software sequence done by: SCIDR register.
1. An access to the SCISR register – No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
2. A read to the SCIDR register. generates an interrupt.
The RDRF bit must be cleared before the end of the The NF flag is reset by a SCISR register read op-
reception of the next character to avoid an overrun eration followed by a SCIDR register read opera-
error. tion.
Break Character During reception, if a false start bit is detected (e.g.
When a break character is received, the SPI han- 8th, 9th, 10th samples are 011,101,110), the
dles it as a framing error. frame is discarded and the receiving sequence is
Idle Character not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
When a idle frame is detected, there is the same accessible to the user). This NF flag is accessible
procedure as a data received character plus an in- along with the RDRF bit when a next valid frame is
terrupt if the ILIE bit is set and the I bit is cleared in received.
the CCR register.
Note: If the application Start Bit is not long enough
Overrun Error to match the above requirements, then the NF
An overrun error occurs when a character is re- Flag may get set due to the short Start Bit. In this
ceived when RDRF has not been reset. Data can case, the NF flag may be ignored by the applica-
not be transferred from the shift register to the tion software when the first valid byte is received.
See also Section 10.6.4.10.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER

RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

fCPU

TRANSMITTER RATE
CONTROL
/16 /PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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Framing Error Note: the extended prescaler is activated by set-
A framing error is detected when: ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
– The stop bit is not recognized on reception at the follows:
expected time, following either a de-synchroni-
zation or excessive noise. fCPU fCPU
– A break is received. Tx = Rx =
16*ETPR*(PR*TR) 16*ERPR*(PR*RR)
When the framing error is detected:
– the FE bit is set by hardware
with:
– Data is transferred from the Shift register to the
SCIDR register. ETPR = 1,..,255 (see SCIETPR register)
– No interrupt is generated. However this bit rises ERPR = 1,.. 255 (see SCIERPR register)
at the same time as the RDRF bit which itself 10.6.4.6 Receiver Muting and Wake-up Feature
generates an interrupt. In multiprocessor configurations it is often desira-
The FE bit is reset by a SCISR register read oper- ble that only the intended message recipient
ation followed by a SCIDR register read operation. should actively receive the full message contents,
10.6.4.4 Conventional Baud Rate Generation thus reducing redundant SCI service overhead for
all non addressed receivers.
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as The non addressed devices may be placed in
follows: sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
fCPU fCPU
Tx = Rx = sleep mode:
(16*PR)*TR (16*PR)*RR All the reception status bits can not be set.
with: All the receive interrupts are inhibited.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits) A muted receiver may be awakened by one of the
following two ways:
TR = 1, 2, 4, 8, 16, 32, 64,128
– by Idle Line detection if the WAKE bit is reset,
(see SCT[2:0] bits)
– by Address Mark detection if the WAKE bit is set.
RR = 1, 2, 4, 8, 16, 32, 64,128
Receiver wakes-up by Idle Line detection when
(see SCR[2:0] bits) the Receive line has recognised an Idle Frame.
All these bits are in the SCIBRR register. Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Example: If fCPU is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive Receiver wakes-up by Address Mark detection
baud rates are 38400 baud. when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
Note: the baud rate registers MUST NOT be
dress. The reception of this particular word wakes
changed while the transmitter or the receiver is en-
up the receiver, resets the RWU bit and sets the
abled.
RDRF bit, which allows the receiver to receive this
10.6.4.5 Extended Baud Rate Generation word normally and to use it as an address word.
The extended prescaler option gives a very fine Caution: In Mute mode, do not write to the
tuning on the baud rate, using a 255 value prescal- SCICR2 register. If the SCI is in Mute mode during
er, whereas the conventional Baud Rate Genera- the read operation (RWU=1) and a address mark
tor retains industry standard software compatibili- wake up event occurs (RWU is reset) before the
ty. write operation, the RWU bit will be set again by
The extended baud rate generator block diagram this write operation. Consequently the address
is described in the Figure 62. byte is lost and the SCI is not woken up from Mute
mode.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.

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10.6.4.7 Parity Control even number of “1s” if even parity is selected
Parity control (generation of parity bit in transmis- (PS=0) or an odd number of “1s” if odd parity is se-
sion and parity checking in reception) can be ena- lected (PS=1). If the parity check fails, the PE flag
bled by setting the PCE bit in the SCICR1 register. is set in the SCISR register and an interrupt is gen-
Depending on the frame length defined by the M erated if PIE is set in the SCICR1 register.
bit, the possible SCI frame formats are as listed in 10.6.4.8 SCI Clock Tolerance
Table 20. During reception, each bit is sampled 16 times.
Table 20. Frame Formats The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
M bit PCE bit SCI frame tion, all the three samples should have the same
0 0 | SB | 8 bit data | STB | value otherwise the noise flag (NF) is set. For ex-
0 1 | SB | 7-bit data | PB | STB | ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value will be “1”,
1 0 | SB | 9-bit data | STB |
but the Noise Flag bit is be set because the three
1 1 | SB | 8-bit data PB | STB | samples values are not the same.
Legend: SB = Start Bit, STB = Stop Bit,
Consequently, the bit length must be long enough
PB = Parity Bit
so that the 8th, 9th and 10th samples have the de-
Note: In case of wake up by an address mark, the sired bit value. This means the clock frequency
MSB bit of the data is taken into account and not should not vary more than 6/16 (37.5%) within one
the parity bit bit. The sampling clock is resynchronized at each
Even parity: the parity bit is calculated to obtain start bit, so that when receiving 10 bits (one start
an even number of “1s” inside the frame made of bit, 1 data byte, 1 stop bit), the clock deviation
the 7 or 8 LSB bits (depending on whether M is must not exceed 3.75%.
equal to 0 or 1) and the parity bit. Note: The internal sampling clock of the microcon-
Ex: data=00110101; 4 bits set => parity bit will be troller samples the pin value on every falling edge.
0 if even parity is selected (PS bit = 0). Therefore, the internal sampling clock and the time
the application expects the sampling to take place
Odd parity: the parity bit is calculated to obtain an may be out of sync. For example: If the baud rate
odd number of “1s” inside the frame made of the 7 is 15.625 kbaud (bit length is 64µs), then the 8th,
or 8 LSB bits (depending on whether M is equal to 9th and 10th samples will be at 28µs, 32µs & 36µs
0 or 1) and the parity bit. respectively (the first sample starting ideally at
Ex: data=00110101; 4 bits set => parity bit will be 0µs). But if the falling edge of the internal clock oc-
1 if odd parity is selected (PS bit = 1). curs just before the pin value changes, the sam-
Transmission mode: If the PCE bit is set then the ples would then be out of sync by ~4us. This
MSB bit of the data written in the data register is means the entire bit length must be at least 40µs
not transmitted but is changed by the parity bit. (36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.9 Clock Deviation Causes 10.6.4.10 Noise Error Causes
The causes which contribute to the total deviation See also description of Noise error in Section
are: 10.6.4.3.
– DTRA: Deviation due to transmitter error (Local Start bit
oscillator error of the transmitter or the trans- The noise flag (NF) is set during start bit reception
mitter is transmitting at a different baud rate). if one of the following conditions occurs:
– DQUANT: Error due to the baud rate quantisa- 1. A valid falling edge is not detected. A falling
tion of the receiver. edge is considered to be valid if the 3 consecu-
– DREC: Deviation of the local oscillator of the tive samples before the falling edge occurs are
receiver: This deviation can occur during the detected as '1' and, after the falling edge
reception of one complete SCI message as- occurs, during the sampling of the 16 samples,
suming that the deviation has been compen- if one of the samples numbered 3, 5 or 7 is
sated at the beginning of the message. detected as a “1”.
– DTCL: Deviation due to the transmission line 2. During sampling of the 16 samples, if one of the
(generally due to the transceivers) samples numbered 8, 9 or 10 is detected as a
All the deviations of the system should be added “1”.
and compared to the SCI clock tolerance: Therefore, a valid Start Bit must satisfy both the
DTRA + DQUANT + DREC + DTCL < 3.75% above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.

Figure 63. Bit Sampling in Reception Mode

RDI LINE

sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Low Power Modes Enable Exit Exit
Event
Interrupt Event Control from from
Mode Description Flag
Bit Wait Halt
No effect on SCI. Transmit Data Register
WAIT TDRE TIE Yes No
SCI interrupts cause the device to exit Empty
from Wait mode. Transmission Com-
TC TCIE Yes No
SCI registers are frozen. plete
Received Data Ready
In Halt mode, the SCI stops transmit- RDRF Yes No
HALT to be Read RIE
ting/receiving until Halt mode is exit-
Overrun Error Detected OR Yes No
ed.
Idle Line Detected IDLE ILIE Yes No
10.6.6 Interrupts Parity Error PE PIE Yes No
The SCI interrupt events are connected to the rupt mask in the CC register is reset (RIM instruc-
same interrupt vector. tion).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-

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10.6.7 Register Description Note: The IDLE bit will not be set again until the
STATUS REGISTER (SCISR) RDRF bit has been set itself (i.e. a new idle line oc-
Read Only curs).
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE TC RDRF IDLE OR NF FE PE
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
Bit 7 = TDRE Transmit data register empty. register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the access to the SCISR register followed by a read to
TDR register has been transferred into the shift the SCIDR register).
register. An interrupt is generated if the TIE bit=1 0: No Overrun error
in the SCICR2 register. It is cleared by a software 1: Overrun error is detected
sequence (an access to the SCISR register fol- Note: When this bit is set RDR register content will
lowed by a write to the SCIDR register). not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift reg- Bit 2 = NF Noise flag.
ister unless the TDRE bit is cleared. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
Bit 6 = TC Transmission complete. by a read to the SCIDR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data is complete. An interrupt is 1: Noise is detected
generated if TCIE=1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it ap-
cleared by a software sequence (an access to the pears at the same time as the RDRF bit which it-
SCISR register followed by a write to the SCIDR self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a Pre- This bit is set by hardware when a de-synchroniza-
amble or a Break. tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag. the SCIDR register).
This bit is set by hardware when the content of the 0: No Framing error is detected
RDR register has been transferred to the SCIDR 1: Framing error or break character is detected
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se- Note: This bit does not generate interrupt as it ap-
quence (an access to the SCISR register followed pears at the same time as the RDRF bit which it-
by a read to the SCIDR register). self generates an interrupt. If the word currently
0: Data is not received being transferred causes both frame error and
1: Received data is ready to be read overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de- Bit 0 = PE Parity error.
tected. An interrupt is generated if the ILIE=1 in This bit is set by hardware when a parity error oc-
the SCICR2 register. It is cleared by a software se- curs in receiver mode. It is cleared by a software
quence (an access to the SCISR register followed sequence (a read to the status register followed by
by a read to the SCIDR register). an access to the SCIDR data register). An inter-
0: No Idle Line is detected rupt is generated if PIE=1 in the SCICR1 register.
1: Idle Line is detected 0: No parity error
1: Parity error

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (SCICR1)
Read/Write Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7 0 0: Idle Line
1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE

Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8. This bit selects the hardware parity control (gener-
This bit is used to store the 9th bit of the received ation and detection). When the parity control is en-
word when M=1. abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
Bit 6 = T8 Transmit data bit 8. cleared by software. Once it is set, PCE is active
This bit is used to store the 9th bit of the transmit- after the current byte (in reception and in transmis-
ted word when M=1. sion).
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans- Bit 1 = PS Parity selection.
fer in order to reduce power consumption.This bit This bit selects the odd or even parity when the
is set and cleared by software. parity generation/detection is enabled (PCE bit
0: SCI enabled set). It is set and cleared by software. The parity
1: SCI prescaler and outputs disabled will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software. Bit 0 = PIE Parity interrupt enable.
0: 1 Start bit, 8 Data bits, 1 Stop bit This bit enables the interrupt capability of the hard-
1: 1 Start bit, 9 Data bits, 1 Stop bit ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
1: Parity error interrupt enabled.
transfer (both transmission and reception).

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 2 (SCICR2) Notes:
Read/Write – During transmission, a “0” pulse on the TE bit
Reset Value: 0000 0000 (00h) (“0” followed by “1”) sends a preamble (idle line)
after the current word.
7 0 – When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE TCIE RIE ILIE TE RE RWU SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
Bit 7 = TIE Transmitter interrupt enable. (or if TE is never set).
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever Bit 2 = RE Receiver enable.
TDRE=1 in the SCISR register This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena- 1: Receiver is enabled and begins searching for a
ble start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in Bit 1 = RWU Receiver wake-up.
the SCISR register This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable. recognized.
This bit is set and cleared by software. 0: Receiver in Active mode
0: Interrupt is inhibited 1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable. wakeup by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is
in the SCISR register. set and cleared by software.
0: No break character is transmitted
Bit 3 = TE Transmitter enable. 1: Break characters are transmitted
This bit enables the transmitter. It is set and Note: If the SBK bit is set to “1” and then to “0”, the
cleared by software. transmitter will send a BREAK word at the end of
0: Transmitter is disabled the current word.
1: Transmitter is enabled

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (SCIDR) Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
Reset Value: Undefined clock to yield the transmit rate clock in convention-
Contains the Received or Transmitted data char- al Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
TR dividing factor SCT2 SCT1 SCT0
ten to.
1 0 0 0
7 0
2 0 0 1
4 0 1 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
8 0 1 1
The Data register performs a double function (read 16 1 0 0
and write) since it is composed of two registers, 32 1 0 1
one for transmission (TDR) and one for reception 64 1 1 0
(RDR).
128 1 1 1
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 60). Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
The RDR register provides the parallel interface These 3 bits, in conjunction with the SCP[1:0] bits
between the input shift register and the internal define the total division applied to the bus clock to
bus (see Figure 60). yield the receive rate clock in conventional Baud
Rate Generator mode.
BAUD RATE REGISTER (SCIBRR) RR Dividing factor SCR2 SCR1 SCR0
Read/Write 1 0 0 0
Reset Value: 0000 0000 (00h) 2 0 0 1
4 0 1 0
7 0
8 0 1 1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 16 1 0 0
32 1 0 1
Bits 7:6= SCP[1:0] First SCI Prescaler 64 1 1 0
These 2 prescaling bits allow several standard 128 1 1 1
clock division ranges:
PR Prescaling factor SCP1 SCP0
1 0 0
3 0 1
4 1 0
13 1 1

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR) REGISTER (SCIETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit. sion factor for the transmit circuit.
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register. Prescaler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value different from 00h is stored in this when a value different from 00h is stored in this
register. Therefore the clock frequency issued register. Therefore the clock frequency issued
from the 16 divider (see Figure 62) is divided by from the 16 divider (see Figure 62) is divided by
the binary factor set in the SCIERPR register (in the binary factor set in the SCIETPR register (in
the range 1 to 255). the range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset. ter a reset.
Table 21. Baudrate Selection
Conditions
Baud
Symbol Parameter Accuracy Standard Unit
fCPU Prescaler Rate
vs. Standard
Conventional Mode
TR (or RR)=128, PR=13 300 ~300.48
TR (or RR)= 32, PR=13 1200 ~1201.92
TR (or RR)= 16, PR=13 2400 ~2403.84
~0.16% TR (or RR)= 8, PR=13 4800 ~4807.69
fTx TR (or RR)= 4, PR=13 9600 ~9615.38
Communication frequency 8MHz TR (or RR)= 16, PR= 3 10400 ~10416.67 Hz
fRx
TR (or RR)= 2, PR=13 19200 ~19230.77
TR (or RR)= 1, PR=13 38400 ~38461.54
Extended Mode
~0.79% ETPR (or ERPR) = 35, 14400 ~14285.71
TR (or RR)= 1, PR=1

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Table 22. SCI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SCISR TDRE TC RDRF IDLE OR NF FE PE
0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0052h
Reset Value 0 0 0 0 0 0 0 0
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
0053h
Reset Value x 0 0 0 0 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIERPR MSB LSB
0055h
Reset Value 0 0 0 0 0 0 0 0
SCIPETPR MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0

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10.7 I2C BUS INTERFACE (I2C)

10.7.1 Introduction and vice versa, using either an interrupt or polled
The I2C Bus Interface serves as an interface be- handshake. The interrupts are enabled or disabled
tween the microcontroller and the serial I2C bus. It by software. The interface is connected to the I2C
provides both multimaster and slave functions, bus by a data pin (SDAI) and by a clock pin (SCLI).
and controls all I2C bus-specific sequencing, pro- It can be connected both with a standard I2C bus
tocol, arbitration and timing. It supports fast I2C and a Fast I2C bus. This selection is made by soft-
mode (400kHz). ware.
10.7.2 Main Features Mode Selection
2
■ Parallel-bus/I C protocol converter The interface can operate in the four following
modes:
■ Multi-master capability

■ 7-bit/10-bit Addressing
– Slave transmitter/receiver
■ SMBus V1.1 Compliant
– Master transmitter/receiver
■ Transmitter/Receiver flag By default, it operates in slave mode.
■ End-of-byte transmission flag The interface automatically switches from slave to
■ Transfer problem detection
master after it generates a START condition and
from master to slave in case of arbitration loss or a
I2C Master Features: STOP generation, allowing then Multi-Master ca-
■ Clock generation pability.
2
■ I C bus busy flag Communication Flow
■ Arbitration Lost Flag In Master mode, it initiates a data transfer and
■ End of byte transmission flag generates the clock signal. A serial data transfer
■ Transmitter/Receiver Flag
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
■ Start bit detection flag
generated in master mode by software.
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
I2C Slave Features: nising its own address (7 or 10-bit), and the Gen-
■ Stop bit detection eral Call address. The General Call address de-
2
■ I C bus busy flag
tection may be enabled or disabled by software.
■ Detection of misplaced start or stop condition
Data and addresses are transferred as 8-bit bytes,
2 MSB first. The first byte(s) following the start con-
■ Programmable I C Address detection
dition contain the address (one in 7-bit mode, two
■ Transfer problem detection in 10-bit mode). The address is always transmitted
■ End-of-byte transmission flag in Master mode.
■ Transmitter/Receiver flag A 9th clock pulse follows the 8 clock cycles of a
10.7.3 General Description byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
In addition to receiving and transmitting data, this ure 64.
interface converts it from serial to parallel format
Figure 64. I2C BUS Protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION
VR02119B

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I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by The SCL frequency (Fscl) is controlled by a pro-
software. grammable clock divider which depends on the
The I2C interface address and/or general call ad- I2C bus mode.
dress can be selected by software. When the I2C cell is enabled, the SDA and SCL
The speed of the I2C interface may be selected ports must be configured as floating inputs. In this
between Standard (up to 100KHz) and Fast I2C case, the value of the external pull-up resistor
(up to 400KHz). used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 65. I2C Interface Block Diagram
DATA REGISTER (DR)

SDA or SDAI DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

OWN ADDRESS REGISTER 2 (OAR2)

SCL or SCLI CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1) CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

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I2C BUS INTERFACE (Cont’d)

10.7.4 Functional Description Then the interface waits for a read of the SR1 reg-
Refer to the CR, SR1 and SR2 registers in Section ister followed by a read of the DR register, holding
10.7.7. for the bit definitions. the SCL line low (see Figure 66 Transfer se-
quencing EV2).
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates Slave Transmitter
a transmit or receive sequence. Following the address reception and after SR1
First the interface frequency must be configured register has been read, the slave sends bytes from
using the FRi bits in the OAR2 register. the DR register to the SDA line via the internal shift
register.
10.7.4.1 Slave Mode
The slave waits for a read of the SR1 register fol-
As soon as a start condition is detected, the lowed by a write in the DR register, holding the
address is received from the SDA line and sent to SCL line low (see Figure 66 Transfer sequencing
the shift register; then it is compared with the EV3).
address of the interface or the General Call
address (if selected by software). When the acknowledge pulse is received:
Note: In 10-bit addressing mode, the comparison – The EVF and BTF bits are set by hardware with
includes the header sequence (11110xx0) and the an interrupt if the ITE bit is set.
two most significant bits of the address. Closing slave communication
Header matched (10-bit mode only): the interface After the last data byte is transferred a Stop Con-
generates an acknowledge pulse if the ACK bit is dition is generated by the master. The interface
set. detects this condition and sets:
Address not matched: the interface ignores it – EVF and STOPF bits with an interrupt if the ITE
and waits for another Start condition. bit is set.
Address matched: the interface generates in se- Then the interface waits for a read of the SR2 reg-
quence: ister (see Figure 66 Transfer sequencing EV4).
– Acknowledge pulse if the ACK bit is set. Error Cases
– EVF and ADSL bits are set with an interrupt if the – BERR: Detection of a Stop or a Start condition
ITE bit is set. during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
Then the interface waits for a read of the SR1 reg- bit is set.
ister, holding the SCL line low (see Figure 66 If it is a Stop then the interface discards the data,
Transfer sequencing EV1). released the lines and waits for another Start
Next, in 7-bit mode read the DR register to deter- condition.
mine from the least significant bit (Data Direction If it is a Start then the interface discards the data
Bit) if the slave must enter Receiver or Transmitter and waits for the next slave address on the bus.
mode.
– AF: Detection of a non-acknowledge bit. In this
In 10-bit mode, after receiving the address se- case, the EVF and AF bits are set with an inter-
quence the slave is always in receive mode. It will rupt if the ITE bit is set.
enter transmit mode on receiving a repeated Start The AF bit is cleared by reading the I2CSR2 reg-
condition followed by the header sequence with ister. However, if read before the completion of
matching address bits and the least significant bit the transmission, the AF flag will be set again,
set (11110xx1). thus possibly generating a new interrupt. Soft-
Slave Receiver ware must ensure either that the SCL line is back
Following the address reception and after SR1 at 0 before reading the SR2 register, or be able
register has been read, the slave receives bytes to correctly handle a second interrupt during the
from the SDA line into the DR register via the inter- 9th pulse of a transmitted byte.
nal shift register. After each byte the interface gen- Note: In case of errors, SCL line is not held low;
erates in sequence: however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line
– Acknowledge pulse if the ACK bit is set
may be held low due to SB or BTF flags that are
– EVF and BTF bits are set with an interrupt if the set at the same time. It is then necessary to re-
ITE bit is set. lease both lines by software.

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I2C INTERFACE (Cont’d)

How to release the SDA / SCL lines Then the second address byte is sent by the inter-
Set and subsequently clear the STOP bit while face.
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte. After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
SMBus Compatibility – The EVF bit is set by hardware with interrupt
ST7 I2C is compatible with SMBus V1.1 protocol. It generation if the ITE bit is set.
supports all SMBus adressing modes, SMBus bus Then the master waits for a read of the SR1 regis-
protocols and CRC-8 packet error checking. Refer ter followed by a write in the CR register (for exam-
to AN1713: SMBus Slave Driver For ST7 I2C Pe- ple set PE bit), holding the SCL line low (see Fig-
ripheral. ure 66 Transfer sequencing EV6).

10.7.4.2 Master Mode Next the master must enter Receiver or Transmit-
To switch from default Slave mode to Master ter mode.
mode a Start condition generation is needed. Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
Start condition sequence with the least significant bit set
Setting the START bit while the BUSY bit is (11110xx1).
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion. Master Receiver
Once the Start condition is sent: Following the address transmission and after SR1
and CR registers have been accessed, the master
– The EVF and SB bits are set by hardware with receives bytes from the SDA line into the DR reg-
an interrupt if the ITE bit is set. ister via the internal shift register. After each byte
Then the master waits for a read of the SR1 regis- the interface generates in sequence:
ter followed by a write in the DR register with the – Acknowledge pulse if the ACK bit is set
Slave address, holding the SCL line low (see
Figure 66 Transfer sequencing EV5). – EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 reg-
Slave address transmission ister followed by a read of the DR register, holding
Then the slave address is sent to the SDA line via the SCL line low (see Figure 66 Transfer se-
the internal shift register. quencing EV7).
In 7-bit addressing mode, one address byte is To close the communication: before reading the
sent. last byte from the DR register, set the STOP bit to
In 10-bit addressing mode, sending the first byte generate the Stop condition. The interface goes
including the header sequence causes the follow- automatically back to slave mode (M/SL bit
ing event: cleared).
– The EVF bit is set by hardware with interrupt Note: In order to generate the non-acknowledge
generation if the ITE bit is set. pulse after the last received data byte, the ACK bit
Then the master waits for a read of the SR1 regis- must be cleared just before reading the second
ter followed by a write in the DR register, holding last data byte.
the SCL line low (see Figure 66 Transfer se-
quencing EV9).

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I2C BUS INTERFACE (Cont’d)

Master Transmitter of communication gives the possibility to reiniti-
Following the address transmission and after SR1 ate transmission.
register has been read, the master sends bytes Multimaster Mode
from the DR register to the SDA line via the inter- Normally the BERR bit would be set whenever
nal shift register. unauthorized transmission takes place while
transfer is already in progress. However, an is-
The master waits for a read of the SR1 register fol- sue will arise if an external master generates an
lowed by a write in the DR register, holding the unauthorized Start or Stop while the I2C master
SCL line low (see Figure 66 Transfer sequencing is on the first or second pulse of a 9-bit transac-
EV8). tion. It is possible to work around this by polling
When the acknowledge bit is received, the the BUSY bit during I2C master mode transmis-
interface sets: sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
– EVF and BTF bits with an interrupt if the ITE bit
being set.
is set.
To close the communication: after writing the last – AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
byte to the DR register, set the STOP bit to gener-
with an interrupt if the ITE bit is set. To resume,
ate the Stop condition. The interface goes auto-
set the Start or Stop bit.
matically back to slave mode (M/SL bit cleared).
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
Error Cases the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
– BERR: Detection of a Stop or a Start condition ware must ensure either that the SCL line is back
during a byte transfer. In this case, the EVF and at 0 before reading the SR2 register, or be able
BERR bits are set by hardware with an interrupt to correctly handle a second interrupt during the
if ITE is set. 9th pulse of a transmitted byte.
Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9- – ARLO: Detection of an arbitration lost condition.
bit transaction: In this case the ARLO bit is set by hardware (with
Single Master Mode an interrupt if the ITE bit is set and the interface
If a Start or Stop is issued during the first or sec- goes automatically back to slave mode (the M/SL
ond pulse of a 9-bit transaction, the BERR flag bit is cleared).
will not be set and transfer will continue however Note: In all these cases, the SCL line is not held
the BUSY flag will be reset. To work around this, low; however, the SDA line can remain low due to
slave devices should issue a NACK when they possible «0» bits transmitted last. It is then neces-
receive a misplaced Start or Stop. The reception sary to release both lines by software.
of a NACK or BUSY by the master in the middle

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I2C BUS INTERFACE (Cont’d)

Figure 66. Transfer Sequencing
7-bit Slave receiver:
S Address A Data1 A Data2 A DataN A P
.....
EV1 EV2 EV2 EV2 EV4

7-bit Slave transmitter:

S Address A Data1 A Data2 A DataN NA P
.....
EV1 EV3 EV3 EV3 EV3-1 EV4

7-bit Master receiver:

S Address A Data1 A Data2 A DataN NA P
.....
EV5 EV6 EV7 EV7 EV7

7-bit Master transmitter:

S Address A Data1 A Data2 A DataN A P
.....
EV5 EV6 EV8 EV8 EV8 EV8

10-bit Slave receiver:

S Header A Address A Data1 A DataN A P
.....
EV1 EV2 EV2 EV4

10-bit Slave transmitter:

Sr Header A Data1 A .... DataN A P
EV1 EV3 EV3 . EV3-1 EV4

10-bit Master transmitter

S Header A Address A Data1 A DataN A P
.....
EV5 EV9 EV6 EV8 EV8 EV8

10-bit Master receiver:

Sr Header A Data1 A DataN A P
.....
EV5 EV6 EV7 EV7

Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

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I2C BUS INTERFACE (Cont’d)

10.7.5 Low Power Modes
Mode Description
No effect on I2C interface.
WAIT
I2C interrupts cause the device to exit from WAIT mode.
I2C registers are frozen.
HALT In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

10.7.6 Interrupts
Figure 67. Event Flags and Interrupt Generation

ADD10 ITE
BTF
ADSL
SB INTERRUPT
AF
STOPF
ARLO EVF
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.

Enable Exit Exit

Event
Interrupt Event Control from from
Flag
Bit Wait Halt
10-bit Address Sent Event (Master mode) ADD10 Yes No
End of Byte Transfer Event BTF Yes No
Address Matched Event (Slave mode) ADSEL Yes No
Start Bit Generation Event (Master mode) SB Yes No
ITE
Acknowledge Failure Event AF Yes No
Stop Detection Event (Slave mode) STOPF Yes No
Arbitration Lost Event (Multimaster configuration) ARLO Yes No
Bus Error Event BERR Yes No

Note: The I2C interrupt events are connected to

the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).

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I2C BUS INTERFACE (Cont’d)

10.7.7 Register Description – In slave mode:
I2C CONTROL REGISTER (CR) 0: No start generation
Read / Write 1: Start generation when the bus is free
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
7 0 This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
0 0 PE ENGC START ACK STOP ITE bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable. Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. This bit is set and cleared by software. It is also
0: Peripheral disabled cleared by hardware in master mode. Note: This
1: Master/Slave capability bit is not cleared when the interface is disabled
Notes: (PE=0).
– When PE=0, all the bits of the CR register and – In master mode:
the SR register except the Stop bit are reset. All 0: No stop generation
outputs are released while PE=0 1: Stop generation after the current byte transfer
– When PE=1, the corresponding I/O pins are se- or after the current Start condition is sent. The
lected by hardware as alternate functions. STOP bit is cleared by hardware when the Stop
– To enable the I2C interface, write the CR register condition is sent.
TWICE with PE=1 as the first write only activates – In slave mode:
the interface (only PE is set).
0: No stop generation
1: Release the SCL and SDA lines after the cur-
Bit 4 = ENGC Enable General Call. rent byte transfer (BTF=1). In this mode the
This bit is set and cleared by software. It is also STOP bit has to be cleared by software.
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac- Bit 0 = ITE Interrupt enable.
knowledged (01h ignored). This bit is set and cleared by software and cleared
0: General Call disabled
by hardware when the interface is disabled
1: General Call enabled (PE=0).
0: Interrupts disabled
Note: In accordance with the I2C standard, when
1: Interrupts enabled
GCAL addressing is enabled, an I2C slave can Refer to Figure 67 for the relationship between the
only receive data. It will not transmit data to the events and the interrupt.
master. SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 66) is de-
Bit 3 = START Generation of a Start condition. tected.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation

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I2C BUS INTERFACE (Cont’d)

I2C STATUS REGISTER 1 (SR1) 1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h) Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
7 0
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
EVF ADD10 TRA BUSY BTF ADSL M/SL SB progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
Bit 7 = EVF Event flag. 0: No communication on the bus
This bit is set by hardware as soon as an event oc- 1: Communication ongoing on the bus
curs. It is cleared by software reading SR2 register Note:
in case of error event or as described in Figure 66. – The BUSY flag is NOT updated when the inter-
It is also cleared by hardware when the interface is face is disabled (PE=0). This can have conse-
disabled (PE=0). quences when operating in Multimaster mode;
0: No event i.e. a second active I2C master commencing a
1: One of the following events has occurred: transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
– BTF=1 (Byte received or transmitted) consists of checking that the I2C is not busy be-
– ADSL=1 (Address matched in Slave mode fore enabling the I2C Multimaster cell.
while ACK=1)
– SB=1 (Start condition generated in Master Bit 3 = BTF Byte transfer finished.
mode) This bit is set by hardware as soon as a byte is cor-
– AF=1 (No acknowledge received after byte rectly received or transmitted with interrupt gener-
transmission) ation if ITE=1. It is cleared by software reading
– STOPF=1 (Stop condition detected in Slave SR1 register followed by a read or write of DR reg-
mode) ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– ARLO=1 (Arbitration lost in Master mode)
– Following a byte transmission, this bit is set after
– BERR=1 (Bus error, misplaced Start or Stop reception of the acknowledge clock pulse. In
condition detected) case an address byte is sent, this bit is set only
– ADD10=1 (Master has sent header byte) after the EV6 event (See Figure 66). BTF is
– Address byte successfully transmitted in Mas- cleared by reading SR1 register followed by writ-
ter mode. ing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
Bit 6 = ADD10 10-bit addressing in Master mode. ACK=1. BTF is cleared by reading SR1 register
This bit is set by hardware when the master has followed by reading the byte from DR register.
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed The SCL line is held low while BTF=1.
by a write in the DR register of the second address 0: Byte transfer not done
byte. It is also cleared by hardware when the pe- 1: Byte transfer succeeded
ripheral is disabled (PE=0).
0: No ADD10 event occurred. Bit 2 = ADSL Address matched (Slave mode).
1: Master has sent first address byte (header) This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
Bit 5 = TRA Transmitter/Receiver. tent or a general call is recognized. An interrupt is
When BTF is set, TRA=1 if a data byte has been generated if ITE=1. It is cleared by software read-
transmitted. It is cleared automatically when BTF ing SR1 register or by hardware when the inter-
is cleared. It is also cleared by hardware after de- face is disabled (PE=0).
tection of Stop condition (STOPF=1), loss of bus The SCL line is held low while ADSL=1.
arbitration (ARLO=1) or when the interface is disa- 0: Address mismatched or not received
bled (PE=0). 1: Received address matched
0: Data byte received (if BTF=1)

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I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave. The SCL line is not held low while STOPF=1.
This bit is set by hardware as soon as the interface 0: No Stop condition detected
is in Master mode (writing START=1). It is cleared 1: Stop condition detected
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0). Bit 2 = ARLO Arbitration lost.
0: Slave mode This bit is set by hardware when the interface los-
1: Master mode es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
Bit 0 = SB Start bit (Master mode). the interface is disabled (PE=0).
This bit is set by hardware as soon as the Start
condition is generated (following a write After an ARLO event the interface switches back
START=1). An interrupt is generated if ITE=1. It is automatically to Slave mode (M/SL=0).
cleared by software reading SR1 register followed The SCL line is not held low while ARLO=1.
by writing the address byte in DR register. It is also 0: No arbitration lost detected
cleared by hardware when the interface is disa-
1: Arbitration lost detected
bled (PE=0).
Note:
0: No Start condition
– In a Multimaster environment, when the interface
1: Start condition generated is configured in Master Receive mode it does not
perform arbitration during the reception of the
I2C STATUS REGISTER 2 (SR2) Acknowledge Bit. Mishandling of the ARLO bit
Read Only from the I2CSR2 register may occur when a sec-
Reset Value: 0000 0000 (00h) ond master simultaneously requests the same
data from the same slave and the I2C master
7 0
does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.
0 0 0 AF STOPF ARLO BERR GCAL

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface de-
Bit 7:5 = Reserved. Forced to 0 by hardware. tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
Bit 4 = AF Acknowledge failure.
terface is disabled (PE=0).
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is The SCL line is not held low while BERR=1.
cleared by software reading SR2 register or by 0: No misplaced Start or Stop condition
hardware when the interface is disabled (PE=0). 1: Misplaced Start or Stop condition
The SCL line is not held low while AF=1 but by oth- Note:
er flags (SB or BTF) that are set at the same time. – If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to
0: No acknowledge failure re-synchronize communication, get the transmis-
1: Acknowledge failure sion acknowledged and the bus released for fur-
Note: ther communication
– When an AF event occurs, the SCL line is not
held low; however, the SDA line can remain low
if the last bits transmitted are all 0. It is then nec- Bit 0 = GCAL General Call (Slave mode).
essary to release both lines by software. This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
Bit 3 = STOPF Stop detection (Slave mode). (STOPF=1) or when the interface is disabled
This bit is set by hardware when a Stop condition (PE=0).
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is 0: No general call address detected on bus
cleared by software reading SR2 register or by 1: general call address detected on bus
hardware when the interface is disabled (PE=0).

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I2C BUS INTERFACE (Cont’d)

I2C CLOCK CONTROL REGISTER (CCR) I2C DATA REGISTER (DR)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = FM/SM Fast/Standard I2C mode.

This bit is set and cleared by software. It is not Bit 7:0 = D[7:0] 8-bit Data Register.
cleared when the interface is disabled (PE=0). These bits contain the byte to be received or trans-
0: Standard I2C mode mitted on the bus.
1: Fast I2C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
Bit 6:0 = CC[6:0] 7-bit clock divider. ister.
These bits select the speed of the bus (FSCL) de- – Receiver mode: the first data byte is received au-
pending on the I2C mode. They are not cleared tomatically in the DR register using the least sig-
when the interface is disabled (PE=0). nificant bit of the address.
Refer to the Electrical Characteristics section for Then, the following data bytes are received one
the table of values. by one after reading the DR register.
Note: The programmed FSCL assumes no load on
SCL and SDA lines.

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I2C BUS INTERFACE (Cont’d)

I2C OWN ADDRESS REGISTER (OAR1) I2C OWN ADDRESS REGISTER (OAR2)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0100 0000 (40h)
7 0 7 0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 FR1 FR0 0 0 0 ADD9 ADD8 0

7-bit Addressing Mode Bit 7:6 = FR[1:0] Frequency bits.

Bit 7:1 = ADD[7:1] Interface address. These bits are set by software only when the inter-
These bits define the I2C bus address of the inter- face is disabled (PE=0). To configure the interface
face. They are not cleared when the interface is to I2C specified delays select the value corre-
disabled (PE=0). sponding to the microcontroller frequency FCPU.
fCPU FR1 FR0
Bit 0 = ADD0 Address direction bit. < 6 MHz 0 0
This bit is don’t care, the interface acknowledges 6 to 8 MHz 0 1
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored. Bit 5:3 = Reserved

10-bit Addressing Mode Bit 2:1 = ADD[9:8] Interface address.

Bit 7:0 = ADD[7:0] Interface address. These are the most significant bits of the I2C bus
These are the least significant bits of the I2C bus address of the interface (10-bit mode only). They
address of the interface. They are not cleared are not cleared when the interface is disabled
when the interface is disabled (PE=0). (PE=0).

Bit 0 = Reserved.

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I²C BUS INTERFACE (Cont’d)

Table 23. I2C Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

I2CCR PE ENGC START ACK STOP ITE

0018h
Reset Value 0 0 0 0 0 0 0 0
I2CSR1 EVF ADD10 TRA BUSY BTF ADSL M/SL SB
0019h
Reset Value 0 0 0 0 0 0 0 0
I2CSR2 AF STOPF ARLO BERR GCAL
001Ah
Reset Value 0 0 0 0 0 0 0 0
I2CCCR FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
001Bh
Reset Value 0 0 0 0 0 0 0 0
I2COAR1 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
001Ch
Reset Value 0 0 0 0 0 0 0 0
I2COAR2 FR1 FR0 ADD9 ADD8
001Dh
Reset Value 0 1 0 0 0 0 0 0
I2CDR MSB LSB
001Eh
Reset Value 0 0 0 0 0 0 0 0

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10.8 CONTROLLER AREA NETWORK (CAN)

10.8.1 Introduction are checked for correctness and acknowledged

This peripheral is designed to support serial data accordingly although such frames cannot be trans-
exchanges using a multi-master contention based mitted nor received. The same applies to overload
priority scheme as described in CAN specification frames which are recognized but never initiated.
Rev. 2.0 part A. It can also be connected to a 2.0 B
network without problems, since extended frames
Figure 68. CAN Block Diagram

ST7 Internal Bus

ST7 Interface

TX/RX TX/RX TX/RX ID ID PSR

Buffer 1 Buffer 2 Buffer 3 Filter 0 Filter 1

10 Bytes 10 Bytes 10 Bytes 4 Bytes 4 Bytes

BRPR

BTR

ICR
RX BTL BCDL SHREG

ISR
TX EML CRC

CSR

TECR
CAN 2.0B passive Core

RECR

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CONTROLLER AREA NETWORK (Cont’d)

10.8.2 Main Features The acknowledgement (ACK) field comprises the
– Support of CAN specification 2.0A and 2.0B pas- ACK slot and the ACK delimiter. The bit in the ACK
sive slot is placed on the bus by the transmitter as a re-
cessive bit (logical 1). It is overwritten as a domi-
– Three prioritized 10-byte Transmit/Receive mes- nant bit (logical 0) by those receivers which have
sage buffers at this time received the data correctly. In this way,
– Two programmable global 12-bit message ac- the transmitting node can be assured that at least
ceptance filters one receiver has correctly received its message.
– Programmable baud rates up to 1 MBit/s Note that messages are acknowledged by the re-
ceivers regardless of the outcome of the accept-
– Buffer flip-flopping capability in transmission ance test.
– Maskable interrupts for transmit, receive (one The end of the message is indicated by the End Of
per buffer), error and wake-up Frame (EOF). The intermission field defines the
– Automatic low-power mode after 20 recessive minimum number of bit periods separating con-
bits or on demand (standby mode) secutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
– Interrupt-driven wake-up from standby mode
upon reception of dominant pulse 10.8.3.2 Hardware Blocks
– Optional dominant pulse transmission on leaving The CAN controller contains the following func-
standby mode tional blocks (refer to Figure 68):
– Automatic message queuing for transmission – ST7 Interface: buffering of the ST7 internal bus
upon writing of data byte 7 and address decoding of the CAN registers.
– Programmable loop-back mode for self-test op- – TX/RX Buffers: three 10-byte buffers for trans-
eration mission and reception of maximum length mes-
sages.
– Advanced error detection and diagnosis func-
tions – ID Filters: two 12-bit compare and don’t care
masks for message acceptance filtering.
– Software-efficient buffer mapping at a unique ad-
dress space – PSR: page selection register (see memory map).
– Scalable architecture. – BRPR: clock divider for different data rates.
– BTR: bit timing register.
10.8.3 Functional Description
– ICR: interrupt control register.
10.8.3.1 Frame Formats
– ISR: interrupt status register.
A summary of all the CAN frame formats is given
in Figure 69 for reference. It covers only the stand- – CSR: general purpose control/status register.
ard frame format since the extended one is only – TECR: transmit error counter register.
acknowledged. – RECR: receive error counter register.
A message begins with a start bit called Start Of – BTL: bit timing logic providing programmable bit
Frame (SOF). This bit is followed by the arbitration sampling and bit clock generation for synchroni-
field which contains the 11-bit identifier (ID) and zation of the controller.
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is a data frame or a re- – BCDL: bit coding logic generating a NRZ-coded
mote request frame. A remote request frame does datastream with stuff bits.
not have any data byte. – SHREG: 8-bit shift register for serialization of
The control field contains the Identifier Extension data to be transmitted and parallelisation of re-
bit (IDE), which indicates standard or extended ceived data.
format, a reserved bit (ro) and, in the last four bits, – CRC: 15-bit CRC calculator and checker.
a count of the data bytes (DLC). The data field – EML: error detection and management logic.
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a – CAN Core: CAN 2.0B passive protocol control-
frame integrity check for detecting bit errors. ler.

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 ST72F521, ST72521B

CONTROLLER AREA NETWORK (Cont’d)

Figure 69. CAN Frames

Inter-Frame Space
Inter-Frame Space Data Frame or Overload Frame
44 + 8 * N

Arbitration Field Control Field Data Field CRC Field Ack Field
2
12 6 8*N 16 7

ID DLC CRC EOF

RTR
IDE
r0
SOF

ACK
Inter-Frame Space
Inter-Frame Space Remote Frame or Overload Frame
44

Arbitration Field Control Field CRC Field Ack Field End Of Frame
2
12 6 16 7

ID DLC CRC
IDE
r0
RTR
SOF

ACK

Data Frame or Inter-Frame Space

Remote Frame Error Frame or Overload Frame

Error Flag Flag Echo Error Delimiter

6 ≤6 8

Data Frame or Notes:

Any Frame Inter-Frame Space Remote Frame •0 <= N <= 8
• SOF = Start Of Frame
Suspend • ID = Identifier
Intermission Transmission Bus Idle
3 • RTR = Remote Transmission Request
8
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
End Of Frame or • DLC = Data Length Code
Error Delimiter or Inter-Frame Space • CRC = Cyclic Redundancy Code
Overload Delimiter Overload Frame or Error Frame • Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
Overload Flag Overload Delimiter • Suspend transmission: applies to error
6 8 passive nodes only.
• EOF = End of Frame
• ACK = Acknowledge bit

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CONTROLLER AREA NETWORK (Cont’d)

10.8.3.3 Modes of Operation bit. If the WKPS bit is set in the CSR register,
The CAN Core unit assumes one of the seven then the controller passes through WAKE-UP
states described below: otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
– STANDBY. Standby mode is entered either on a nism is software-driven and therefore carries a
chip reset or on resetting the RUN bit in the Con- significant time overhead. All messages received
trol/Status Register (CSR). Any on-going trans- after the wake-up bit and before the controller is
mission or reception operation is not interrupted set to run and has completed synchronization
and completes normally before the Bit Time Log- are ignored.
ic and the clock prescaler are turned off for mini-
mum power consumption. This state is signalled Note: Standby mode is not entered on resetting
by the RUN bit being read-back as 0. the RUN bit in the Control/Status register (CSR) if
Once in standby, the only event monitored is the the CANRX pin is shorted to GND.
reception of a dominant bit which causes a wake- – WAKE-UP. The CAN bus line is forced to domi-
up interrupt if the SCIE bit of the Interrupt Control nant for one bit time signalling the wake-up con-
Register (ICR) is set. dition to all other bus members.
The STANDBY mode is left by setting the RUN
Figure 70. CAN Controller State Diagram
ARESET

RUN & WKPS

STANDBY

RUN RUN & WKPS WAKE-UP

RESYNC

FSYN & BOFF & 11 Recessive bits |

(FSYN | BOFF) & 128 * 11 Recessive bits

RUN
IDLE

Write to DATA7 |
TX Error & NRTX Start Of Frame

TX OK RX OK

Arbitration lost
TRANSMISSION RECEPTION

TX Error RX Error

BOFF
ERROR
BOFF
n

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– RESYNC. The resynchronization mode is used allows transmitted messages to be simultane-
to find the correct entry point for starting trans- ously received when they pass the acceptance
mission or reception after the node has gone filtering. This is particularly useful for checking
asynchronous either by going into the STANDBY the integrity of the communication path.
or bus-off states. RECEPTION. Once the CAN controller has syn-
Resynchronization is achieved when 128 se- chronized itself onto the bus activity, it is ready
quences of 11 recessive bits have been moni- for reception of new messages. Every incoming
tored unless the node is not bus-off and the message gets its identifier compared to the ac-
FSYN bit in the CSR register is set in which case ceptance filters. If the bitwise comparison of the
a single sequence of 11 recessive bits needs to selected bits ends up with a match for at least
be monitored. one of the filters then that message is elected for
– IDLE. The CAN controller looks for one of the fol- reception and a target buffer is searched for. This
lowing events: the RUN bit is reset, a Start Of buffer will be the first one - order is 1 to 3 - that
Frame appears on the CAN bus or the DATA7 has the LOCK and RDY bits of its BCSRx regis-
register of the currently active page is written to. ter reset.
– TRANSMISSION. Once the LOCK bit of a Buffer – When no such buffer exists then an overrun
interrupt is generated if the ORIE bit of the ICR
Control/Status Register (BCSRx) has been set register has been set. In this case the identifi-
and read back as such, a transmit job can be er of the last message is made available in the
submitted by writing to the DATA7 register. The Last Identifier Register (LIDHR and LIDLR) at
message with the highest priority will be transmit- least until it gets overwritten by a new identifi-
ted as soon as the CAN bus becomes idle. er picked-up from the bus.
Among those messages with a pending trans- – When a buffer does exist, the accepted mes-
mission request, the highest priority is given to sage gets written into it, the ACC bit in the
BCSRx register gets the number of the match-
Buffer 3 then 2 and 1. If the transmission fails due ing filter, the RDY and RXIF bits get set and an
to a lost arbitration or to an error while the NRTX interrupt is generated if the RXIE bit in the ISR
bit of the CSR register is reset, then a new trans- register is set.
mission attempt is performed. This goes on until Up to three messages can be automatically
the transmission ends successfully or until the received without intervention from the CPU
job is cancelled by unlocking the buffer, by set- because each buffer has its own set of status
ting the NRTX bit or if the node ever enters bus- bits, greatly reducing the reactiveness require-
off or if a higher priority message becomes pend- ments in the processing of the receive inter-
ing. The RDY bit in the BCSRx register, which rupts.
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successful-
ly then the TXIF bit in the Interrupt Status Regis-
ter (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
Note 1: Setting the SRTE bit of the CSR register

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– ERROR. The error management as described in cation to determine the stability of the network.
the CAN protocol is completely handled by hard- Moreover, as one of the node status bits (EPSV
ware using 2 error counters which get increment- or BOFF of the CSR register) changes, an inter-
ed or decremented according to the error rupt is generated if the SCIE bit is set in the ICR
condition. Both of them may be read by the appli- Register. Refer to Figure 71.
Figure 71. CAN Error State Diagram

When TECR or RECR > 127, the EPSV bit gets set

ERROR ACTIVE
ERROR PASSIVE

When TECR and RECR < 128,

the EPSV bit gets cleared

When 128 * 11 recessive bits occur: When TECR > 255 the BOFF bit gets set
- the BOFF bit gets cleared and the EPSV bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared

BUS OFF

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10.8.3.4 Bit Timing Logic – Resynchronization Jump Width (RJW): de-
The bit timing logic monitors the serial bus-line and fines an upper bound to the amount of lengthen-
performs sampling and adjustment of the sample ing or shortening of the bit segments. It is
point by synchronizing on the start-bit edge and re- programmable between 1 and 4 time quanta.
synchronizing on following edges. To guarantee the correct behaviour of the CAN
Its operation may be explained simply when the controller, SYNC_SEG + BS1 + BS2 must be
nominal bit time is divided into three segments as greater than or equal to 5 time quanta.
follows: The CAN controller resynchronizes on recessive
– Synchronisation segment (SYNC_SEG): a bit to dominant edges only.
change is expected to lie within this time seg- For a detailed description of the CAN resynchroni-
ment. It has a fixed length of one time quanta (1 zation mechanism and other bit timing configura-
x tCAN). tion constraints, please refer to the Bosch CAN
– Bit segment 1 (BS1): defines the location of the standard 2.0.
sample point. It includes the PROP_SEG and As a safeguard against programming errors, the
PHASE_SEG1 of the CAN standard. Its duration configuration of the Bit Timing Register (BTR) is
is programmable between 1 and 16 time quanta only possible while the device is in STANDBY
but may be automatically lengthened to compen- mode.
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
Figure 72. Bit Timing

NOMINAL BIT TIME

SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2)

1 x tCAN tBS1 tBS2

SAMPLE POINT TRANSMIT POINT

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10.8.4 Register Description Bit 4 = TXIF Transmit Interrupt Flag
The CAN registers are organized as 6 general pur-
− Read/Clear
Set by hardware to signal that the highest priority
pose registers plus 5 pages of 16 registers span- message queued for transmission has been suc-
ning the same address space and primarily used cessfully transmitted.
for message and filter storage. The page actually Cleared by software.
selected is defined by the content of the Page Se-
Bit 3 = SCIF Status Change Interrupt Flag
lection Register.
− Read/Clear
10.8.4.1 General Purpose Registers Set by hardware to signal the reception of a domi-
INTERRUPT STATUS REGISTER (ISR) nant bit while in standby mode. In Run mode this bit
Read/Write is set when EPVS is set or reset (refer to Figure 71.
CAN Error State Diagram). This bit also signals any
Reset Value: 00h receive error when ESCI=1.
Cleared by software.
7 0
Bit 2 = ORIF Overrun Interrupt Flag
RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND
− Read/Clear
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3 Cleared by software.
− Read/Clear Bit 1 = TEIF Transmit Error Interrupt Flag
Set by hardware to signal that a new error-free mes- − Read/Clear
sage is available in buffer 3. Set by hardware to signal that an error occurred dur-
Cleared by software to release buffer 3. ing the transmission of the highest priority message
Also cleared by resetting bit RDY of BCSR3. queued for transmission.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2 Cleared by software.
− Read/Clear Bit 0 = EPND Error Interrupt Pending
Set by hardware to signal that a new error-free − Read Only
message is available in buffer 2. Set by hardware when at least one of the three error
Cleared by software to release buffer 2. interrupt flags SCIF, ORIF or TEIF is set.
Also cleared by resetting bit RDY of BCSR2. Reset by hardware when all error interrupt flags
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1 have been cleared.
− Read/Clear Caution:
Set by hardware to signal that a new error-free mes-
sage is available in buffer 1. Interrupt flags are reset by writing a “0” to the cor-
Cleared by software to release buffer 1. responding bit position. The appropriate way con-
Also cleared by resetting bit RDY of BCSR1. sists in writing an immediate mask or the one’s com-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modify-
write nature.

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INTERRUPT CONTROL REGISTER (ICR) whenever a message has been successfully trans-
mitted.
Read/Write Cleared by software to disable transmit interrupt
Reset Value: 00h requests.
Bit 3 = SCIE Status Change Interrupt Enable
7 0 − Read/Set/Clear
Set by software to enable an interrupt request
0 ESCI RXIE TXIE SCIE ORIE TEIE 0 whenever the node’s status changes in run mode or
whenever a dominant pulse is received in standby
Bit 7 = Reserved. mode.
Cleared by software to disable status change inter-
Bit 6 = ESCI Extended Status Change Interrupt
− Read/Set/Clear rupt requests.
Set by software to specify that SCIF is to be set on Bit 2 = ORIE Overrun Interrupt Enable
receive errors also. − Read/Set/Clear
Cleared by software to set SCIF only on status Set by software to enable an interrupt request
changes and wake-up but not on all receive errors. whenever a message should be stored and no re-
ceive buffer is avalaible.
Bit 5 = RXIE Receive Interrupt Enable
− Read/Set/Clear Cleared by software to disable overrun interrupt re-
quests.
Set by software to enable an interrupt request
whenever a message has been received free of er- Bit 1 = TEIE Transmit Error Interrupt Enable
rors. − Read/Set/Clear
Cleared by software to disable receive interrupt re- Set by software to enable an interrupt whenever an
quests. error has been detected during transmission of a
message.
Bit 4 = TXIE Transmit Interrupt Enable
− Read/Set/Clear Cleared by software to disable transmit error inter-
rupts.
Set by software to enable an interrupt request
Bit 0 = Reserved.

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CONTROLLER AREA NETWORK (Cont’d)

CONTROL/STATUS REGISTER (CSR) Bit 3 = NRTX No Retransmission
Read/Write
− Read/Set/Clear
Set by software to disable the retransmission of un-
Reset Value: 00h successful messages. It does not stop transmission
in case of Arbitration Lost.
7 0 Cleared by software to enable retransmission of
messages until success is met.
0 BOFF EPSV SRTE NRTX FSYN WKPS RUN Bit 2 = FSYN Fast Synchronization
− Read/Set/Clear
Bit 6 = BOFF Bus-Off State Set by software to enable a fast resynchronization
− Read Only when leaving standby mode, i.e. wait for only 11 re-
cessive bits in a row.
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds Cleared by software to enable the standard resyn-
255. chronization when leaving standby mode, i.e. wait
Reset by hardware to indicate that the node is in- for 128 sequences of 11 recessive bits.
volved in bus activities. Bit 1 = WKPS Wake-up Pulse
Bit 5 = EPSV Error Passive State − Read/Set/Clear
− Read Only Set by software to generate a dominant pulse when
leaving standby mode.
Set by hardware to indicate that the node is error
passive. Cleared by software for no dominant wake-up
Reset by hardware to indicate that the node is either pulse.
error active (BOFF = 0) or bus-off. Bit 0 = RUN CAN Enable
Bit 4 = SRTE Simultaneous Receive/Transmit En- − Read/Set/Clear
able − Read/Set/Clear Set by software to leave standby mode after 128 se-
Set by software to enable simultaneous transmis- quences of 11 recessive bits or just 11 recessive
sion and reception of a message passing the ac- bits if FSYN is set.
ceptance filtering. Allows to check the integrity of Cleared by software to request a switch to the
the communication path. standby or low-power mode as soon as any on-go-
Reset by software to discard all messages trans- ing transfer is complete. Read-back as 1 in the
mitted by the node. Allows remote and data frames meantime to enable proper signalling of the standby
to share the same identifier. state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.

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BAUD RATE PRESCALER REGISTER (BRPR) BIT TIMING REGISTER (BTR)
Read/Write in Standby mode Read/Write in Standby mode
Reset Value: 00h Reset Value: 23h

7 0 7 0

RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 BS22 BS21 BS20 BS13 BS12 BS11 BS10

RJW[1:0] determine the maximum number of time BS2[2:0] determine the length of Bit Segment 2.
quanta by which a bit period may be shortened or tBS2 = tCAN * (BS2 + 1)
lengthened to achieve resynchronization. BS1[3:0] determine the length of Bit Segment 1.
tRJW = tCAN * (RJW + 1) tBS1 = tCAN * (BS1 + 1)
BRP[5:0] determine the CAN system clock cycle
time or time quanta which is used to build up the in- Note: Writing to this register is allowed only in
dividual bit timing. Standby mode to prevent any accidental CAN pro-
tCAN = tCPU * (BRP + 1) tocol violation through programming errors.
Where tCPU = time period of the CPU clock.
The resulting baud rate can be computed by the for- PAGE SELECTION REGISTER (PSR)
mula:
Read/Write
Reset Value: 00h

7 0

1
BR = ---------------------------------------------------------------------------------------------------
- PAGE PAGE PAGE
t CPU × ( BRP + 1 ) × ( BS1 + BS2 + 3 ) 0 0 0 0 0
2 1 0

PAGE[2:0] determine which buffer or filter page is

mapped at addresses 0010h to 001Fh.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN pro- PAGE2 PAGE1 PAGE0 Page Title
tocol violation through programming errors.
0 0 0 Diagnosis

0 0 1 Buffer 1

0 1 0 Buffer 2

0 1 1 Buffer 3

1 0 0 Filters

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

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10.8.4.2 Paged Registers TRANSMIT ERROR COUNTER REG. (TECR)
LAST IDENTIFIER HIGH REGISTER (LIDHR) Read Only
Read/Write Reset Value: 00h
Reset Value: Undefined 7 0

7 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3

TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
LID[10:3] are the most significant 8 bits of the last fault confinement mechanism of the CAN protocol.
Identifier read on the CAN bus. In case of an error during transmission, this counter
is incremented by 8. It is decremented by 1 after
every successful transmission. When the counter
LAST IDENTIFIER LOW REGISTER (LIDLR) value exceeds 127, the CAN controller enters the
Read/Write error passive state. When a value of 256 is reached,
the CAN controller is disconnected from the bus.
Reset Value: Undefined

7 0 RECEIVE ERROR COUNTER REG. (RECR)

Page: 00h — Read Only
LDLC LDLC LDLC LDLC
LID2 LID1 LID0 LRTR
3 2 1 0 Reset Value: 00h

7 0
LID[2:0] are the least significant 3 bits of the last
Identifier read on the CAN bus. REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
LRTR is the last Remote Transmission Request bit
read on the CAN bus.
REC[7:0] is the Receive Error Counter implement-
LDLC[3:0] is the last Data Length Code read on the ing part of the fault confinement mechanism of the
CAN bus. CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.

IDENTIFIER HIGH REGISTERS (IDHRx)

Read/Write
Reset Value: Undefined

7 0

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

ID[10:3] are the most significant 8 bits of the 11-bit

message identifier.The identifier acts as the mes-
sage’s name, used for bus access arbitration and
acceptance filtering.

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CONTROLLER AREA NETWORK (Cont’d)

IDENTIFIER LOW REGISTERS (IDLRx) BUFFER CONTROL/STATUS REGs. (BCSRx)
Read/Write Read/Write
Reset Value: Undefined Reset Value: 00h

7 0 7 0

ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 0 0 0 0 ACC RDY BUSY LOCK

ID[2:0] are the least significant 3 bits of the 11-bit Bit 3 = ACC Acceptance Code
message identifier. − Read Only
Set by hardware with the id of the highest priority
RTR is the Remote Transmission Request bit. It is filter which accepted the message stored in the
set to indicate a remote frame and reset to indicate buffer.
a data frame. ACC = 0: Match for Filter/Mask0. Possible match
DLC[3:0] is the Data Length Code. It gives the for Filter/Mask1.
number of bytes in the data field of the mes- ACC = 1: No match for Filter/Mask0 and match for
sage.The valid range is 0 to 8. Filter/Mask1.
Reset by hardware when either RDY or RXIF gets
DATA REGISTERS (DATA0-7x) reset.
Bit 2 = RDY Message Ready
Read/Write − Read/Clear
Reset Value: Undefined Set by hardware to signal that a new error-free
message is available (LOCK = 0) or that a trans-
7 0 mission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release
DATA DATA DATA DATA DATA DATA DATA DATA the buffer and to clear the corresponding RXIF bit
7 6 5 4 3 2 1 0 in the Interrupt Status Register.
Cleared by hardware when LOCK = 1 to indicate
that the transmission request has been serviced or
DATA[7:0] is a message data byte. Up to eight such cancelled.
bytes may be part of a message. Writing to byte
Bit 1 = BUSY Busy Buffer
DATA7 initiates a transmit request and should al-
ways be done even when DATA7 is not part of the
− Read Only
Set by hardware when the buffer is being filled
message.
(LOCK = 0) or emptied (LOCK = 1) and reset after
the 2nd intermission bit.
Reset by hardware when the buffer is not ac-
cessed by the CAN core for transmission nor re-
ception purposes.
Bit 0 = LOCK Lock Buffer
− Read/Set/Clear
Set by software to lock a buffer. No more message
can be received into the buffer thus preserving its
content and making it available for transmission.
Cleared by software to make the buffer available
for reception. Cancels any pending transmission
request.
Cleared by hardware once a message has been
successfully transmitted provided the early trans-
mit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corrup-
tion or loss of context, LOCK cannot be set nor re-
set while BUSY is set. Trying to do so will result in
LOCK not changing state.

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FILTER HIGH REGISTERS (FHRx) MASK HIGH REGISTERS (MHRx)
Read/Write Read/Write
Reset Value: Undefined Reset Value: Undefined

7 0 7 0

FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 FlL4 MSK1 MSK1
MSK9 MSK8 MSK7 MSK6 MSK5 MSK4
1 0

FIL[11:3] are the most significant 8 bits of a 12-bit

message filter. The acceptance filter is compared MSK[11:3] are the most significant 8 bits of a 12-
bit by bit with the identifier and the RTR bit of the bit message mask. The acceptance mask defines
incoming message. If there is a match for the set which bits of the acceptance filter should match
of bits specified by the acceptance mask then the the identifier and the RTR bit of the incoming mes-
message is stored in a receive buffer. sage.
MSKi = 0: don’t care.
MSKi = 1: match required.
FILTER LOW REGISTERS (FLRx)
Read/Write
MASK LOW REGISTERS (MLRx)
Reset Value: Undefined
Read/Write
7 0 Reset Value: Undefined

FIL3 FIL2 FIL1 FIL0 0 0 0 0 7 0

MSK3 MSK2 MSK1 MSK0 0 0 0 0

FIL[3:0] are the least significant 4 bits of a 12-bit
message filter.
MSK[3:0] are the least significant 4 bits of a 12-bit
message mask.

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CONTROLLER AREA NETWORK (Cont’d)

Figure 73. CAN Register Map

5Ah Interrupt Status

5Bh Interrupt Control

5Ch Control/Status

5Dh Baud Rate Prescaler

5Eh Bit Timing

5Fh Page Selection

60h
Paged Reg1
Paged Reg1
Paged
Paged
Paged Reg2Reg1Reg0
Paged
Paged Reg2Reg1
Paged
Paged
Paged Reg3Reg2Reg1
Paged
Paged Reg3Reg2
Paged
Paged
Paged Reg4Reg3Reg2
Paged
Paged Reg4Reg3
Reg5Reg4Reg3
Paged
Paged
Paged
Paged
Paged Reg5Reg4
Paged
Paged
Paged Reg6Reg5Reg4
Paged
Paged Reg6Reg5
Paged
Paged
Paged Reg7Reg6Reg5
Paged
Paged Reg7Reg6
Paged
Paged
Paged Reg8Reg7Reg6
Paged
Paged Reg8Reg7
Paged
Paged
Paged Reg9Reg8Reg7
Paged
Paged Reg9Reg8
Paged
Paged
Paged Reg10Reg9Reg8
Paged
Paged Reg10Reg9
Paged Paged
Paged Reg10
Reg11 Reg9
Paged
Paged Reg10
Reg11
Paged Paged
Paged Reg10
Reg11
Reg12
Paged
Paged Reg11
Reg12
Paged Paged
Paged Reg11
Reg12
Reg13
Paged
Paged Reg12
Reg13
Paged Paged
Paged Reg12
Reg13
Reg14
Paged
Paged Reg13
Reg14
6Fh Paged Paged
Paged Reg13
Reg14
Reg15
Paged
Paged Reg14
Reg15
Paged
Paged Reg14
Reg15
Paged Reg15
Paged Reg15

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CONTROLLER AREA NETWORK (Cont’d)

Figure 74. Page Maps

PAGE 0 PAGE 1 PAGE 2 PAGE 3 PAGE 4

60h LIDHR IDHR1 IDHR2 IDHR3 FHR0

61h LIDLR IDLR1 IDLR2 IDLR3 FLR0

62h DATA01 DATA02 DATA03 MHR0

63h DATA11 DATA12 DATA13 MLR0

64h DATA21 DATA22 DATA23 FHR1

65h DATA31 DATA32 DATA33 FLR1

66h DATA41 DATA42 DATA43 MHR1

67h DATA51 DATA52 DATA53 MLR1

Reserved
68h DATA61 DATA62 DATA63

69h DATA71 DATA72 DATA73

6Ah

6Bh
Reserved
6Ch Reserved Reserved Reserved

6Dh

6Eh TECR

6Fh RECR BCSR1 BCSR2 BCSR3

Diagnosis Buffer 1 Buffer 2 Buffer 3 Acceptance Filters

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Table 24. CAN Register Map and Reset Values
Address Register
Page 7 6 5 4 3 2 1 0
(Hex.) Label
CANISR RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND
5A
Reset Value 0 0 0 0 0 0 0 0
CANICR ESCI RXIE TXIE SCIE ORIE TEIE ETX
5B
Reset Value 0 0 0 0 0 0 0 0
CANCSR BOFF EPSV SRTE NRTX FSYN WKPS RUN
5C
Reset Value 0 0 0 0 0 0 0 0
CANBRPR RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
5D
Reset Value 0 0 0 0 0 0 0 0
CANBTR BS22 BS21 BS20 BS13 BS12 BS11 BS10
5E
Reset Value 0 0 1 0 0 0 1 1
CANPSR PAGE2 PAGE1 PAGE0
5F
Reset Value 0 0 0 0 0 0 0 0
CANLIDHR LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3
0
Reset Value x x x x x x x x
60
CANIDHRx ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
1 to 3
Reset Value x x x x x x x x
CANFHRx FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 FIL4
60, 64 4
Reset Value x x x x x x x x
CANLIDLR LID2 LID1 LID0 LRTR LDLC3 LDLC2 LDLC1 LDLC0
0
Reset Value x x x x x x x x
61
CANIDLRx ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0
1 to 3
Reset Value x x x x x x x x
CANFLRx FIL3 FIL2 FIL1 FIL0
61, 65 4
Reset Value x x x x 0 0 0 0
CANDRx MSB LSB
62 to 69 1 to 3
Reset Value x x x x x x x x
CANMHRx MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4
62, 66 4
Reset Value x x x x x x x x
CANMLRx MSK3 MSK2 MSK1 MSK0
63, 67 4
Reset Value x x x x 0 0 0 0
CANTECR MSB LSB
6E 0
Reset Value 0 0 0 0 0 0 0 0
CANRECR MSB LSB
Reset Value 0 0 0 0 0 0 0 0
6F
CANBCSRx ACC RDY BUSY LOCK
1 to 3
Reset Value 0 0 0 0 0 0 0 0

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10.8.5 List of CAN Cell Limitations For CAN transmitted messages the 2nd data byte
10.8.5.1 Omitted SOF bit can be corrupted.
Symptom: Details:
Start of Frame (SOF) bit is omitted if transmission The CAN transmit and receive buffers are imple-
is requested in the last Intermission bit. mented as dual ported RAM. During the reception
of a CAN frame the CAN core writes the received
Test Case: identifier and the data byte-by-byte in the corre-
5.3.1 10-Kbit Stress Test sponding buffer.
Details: IF the CAN bit timing configuration is tBS2 < 5 time
The IUT is requested to start transmission immedi- quanta
ately after the completion of the previous transmis- AND
sion. The LT also starts its transmission and as- IF concurrently with the pCAN, the CPU executes
serts the SOF bit just after the 3rd Intermission bit. a write access to the dual ported RAM using an in-
The IUT also starts transmission but omits the struction with more than one cycle access, e.g.
SOF bit. The IUT wins the arbitration and contin- CLR, BSET, BRES
ues the transmission. The frame is sent correctly. THEN the access conflict can lead to the corrup-
tion described in the symptoms paragraph above.
Impact On The Application:
Impact On The Application:
As this effect only occurs when the IUT detects a
SOF bit on the CAN bus, the fact that it omits its Several CAN frames with erroneous data or iden-
own SOF bit has no impact on the communication. tifier will be received/transmitted.
10.8.5.2 CAN: CPU Write Access (More Than Software Workaround:
One Cycle) Corrupts CAN Frame Program tBS2 > 4 time quanta or, when accessing
the receive or transmit buffers, do not use the crit-
Symptoms:
ical instructions which are:
For CAN received messages the identifier high
BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,
byte or last data byte can be corrupted.
SLL, SRL, RRC, SRA, SWAP.

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CONTROLLER AREA NETWORK (Cont’d)

10.8.5.3 Unexpected message transmission cation might need to abort this transmission re-
Symptom: quest. To do so, the application can reset the
LOCK bit in the BCSR register.
The previous message received by pCAN, even if If the message is pending (RDY bit set) but not
this message did not pass the receive filter, will be currently being transmitted, then clearing the
retransmitted by pCAN with a correct identifier and LOCK bit will abort it immediately.
DLC but with corrupted data. The data bytes will If the message is pending (RDY bit set) and cur-
be a copy of the identifier bytes IDHR and IDLR in rently being transmitted then the message will not
the following repetitive pattern: be interrupted but the CAN core will wait until the
DATA_0 = IDHR end of this transmission attempt. Then software
DATA_1 = IDLR must clear the LOCK bit again to abort the trans-
DATA_2 = IDHR mission.
DATA_3 = IDLR An unexpected transmission can occur:
etc.
DATA_7 = IDLR IF the application resets the LOCK bit
If no message has been received before the prob- WHILE the CAN core is preparing the
lem occurs then identifier byte values are random transmission1) AND there is no other transmission
but the data bytes are in the same repetitive pat- pending in another buffer
tern. THEN the LOCK bit is reset but the transmission is
Details: not stopped. Instead the content of the page 0
The buffers of the pCAN cell are configurable as buffer will be transmitted.
receive or transmit buffers. By default, all buffers Impact On The Application:
are configured in reception. To use a buffer to pCAN will echo some messages sent by other
transmit a CAN message the application has to re- nodes. Identifier and DLC will be correct but data
serve this buffer for transmission by setting the are corrupted as described previously.
LOCK bit in the BCSR register. So the buffer is
then locked for any further reception and reserved Note 1: The preparation lasts two bit times just be-
for transmission. fore SOF, this is the critical window during which
the LOCK bit must not be reset by the application.
Once a transmission has been requested by a
write access to data byte 7 of the buffer the appli-

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CONTROLLER AREA NETWORK (Cont’d)

Software Work-around - Devices with Hard- To abort the transmission, first the application sets
ware Fix (ST72F521 rev “R”): the WKPS bit and polls it until it is set. The maxi-
To implement a transmission abort under safe mum time needed to set this bit is two CAN bit
conditions, the LOCK bit must not be reset during times. Once the application has read the WKPS bit
the critical window (2 bit times). A new function as one, it can reset the LOCK bit to stop the cur-
has been implemented in the MCU allowing the rent transmission.
application to synchronize the reset of the LOCK The abort is completed when the LOCK bit is read
bit (abort request) with the reset of the TXRQST bit back as zero by the application. Once the abort
(internal signal) in the pCAN core. has been completed, the application must reset
The synchronization is done using the WKPS bit in the WKPS bit to be able to transmit again. Of
the CANCSR register, the function of this bit has course the transmit buffer must be in LOCK state
been modified and no more Wake-up Pulse (dom- as usual before any transmission attempt.
inant bit) is sent on the CAN_TX signal when the The “C” code sequence below shows the software
WKPS bit is set. This means the functionality de- work-around using the WKPS bit.
scribed in the datasheet is no longer applicable
(see Section 10.8.5.4).
CANCSR |= WKPS; // Set WKPS bit
while(!(CANCSR & WKPS) );// Wait until WKPS bit is set
while( CANBCSR & LOCK )// Wait until abort has been confirmed
{
CANBCSR &= ~LOCK;
}
CANCSR &= ~WKPS; // Allow transmission again
CANBCSR |= LOCK; //Alloc buffer for next transmission

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CONTROLLER AREA NETWORK (Cont’d)

Software Work-around - Devices without Hard- Abort while staying in RUN mode (RUN=1)
ware Fix: Contrary to the STANDBY case described previ-
To implement a transmission abort under safe ously, in the RUN case the application has to han-
conditions, any reset of the LOCK bit during the dle the error or arbitration lost conditions. In case
critical window (2 bit times) must be avoided. Two of transmission errors, causing the frame to be
different cases have to be considered, either the transmitted again and again, the application must
pCAN enters standby mode after the abort, or the set the NRTX bit in the CSR register. This will
abort is performed and pCAN keeps running. cause pCAN to abort the transmission at the end
of the current attempt.
Abort followed by STANDBY mode (RUN=0) In case of arbitration lost, setting the NRTX bit
does not abort the transmission, therefore the ap-
In this case, aborting the pending transmissions plication must reset the LOCK bit to abort the
can safely be done by first entering STANDBY transmission. To avoid resetting the LOCK bit dur-
mode and then releasing the transmit buffers. ing the critical time window, leading to the problem
STANDBY mode is entered by resetting the RUN described at the start of this section, the applica-
bit in the CSR register and once the current trans- tion must monitor the BUSY bit in the BCSR regis-
mission attempt, even if it fails due to error or lost ter and reset the LOCK bit just after the falling
arbitration, has been performed, pCAN enters edge of the BUSY bit. The time between the falling
STANDBY mode (RUN=0). Once in STANDBY edge of the BUSY bit and the SOF of the next
mode the application can abort all pending trans- transmission attempt is in any case long enough to
missions by resetting the corresponding LOCK bit. guarantee that the LOCK bit is reset before the
critical time window.
The “C” code sequence below shows the software
work-around for both the error and arbitration lost
cases.
_asm("SIM\n"); // Mask interrupts
CANCSR |= NRTX; // Set non automatic retransmission bit
while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set
(CANBCSR & RDY) ); // or transmission done
while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge)
if( CANBCSR & RDY )
{ // transmission still pending -> must be aborted
CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safel
while( CANBCSR & RDY );// Wait for unlock confirmed
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n");
}
else
{ // No more abort required as RDY bit already reset
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n"); // Enable interrupts
}

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ST72F521, ST72521B

Figure 75. Work-around Flowchart

Application Requests
an Abort

YES NO
READY == 1

MASK INT

SET NRTX

YES BUSY == 0
NO
AND
READY == 1

YES NO
BUSY == 0

YES NO
READY == 1

RESET LOCK

NO YES
READY == 1

SET LOCK RESET NRTX

ENABLE INT

Abort Done

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 ST72F521, ST72521B

CONTROLLER AREA NETWORK (Cont’d)

The figures below show the abort behaviour in the the error (the first attempt). The abort has been
four possible cases. successful and the transmit buffer is empty.
Figure 76. Abort and successful transmission Figure 79. Abort and arbitration lost
TX RQST TX RQST
ABORT RQST ABORT RQST

CAN TX
CAN TX
CAN RX
CAN RX
LOCK
LOCK READY
READY BUSY
BUSY NRTX

NRTX
In this case the NRTX bit is set but has no effect,
as the previous transmission attempt failed due to
In this case the abort request performed during the an arbitration lost. The application waits for the
transmission has no effect, as the first transmis- falling edge of BUSY bit and checks that READY is
sion is successful. still set. This is the case, this means pCAN has lost
Figure 77. Abort and transmission delayed by the arbitration and LOCK bit can be safely reset.
Abort is immediate and pCAN resets the READY
busy CAN bus and BUSY bits.
TX RQST
ABORT RQST
Timing Considerations
CAN TX As no interrupt signals that an abort has been suc-
CAN RX cessful, the application has to wait until the trans-
LOCK mit buffer is empty (transmission has been aborted
READY or transmitted successfully). This time can vary
BUSY depending on the case in which the abort is per-
NRTX formed (arbitration lost, error or successful trans-
mission). To show the impact of the software work-
In this case the NRTX bit is set to abort the trans- around on this timing behaviour Figure 80 and Fig-
mission after the first attempt. As the first attempt ure 81 compare the reference behaviour (worst
is successful the READY and BUSY bits are reset case when abort is done by LOCK only) with the
by pCAN and the transmit buffer becomes empty. behaviour when NRTX, BUSY and LOCK bits are
An abort is no longer required. used.
Figure 78. Abort and error during transmission Figure 80. Abort by LOCK only - Reference
Error
TX RQST behaviour
ABORT RQST
TX RQST
CAN TX ABORT RQST
CAN RX CAN TX
LOCK CAN RX
READY LOCK
BUSY READY
NRTX BUSY
NRTX

In this case NRTX (abort request) is set before the

error, thus pCAN resets READY and BUSY after

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ST72F521, ST72521B

CONTROLLER AREA NETWORK (Cont’d)

The worst case is when the abort request is done reset. If the next arbitration is won by pCAN then
when the transmission has just started. In this the BUSY bit will be reset by the end of the suc-
case the LOCK bit cannot be reset as long as the cessful transmission. The longest time the applica-
BUSY bit is set, this means until the end of the tion has to wait in this case is the time of the long-
frame. So the application will wait for READY to be est message expected on the bus (minus identifi-
reset during the whole frame and in this case the er) plus the longest message expected to be trans-
worst case will be the longest frame the applica- mitted by the application. This roughly double the
tion is expected to transmit. time the application may have to wait before the
abort sequence is performed.
Figure 81. Abort with the software work-around
10.8.5.4 WKPS Functionality
- by NRTX, BUSY and LOCK
Due to a fix implemented to solve the “Unexpected
TX RQST
ABORT RQST
Message Transmission” issue (see Section
10.8.5.3) the WKPS functionality has been modi-
CAN TX
fied as follows in Flash ST72F521 devices:
CAN RX
LOCK Device Modification
READY
WKPS bit does not generate a wakeup
BUSY
Flash pulse. It is used to synchronize the re-
NRTX
ST72F521 set of the LOCK bit (see “Software
Rev R Work-around - Devices with Hardware
Using the software work-around the worst case Fix (ST72F521 rev “R”):” on page 148)
occurs in the arbitration lost case. If the abort is re-
ROM
quested just after pCAN has lost the arbitration WKPS bit functions according to the
then the application has to wait for the next falling ST72521 All
datasheet description.
edge of the BUSY bit before the LOCK bit can be revisions

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 ST72F521, ST72521B

CONTROLLER AREA NETWORK (Cont’d)

10.8.5.5 Bus-off state not entered ue lower than 128, this is the case with any correct
Symptom: reception even if the message is filtered out.
pCAN does not enter bus-off state under certain As bus-off state is not entered and pCAN still at-
conditions. This is fixed in FLASH version of tempts to transmit its message, after the overflow
ST72F521 starting from silicon Rev R and in ROM the TEC register continues to increment as long as
version ST72521B starting from silicon Rev Y. transmission errors occur.
Details: Impact on the application:
According to the CAN standard, pCAN is expected The application will not stop attempting to transmit
to enter bus-off state when TEC (Transmit Error CAN messages, even when the bus-off conditions
Counter) is greater than 255. have been reached, until the transmission has
But if REC (Receive Error Counter) is greater than been successful or the value of REC becomes
127 (Error Passive State) pCAN does not enter lower than 128. However the application will not
bus-off and the BOFF bit of the CSR register is not disturb the communication of the other nodes on
set. To enter bus-off, REC must decrease to a val- the CAN network as pCAN is in Error Passive
State.
Figure 82. CAN Error State Diagram showing “BUSOFF not entered” limitation

When TECR or RECR > 127, the EPSV bit gets set

ERROR ACTIVE
ERROR PASSIVE

When TECR and RECR < 128,

the EPSV bit gets cleared

When 128 * 11 recessive bits occur: When TECR > 255 and RECR < 128 the BOFF bit
- the BOFF bit gets cleared gets set and the EPSV bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared

BUS OFF

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CONTROLLER AREA NETWORK (Cont’d)

Workaround Description to reach 256 the sequence must be executed 32
The bus-off entry works correctly in almost all cas- times. Under these conditions the shortest se-
es, only when REC is greater than 127 a bus-off quence leading to a TEC overflow lasts 832 bit
will not be recognized by pCAN. Therefore the times.
pCAN bus-off signalling (BOFF) is still used but it Depending on the baudrate the application will
needs to be complemented by monitoring TEC by have to adapt the monitoring period, for example
software. at 500kbps the period must be less than 1600us.
To detect the bus-off condition by software the ap- The ‘C’ code below shows an implementation ex-
plication has to monitor the value of the TEC reg- ample of the monitoring sequence. This code is
ister periodically. An overflow signals a bus-off called periodically as described above.
condition. When a bus-off condition has been de- To detect the overflow, the test condition must
tected the application must execute the following take into account that TEC might also have been
sequence to recover from bus-off properly: the ap- decremented due to a successful transmission. So
plication stops pCAN by clearing the RUN bit in the an overflow condition is detected:
CANCSR register resets all pending transmission
by clearing the LOCK bit in the BCSR register and IF the current TEC value is lower than the previous
starts it again by setting the RUN bit. TEC value
To detect the bus-off condition properly, the TEC AND the difference is greater than the number of
monitoring period must be lower than the time be- possible successful transmissions during the mon-
tween two overflows. As the problem only occurs itoring period.
when pCAN is in Error Passive State (REC > 127) In the example above, one message can be sent,
pCAN will continuously try to send a SOF followed therefore one is added to CANTECR.
by an Error Passive Flag and a Suspend Trans-
mission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit
times. Each time TEC is incremented by 8, hence
************************************************/
/* INITIALISATION
/************************************************/
unsigned char TECReg=0; //Previous value of TEC
unsigned char BusOffFlag=0; //Set to one if bus-off

/************************************************/
/* BUS-OFF MONITORING SEQUENCE
/************************************************/

if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )

{
BusOffFlag = 1;
}
else
{
TECReg = CANTECR;
}

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 ST72F521, ST72521B

10.9 10-BIT A/D CONVERTER (ADC)

10.9.1 Introduction 10.9.2 Main Features

The on-chip Analog to Digital Converter (ADC) pe- ■ 10-bit conversion
ripheral is a 10-bit, successive approximation con- ■ Up to 16 channels with multiplexed input
verter with internal sample and hold circuitry. This ■ Linear successive approximation
peripheral has up to 16 multiplexed analog input
■ Data register (DR) which contains the results
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage ■ Conversion complete status flag
levels from up to 16 different sources. ■ On/off bit (to reduce consumption)
The result of the conversion is stored in a 10-bit The block diagram is shown in Figure 83.
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 83. ADC Block Diagram
fCPU DIV 4 0
fADC
DIV 2 1

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0

AIN1
ANALOG TO DIGITAL
ANALOG
MUX CONVERTER

AINx

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 0 0 D1 D0

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.9.3 Functional Description
The conversion is monotonic, meaning that the re- To read the 10 bits, perform the following steps:
sult never decreases if the analog input does not 1. Poll the EOC bit
and never increases if the analog input does not.
2. Read the ADCDRL register
If the input voltage (VAIN) is greater than VAREF
(high-level voltage reference) then the conversion 3. Read the ADCDRH register. This clears EOC
result is FFh in the ADCDRH register and 03h in automatically.
the ADCDRL register (without overflow indication). Note: The data is not latched, so both the low and
If the input voltage (VAIN) is lower than VSSA (low- the high data register must be read before the next
level voltage reference) then the conversion result conversion is complete, so it is recommended to
in the ADCDRH and ADCDRL registers is 00 00h. disable interrupts while reading the conversion re-
sult.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD- To read only 8 bits, perform the following steps:
CDRL registers. The accuracy of the conversion is 1. Poll the EOC bit
described in the Electrical Characteristics Section. 2. Read the ADCDRH register. This clears EOC
RAIN is the maximum recommended impedance automatically.
for an analog input signal. If the impedance is too
10.9.3.3 Changing the conversion channel
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the The application can change channels during con-
alloted time. version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
10.9.3.1 A/D Converter Configuration
stopped, the EOC bit is cleared, and the A/D con-
The analog input ports must be configured as in- verter starts converting the newly selected chan-
put, no pull-up, no interrupt. Refer to the «I/O nel.
ports» chapter. Using these pins as analog inputs
10.9.4 Low Power Modes
does not affect the ability of the port to be read as
a logic input. Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
In the ADCCSR register:
power consumption when no conversion is need-
– Select the CS[3:0] bits to assign the analog ed and between single shot conversions.
channel to convert.
10.9.3.2 Starting the Conversion Mode Description
In the ADCCSR register: WAIT No effect on A/D Converter
– Set the ADON bit to enable the A/D converter A/D Converter disabled.
and to start the conversion. From this time on, After wakeup from Halt mode, the A/D
the ADC performs a continuous conversion of Converter requires a stabilization time
the selected channel. HALT
tSTAB (see Electrical Characteristics)
before accurate conversions can be
When a conversion is complete: performed.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit. 10.9.5 Interrupts
None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.9.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR) Bit 3:0 = CH[3:0] Channel Selection
Read/Write (Except bit 7 read only) These bits are set and cleared by software. They
select the analog input to convert.
Reset Value: 0000 0000 (00h)
Channel Pin* CH3 CH2 CH1 CH0
7 0 AIN0 0 0 0 0
AIN1 0 0 0 1
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 AIN2 0 0 1 0
AIN3 0 0 1 1
Bit 7 = EOC End of Conversion AIN4 0 1 0 0
This bit is set by hardware. It is cleared by hard- AIN5 0 1 0 1
ware when software reads the ADCDRH register AIN6 0 1 1 0
or writes to any bit of the ADCCSR register. AIN7 0 1 1 1
0: Conversion is not complete AIN8 1 0 0 0
1: Conversion complete AIN9 1 0 0 1
AIN10 1 0 1 0
Bit 6 = SPEED ADC clock selection AIN11 1 0 1 1
This bit is set and cleared by software. AIN12 1 1 0 0
0: fADC = fCPU/4 AIN13 1 1 0 1
1: fADC = fCPU/2 AIN14 1 1 1 0
AIN15 1 1 1 1
Bit 5 = ADON A/D Converter on *The number of channels is device dependent. Refer to
This bit is set and cleared by software. the device pinout description.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Bit 4 = Reserved. Must be kept cleared. Read Only
Reset Value: 0000 0000 (00h)

7 0

D9 D8 D7 D6 D5 D4 D3 D2

Bit 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 D1 D0

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Converted Analog Value

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10-BIT A/D CONVERTER (Cont’d)

Table 25. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCCSR EOC SPEED ADON CH3 CH2 CH1 CH0

0070h
Reset Value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0071h
Reset Value 0 0 0 0 0 0 0 0
ADCDRL D1 D0
0072h
Reset Value 0 0 0 0 0 0 0 0

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 ST72F521, ST72521B

11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55
00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
Relative jrne loop (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 26. CPU Addressing Mode Overview
Pointer Pointer Size Length
Mode Syntax Destination Address (Hex.) (Bytes)
(Hex.)
Inherent nop +0

Immediate ld A,#$55 +1

Short Direct ld A,$10 00..FF +1

Long Direct ld A,$1000 0000..FFFF +2

No Offset Direct Indexed ld A,(X) 00..FF +0

Short Direct Indexed ld A,($10,X) 00..1FE +1

Long Direct Indexed ld A,($1000,X) 0000..FFFF +2

Short Indirect ld A,[$10] 00..FF 00..FF byte +2

Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2

Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2

Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2

Relative Direct jrne loop PC+/-127 +1

Relative Indirect jrne [$10] PC+/-127 00..FF byte +2

Bit Direct bset $10,#7 00..FF +1

Bit Indirect bset [$10],#7 00..FF 00..FF byte +2

Bit Direct Relative btjt $10,#7,skip 00..FF +2

Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

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ST72F521, ST72521B

INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent 11.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
Wait For Interrupt (Low Pow-
after the opcode, but only allows 00 - FF address-
WFI
er Mode)
ing space.
Halt Oscillator (Lowest Power Direct (long)
HALT
Mode) The address is a word, thus allowing 64 Kbyte ad-
RET Sub-routine Return dressing space, but requires 2 bytes after the op-
code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask (level 3)
RIM Reset Interrupt Mask (level 0)
11.1.4 Indexed (No Offset, Short, Long)
SCF Set Carry Flag In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer
The indirect addressing mode consists of three
LD Load sub-modes:
CLR Clear Indexed (No Offset)
PUSH/POP Push/Pop to/from the stack There is no offset, (no extra byte after the opcode),
INC/DEC Increment/Decrement and allows 00 - FF addressing space.
TNZ Test Negative or Zero Indexed (Short)
CPL, NEG 1 or 2 Complement The offset is a byte, thus requires only one byte af-
MUL Byte Multiplication ter the opcode and allows 00 - 1FE addressing
SLL, SRL, SRA, RLC,
space.
Shift and Rotate Operations Indexed (long)
RRC
SWAP Swap Nibbles The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con- 11.1.5 Indirect (Short, Long)
tains the operand value. The required data byte to do the operation is found
Immediate Instruction Function
by its memory address, located in memory (point-
er).
LD Load
The pointer address follows the opcode. The indi-
CP Compare rect addressing mode consists of two sub-modes:
BCP Bit Compare Indirect (short)
AND, OR, XOR Logical Operations
The pointer address is a byte, the pointer size is a
ADC, ADD, SUB, SBC Arithmetic Operations byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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 ST72F521, ST72521B

INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long) 11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed This addressing mode is used to modify the PC
addressing modes. The operand is referenced by register value, by adding an 8-bit signed offset to
its memory address, which is defined by the un- it.
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- Available Relative
er address follows the opcode. Direct/Indirect Function
Instructions
The indirect indexed addressing mode consists of
two sub-modes: JRxx Conditional Jump
CALLR Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long) Relative (Direct)
The pointer address is a byte, the pointer size is a The offset is following the opcode.
word, thus allowing 64 Kbyte addressing space, Relative (Indirect)
and requires 1 byte after the opcode. The offset is defined in memory, which address
Table 27. Instructions Supporting Direct, follows the opcode.
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Additions/Sub-
ADC, ADD, SUB, SBC
stractions operations
BCP Bit Compare

Short Instructions
Function
Only
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC, Shift and Rotate Opera-
RRC tions
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:

Load and Transfer LD CLR

Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF

Using a pre-byte
The instructions are described with one to four op- These prebytes enable instruction in Y as well as
codes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction
cede. using immediate, direct, indexed, or inherent ad-
The whole instruction becomes: dressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using di-
rect, direct bit, or direct relative addressing mode
PC-1 Prebyte to an instruction using the corresponding indirect
PC opcode addressing mode.
PC+1 Additional word (0 to 2) according It also changes an instruction using X indexed ad-
to the number of bytes required to compute the ef- dressing mode to an instruction using indirect X in-
fective address dexed addressing mode.
PIY 91 Replace an instruction using X in-
direct indexed addressing mode by a Y one.

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. INT pin = 1 (ext. INT pin high)
JRIL Jump if ext. INT pin = 0 (ext. INT pin low)
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I1:0 = 11 I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A=A+M A M N Z
pop reg reg M
POP Pop from the Stack
pop CC CC M I1 H I0 N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C=0 0
RET Subroutine Return
RIM Enable Interrupts I1:0 = 10 (level 0) 1 0
RLC Rotate left true C C <= A <= C reg, M N Z C
RRC Rotate right true C C => A => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Substract with Carry A=A-M-C A M N Z C
SCF Set carry flag C=1 1
SIM Disable Interrupts I1:0 = 11 (level 3) 1 1
SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C
SLL Shift left Logic C <= A <= 0 reg, M N Z C
SRL Shift right Logic 0 => A => C reg, M 0 Z C
SRA Shift right Arithmetic A7 => A => C reg, M N Z C
SUB Substraction A=A-M A M N Z C
SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1 1
WFI Wait for Interrupt 1 0
XOR Exclusive OR A = A XOR M A M N Z

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12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re- Figure 85. Pin input voltage
ferred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max- ST7 PIN
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the VIN
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V.They are given only as de-
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 84.
Figure 84. Pin loading conditions

ST7 PIN

CL

12.1.5 Pin input voltage

The input voltage measurement on a pin of the de-
vice is described in Figure 85.

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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
12.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.5
VPP - VSS Programming Voltage 13
V
1) & 2)
Input Voltage on true open drain pin VSS-0.3 to 6.5
VIN
Input voltage on any other pin VSS-0.3 to VDD+0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins 50
mV
|VSSA - VSSx| Variations between digital and analog ground pins 50
VESD(HBM) Electro-static discharge voltage (Human Body Model)
see section 12.7.3 on page 181
VESD(MM) Electro-static discharge voltage (Machine Model)
12.2.2 Current Characteristics
Symbol Ratings Maximum value Unit
IVDD 3)
Total current into VDD power lines (source) 150
mA
IVSS Total current out of VSS ground lines (sink) 3) 150
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
Injected current on VPP pin ±5
Injected current on RESET pin ±5 mA
2) & 4)
IINJ(PIN) Injected current on OSC1 and OSC2 pins ±5
Injected current on PC6 (Flash devices only) +5
5) & 6)
Injected current on any other pin ±5
2)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) 5) ± 25
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 196.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.

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12.2.3 Thermal Characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions
Symbol Parameter Conditions Min Max Unit
fCPU Internal clock frequency 0 8 MHz
Standard voltage range (except Flash
3.8 5.5
VDD Write/Erase) V
Operating Voltage for Flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5
1 Suffix Version 0 70
5 Suffix Version -10 85
TA Ambient temperature range 6 or A Suffix Versions -40 85 °C
7 or B Suffix Versions -40 105
C Suffix Version -40 125

Figure 86. fCPU Max Versus VDD

fCPU [MHz]

8 FUNCTIONALITY
FUNCTIONALITY GUARANTEED
NOT GUARANTEED IN THIS AREA
6 (UNLESS
IN THIS AREA
OTHERWISE
4 SPECIFIED
IN THE TABLES
2 OF PARAMETRIC
DATA)
1
0
3.5 3.8 4.0 4.5 5.5

SUPPLY VOLTAGE [V]

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information.

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OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
VD level = High in option byte 4.0 1) 4.2 4.5
Reset release threshold
VIT+(LVD)
(VDD rise) VD level = Med. in option byte3) 3.55 1) 3.75 4.01)
VD level = Low in option byte3) 2.95 1) 3.15 3.351)
V
VD level = High in option byte 3.8 4.0 4.25 1)
Reset generation threshold
VIT-(LVD)
(VDD fall) VD level = Med. in option byte3) 3.351) 3.55 3.751)
VD level = Low in option byte3) 2.81) 3.0 3.15 1)
LVD voltage threshold hysteresis
Vhys(LVD) 1) VIT+(LVD)-VIT-(LVD) 150 200 250 mV

Flash device, LVD enabled 6µs/V 20ms/V

VtPOR VDD rise time 1)2)
ROM device, LVD enabled 6µs/V 100ms/V
VDD glitches filtered (not detect-
tg(VDD) 40 ns
ed) by LVD 1)
Notes:
1. Data based on characterization results, tested in production for ROM devices only.
2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the
VIT+(LVD) threshold.
3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
Below 3.8V, device operation is not guaranteed.

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
1)
VD level = High in option byte 4.4 4.6 4.9
1⇒0 AVDF flag toggle threshold
VIT+(AVD)
(VDD rise) VD level = Med. in option byte 3.95 1) 4.15 4.41)
VD level = Low in option byte 3.4 1) 3.6 3.81)
V
VD level = High in option byte 4.2 4.4 4.65 1)
0⇒1 AVDF flag toggle threshold
VIT-(AVD)
(VDD fall) VD level = Med. in option byte 3.751) 4.0 4.2 1)
VD level = Low in option byte 3.21) 3.4 3.6 1)
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200 mV
Voltage drop between AVD flag set
∆VIT- VIT-(AVD)-VIT-(LVD) 450 mV
and LVD reset activated
1. Data based on characterization results, tested in production for ROM devices only.

12.3.4 External Voltage Detector (EVD) Thresholds

Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
1⇒0 AVDF flag toggle threshold
VIT+(EVD) 1.15 1.26 1.35
(VDD rise)1)
V
0⇒1 AVDF flag toggle threshold
VIT-(EVD) 1.1 1.2 1.3
(VDD fall)1)
Vhys(EVD) EVD voltage threshold hysteresis VIT+(EVD)-VIT-(EVD) 200 mV
1. Data based on characterization results, not tested in production.

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12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
12.4.1 CURRENT CONSUMPTION
Flash Devices ROM Devices
Symbol Parameter Conditions Unit
Typ Max 1) Typ Max 1)
fOSC=2MHz, fCPU=1MHz 1.3 3.0 1.3 2.0
fOSC=4MHz, fCPU=2MHz 2.0 5.0 2.0 3.0
Supply current in RUN mode 2) mA
fOSC=8MHz, fCPU=4MHz 3.6 8.0 3.6 5.0
fOSC=16MHz, fCPU=8MHz 7.1 15.0 7.1 10.0
fOSC=2MHz, fCPU=62.5kHz 600 2700 600 1800
fOSC=4MHz, fCPU=125kHz 700 3000 700 2100
Supply current in SLOW mode 2) µA
fOSC=8MHz, fCPU=250kHz 800 3600 800 2400
fOSC=16MHz, fCPU=500kHz 1100 4000 1100 3000
fOSC=2MHz, fCPU=1MHz 1.0 3.0 1.0 1.3
IDD 2) fOSC=4MHz, fCPU=2MHz 1.5 4.0 1.5 2.0
Supply current in WAIT mode mA
fOSC=8MHz, fCPU=4MHz 2.5 5.0 2.5 3.3
fOSC=16MHz, fCPU=8MHz 4.5 7.0 4.5 6.0
fOSC=2MHz, fCPU=62.5kHz 580 1200 70 200
f =4MHz, fCPU=125kHz 650 1300 100 300
Supply current in SLOW WAIT mode 2) OSC µA
fOSC=8MHz, fCPU=250kHz 770 1800 200 600
fOSC=16MHz, fCPU=500kHz 1050 2000 350 1200
-40°C≤TA≤+85°C <1 10 <1 10
Supply current in HALT mode 3) µA
-40°C≤TA≤+125°C <1 50 <1 50
fOSC=2MHz 80 No 15 25
Supply current in ACTIVE-HALT mode fOSC=4MHz 160 max. 30 50
IDD 4) µA
fOSC=8MHz 325 guaran- 60 100
fOSC =16MHz 650 teed 120 200

Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.4.2) and the peripheral power
consumption (Section 12.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data
based on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the
total current consumption of the device, add the clock source consumption (Section 12.4.2).

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.1.1 Power Consumption vs fCPU: Flash Devices
Figure 87. Typical IDD in RUN mode Figure 89. Typical IDD in WAIT mode

6 8MHz
9 8MHz
4MHz
4MHz
8 2MHz
2MHz 5
1MHz
7 1MHz
4
6

Idd (mA)
Idd (mA)

5 3
4
2
3
2 1
1
0
0
3.2 3.6 4 4.4 4.8 5.2 5.5
3.2 3.6 4 4.4 4.8 5.2 5.5
Vdd (V)
Vdd (V)

Figure 88. Typical IDD in SLOW mode Figure 90. Typ. IDD in SLOW-WAIT mode

1.20
500kHz
1.20 500kHz 250kHz
250kHz 1.00 125kHz
1.00 125kHz 62.5kHz
62.5kHz 0.80
)

0.80
Idd (mA)

0.60
(

0.60
0.40
0.40
0.20
0.20
0.00
0.00 3.2 3.6 4 4.4 4.8 5.2 5.5
3.2 3.6 4 4.4 4.8 5.2 5.5
Vdd (V)
Vdd (V)

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.2 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).
Symbol Parameter Conditions Typ Max Unit
IDD(RCINT) Supply current of internal RC oscillator 625
see section
IDD(RES) Supply current of resonator oscillator 1) & 2) 12.5.3 on page
174 µA
IDD(PLL) PLL supply current VDD= 5V 360
IDD(LVD) LVD supply current VDD= 5V 150 300

Notes:
1.. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in
production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 On-Chip Peripherals
Measured on S72F521R9T3 on TQFP64 generic board TA = 25°C fCPU=4MHz.
Symbol Parameter Conditions Typ Unit
IDD(TIM) 16-bit Timer supply current 1) VDD=5.0V 50 µA
IDD(ART) ART PWM supply current2) VDD=5.0V 75 µA
3)
IDD(SPI) SPI supply current VDD=5.0V 400 µA
IDD(SCI) SCI supply current 4) VDD=5.0V 400 µA
IDD(I2C) I2C supply current 5) VDD=5.0V 175 µA
IDD(ADC) ADC supply current when converting 6) VDD=5.0V 400 µA
5)
IDD(CAN) CAN supply current VDD=5.0V 400 µA

Notes:
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer counter enabled
(only TCE bit set).
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
mit sequence.
5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master
communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm
external pull-up on clock and data lines).
6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
7. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.

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12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.
12.5.1 General Timings
Symbol Parameter Conditions Min Typ 1) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time
fCPU=8MHz 250 375 1500 ns
2) 10 22 tCPU
Interrupt reaction time
tv(IT)
tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 1.25 2.75 µs

12.5.2 External Clock Source

Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage VDD-1 VDD
V
VOSC1L OSC1 input pin low level voltage VSS VSS+1
tw(OSC1H)
OSC1 high or low time 3) see Figure 91 5
tw(OSC1L)
ns
tr(OSC1)
OSC1 rise or fall time 3) 15
tf(OSC1)
IL OSC1 Input leakage current VSS≤VIN≤VDD ±1 µA

Figure 91. Typical Application with an External Clock Source

90%
VOSC1H
10%

VOSC1L

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

OSC2
Not connected internally

fOSC
EXTERNAL
IL
CLOCK SOURCE
OSC1
ST72XXX

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four close as possible to the oscillator pins in order to
different Crystal/Ceramic resonator oscillators. All minimize output distortion and start-up stabiliza-
the information given in this paragraph are based tion time. Refer to the crystal/ceramic resonator
on characterization results with specified typical manufacturer for more details (frequency, pack-
external components. In the application, the reso- age, accuracy...).
nator and the load capacitors have to be placed as
Symbol Parameter Conditions Min Max Unit
LP: Low power oscillator 1 2
MP: Medium power oscillator >2 4
fOSC Oscillator Frequency 1) MHz
MS: Medium speed oscillator >4 8
HS: High speed oscillator >8 16
RF Feedback resistor2) 20 40 kΩ
RS=200Ω LP oscillator 22 56
CL1 Recommended load capacitance ver-
RS=200Ω MP oscillator 22 46
sus equivalent serial resistance of the pF
CL2 RS=200Ω MS oscillator 18 33
crystal or ceramic resonator (RS)
RS=100Ω HS oscillator 15 33

Symbol Parameter Conditions Typ Max Unit

VDD=5V LP oscillator 80 150
VIN=VSS MP oscillator 160 250
i2 OSC2 driving current µA
MS oscillator 310 460
HS oscillator 610 910

Figure 92. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS i2

fOSC
CL1 OSC1

RESONATOR RF
CL2
OSC2
ST72XXX

Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Typical Ceramic Resonators

fOSC
Supplier Recommended OSCRANGE
(MHz) Reference2)
Option bit configuration
2 CSTCC2M00G56A-R0 MP Mode3)
Murata

4 CSTCR4M00G55B-R0 MS Mode
8 CSTCE8M00G55A-R0 HS Mode
16 CSTCE16M0G53A-R0 HS Mode

Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
3. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8V)
For more information on these resonators, please consult www.murata.com

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CLOCK CHARACTERISTICS (Cont’d)

12.5.4 RC Oscillators
Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator frequency
fOSC (RCINT) TA=25°C, VDD=5V 2 3.5 5.6 MHz
See Figure 93

Figure 93. Typical fOSC(RCINT) vs TA Note: To reduce disturbance to the RC oscillator,

it is recommended to place decoupling capacitors
between VDD and VSS as shown in Figure 113

4
Vdd = 5V
fOSC(RCINT) (MHz)

3.8
Vdd = 5.5V
3.6

3.4

3.2

3
-45 0 25 70 130
TA(°C)

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CLOCK CHARACTERISTICS (Cont’d)

12.5.5 PLL Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC PLL input frequency range 2 4 MHz
ROM device,
0.7 2
fOSC = 4 MHz.
Flash device,
∆ fCPU/ fCPU Instantaneous PLL jitter 1) 1.0 2.5 %
fOSC = 4 MHz.
Flash device,
2.5 4.0
fOSC = 2 MHz.

Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 94 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
Figure 94. Integrated PLL Jitter vs signal frequency1
+/-Jitter (%)
1.2
FLASH typ
1 ROM max
0.8 ROM typ

0.6

0.4

0.2

0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency

Note 1: Measurement conditions: fCPU = 8MHz.

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12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers
Symbol Parameter Conditions Min Typ Max Unit
1)
VRM Data retention mode HALT mode (or RESET) 1.6 V

12.6.2 FLASH Memory

DUAL VOLTAGE HDFLASH MEMORY
Symbol Parameter Conditions Min 2) Typ Max 2) Unit
Read mode 0 8
fCPU Operating frequency MHz
Write / Erase mode 1 8
VPP Programming voltage 3) 4.5V ≤ VDD ≤ 5.5V 11.4 12.6 V
RUN mode (fCPU = 4MHz) 3
mA
IDD Supply current4) Write / Erase 0
Power down mode / HALT 1 10
µA
Read (VPP=12V) 200
IPP VPP current4)
Write / Erase 30 mA
tVPP Internal VPP stabilization time 10 µs
tRET Data retention TA=55°C 20 years
NRW Write erase cycles TA=25°C 100 cycles
TPROG Programming or erasing tempera-
-40 25 85 °C
TERASE ture range
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.
4. Data based on simulation results, not tested in production.
Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.

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12.7 EMC CHARACTERISTICS should be noted that good EMC performance is

highly dependent on the user application and the
Susceptibility tests are performed on a sample ba- software in particular.
sis during product characterization.
Therefore it is recommended that the user applies
12.7.1 Functional EMS (Electro Magnetic EMC software optimization and prequalification
Susceptibility) tests in relation with the EMC level requested for
Based on a simple running application on the his application.
product (toggling 2 LEDs through I/O ports), the Software recommendations:
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs). The software flowchart must include the manage-
ment of runaway conditions such as:
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until – Corrupted program counter
a functional disturbance occurs. This test – Unexpected reset
conforms with the IEC 1000-4-2 standard.
– Critical Data corruption (control registers...)
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through Prequalification trials:
a 100pF capacitor, until a functional disturbance Most of the common failures (unexpected reset
occurs. This test conforms with the IEC 1000-4- and program counter corruption) can be repro-
4 standard. duced by manually forcing a low state on the RE-
A device reset allows normal operations to be re- SET pin or the Oscillator pins for 1 second.
sumed. The test results are given in the table be- To complete these trials, ESD stress can be ap-
low based on the EMS levels and classes defined plied directly on the device, over the range of
in application note AN1709. specification values. When unexpected behaviour
12.7.1.1 Designing hardened software to avoid is detected, the software can be hardened to pre-
noise problems vent unrecoverable errors occurring (see applica-
tion note AN1015)
EMC characterization and optimization are per-
formed at component level with a typical applica- .
tion environment and simplified MCU software. It
Level/
Symbol Parameter Conditions
Class
Flash device: VDD=5V, TA=+25°C,
4B
Voltage limits to be applied on any I/O pin to induce a fOSC=8MHz, conforms to IEC 1000-4-2
VFESD
functional disturbance ROM device: VDD=5V, TA=+25°C, fO-
3B
SC=8MHz,conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
Flash device: VDD=5V, TA=+25°C, fOSC=8
VFFTB through 100pF on VDD and VDD pins to induce a func- 3B
MHz, conforms to IEC 1000-4-4
tional disturbance
Fast transient voltage burst limits to be applied
Flash device: VDD=5V, TA=+25°C, fOSC=8
VFFTB through 100pF on VDD and VDD pins to induce a func- 3B
MHz, conforms to IEC 1000-4-4
tional disturbance

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EMC CHARACTERISTICS (Cont’d)

12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Monitored Max vs. [fOSC/fCPU] Unit
Symbol Parameter Conditions
Frequency Band 8/4MHz 16/8MHz
0.1MHz to 30MHz 15 15
VDD=5V, TA=+25°C, 30MHz to 130MHz 20 27 dBµV
SEMI Peak level TQFP64 14x14 package
conforming to SAE J 1752/3 130MHz to 1GHz 0 5
SAE EMI Level 2.5 3.0 -
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types.

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EMC CHARACTERISTICS (Cont’d)

12.7.3 Absolute Maximum Ratings (Electrical 12.7.3.1 Electro-Static Discharge (ESD)
Sensitivity) Electro-Static Discharges (a positive then a nega-
Based on three different tests (ESD, LU and DLU) tive pulse separated by 1 second) are applied to
using specific measurement methods, the product the pins of each sample according to each pin
is stressed in order to determine its performance in combination. The sample size depends on the
terms of electrical sensitivity. For more details, re- number of supply pins in the device (3 parts*(n+1)
fer to the application note AN1181. supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C 2000
(Human Body Model)
V
Electro-static discharge voltage
VESD(MM) TA=+25°C 200
(Machine Model)

Notes:
1. Data based on characterization results, not tested in production.
12.7.3.2 Static and Dynamic Latch-Up ■ DLU: Electro-Static Discharges (one positive
■ LU: 3 complementary static tests are required then one negative test) are applied to each pin
on 10 parts to assess the latch-up performance. of 3 samples when the micro is running to
A supply overvoltage (applied to each power assess the latch-up performance in dynamic
supply pin) and a current injection (applied to mode. Power supplies are set to the typical
each input, output and configurable I/O pin) are values, the oscillator is connected as near as
performed on each sample. This test conforms possible to the pins of the micro and the
to the EIA/JESD 78 IC latch-up standard. For component is put in reset mode. This test
more details, refer to the application note conforms to the IEC1000-4-2 and SAEJ1752/3
AN1181. standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Symbol Parameter Conditions Class 1)
TA=+25°C A
LU Static latch-up class TA=+85°C A
TA=+125°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).

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12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
1)
VIL Input low level voltage 0.3xVDD
VIH Input high level voltage 1) CMOS ports 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 2) 0.7
V
VIL Input low level voltage 1) 0.8
VIH Input high level voltage 1) TTL ports 2
Vhys Schmitt trigger voltage hysteresis 2) 1
Injected Current on PC6 (Flash de-
3) vices only) 0 +4
IINJ(PIN)
Injected Current on an I/O pin VDD=5V ±4 mA
Total injected current (sum of all I/O
ΣIINJ(PIN)3) ± 25
and control pins)
IL Input leakage current VSS≤VIN≤VDD ±1
µA
IS Static current consumption Floating input mode4) 400
RPU Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 50 120 250 kΩ
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time 1) CL=50pF 25
ns
tr(IO)out Output low to high level rise time 1) Between 10% and 90% 25
tw(IT)in External interrupt pulse time 6) 1 tCPU

Figure 95. Unused I/O Pins configured as input Figure 96. Typical IPU vs. VDD with VIN=VSS
90
VDD ST7XXX Ta=140°C
80
Ta=95°C
70
10kΩ UNUSED I/O PORT
Ta=25°C
Ta=-45°C
60
Ipu(uA )

50

UNUSED I/O PORT 40

10kΩ
30

ST7XXX 20

10
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of 0
greater EMC robustness and lower cost. 2 2.5 3 3.5 4 4.5 5 5.5 6
V dd(V)

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-
tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to section 12.2.2
on page 166 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 95). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 96).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

12.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Output low level voltage for a standard I/O pin IIO=+5mA 1.2
when 8 pins are sunk at same time
(see Figure 97) IIO=+2mA 0.5
VOL 1) IIO=+20mA, TA≤85°C 1.3
Output low level voltage for a high sink I/O pin

VDD=5V
when 4 pins are sunk at same time TA≥85°C 1.5 V
(see Figure 98 and Figure 100) IIO=+8mA 0.6
Output high level voltage for an I/O pin IIO=-5mA, TA≤85°C VDD-1.4
VOH 2) when 4 pins are sourced at same time TA≥85°C VDD-1.6
(see Figure 99 and Figure 102) IIO=-2mA VDD-0.7

Figure 97. Typical VOL at VDD=5V (standard) Figure 99. Typical VOH at VDD=5V
1.4
5.5

1.2
5

1
V dd-Voh (V) at Vdd=5V
V ol (V ) at Vdd=5V

4.5
0.8
4

0.6
3.5
Ta =14 0°C " V dd= 5V 1 40°C m in
0.4
Ta =95 °C 3 V dd= 5v 95°C m in
Ta =25 °C
0.2 V dd= 5v 25°C m in
Ta =-45 °C
2.5
V dd= 5v -4 5°C m in
0
2
0 0.005 0.01 0.015
Iio(A) -0.01 -0.008 -0.006 -0.004 -0.002 0

Figure 98. Typical VOL at VDD=5V (high-sink)

1

0.9

0.8

0.7
V ol(V ) at Vdd=5V

0.6

0.5

0.4
Ta= 140 °C
0.3
Ta= 95 °C
0.2 Ta= 25 °C

0.1 Ta= -45°C

0
0 0.01 0.02 0.03
Iio(A)
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 100. Typical VOL vs. VDD (standard)
1 0.45
Ta= -4 5°C
Ta=-4 5°C
0.9
Ta= 25°C 0.4 Ta=2 5°C
0.8 Ta= 95°C Ta=9 5°C
Ta= 140 °C 0.35
0.7 Ta=1 40°C
V ol(V ) at Iio=5m A

Vol(V) at Iio=2mA
0.3
0.6

0.5 0.25

0.4 0.2

0.3 0.15
0.2
0.1
0.1
0.05
0
2 2.5 3 3.5 4 4.5 5 5.5 6 0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V )
Vdd(V)

Figure 101. Typical VOL vs. VDD (high-sink)

0 .6 1 .6

1 .4 Ta = 140 °C
0 .5
Ta =95 °C
1 .2 Ta =25 °C

0 .4 Ta =-45°C
1
Vol(V ) at Iio=20m A
Vol(V ) at Iio=8m A

0 .3 0 .8

0 .6
0 .2
Ta= 14 0°C
0 .4
Ta=9 5°C
0 .1 Ta=2 5°C
0 .2
Ta=-45 °C

0 0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6

V dd (V ) V dd(V )

Figure 102. Typical VDD-VOH vs. VDD

5.5 6

Ta= -4 5°C
5
5 Ta= 25°C
Vdd-Voh(V) at Iio=-2m A

Ta= 95°C
Vdd-Voh(V) at Iio=-5mA

4.5
4 Ta= 140°C

4
3
3.5
Ta= -4 5°C
2
3 Ta= 25°C

Ta= 95°C
2.5 1
Ta= 140°C

2
0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V) Vdd(V)

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12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
1)
VIL Input low level voltage 0.16xVDD
V
VIH Input high level voltage 1) 0.85xVDD
Vhys Schmitt trigger voltage hysteresis 2) 2.5
V
VOL Output low level voltage 3) VDD=5V IIO=+2mA 0.2 0.5
IIO Input current on RESET pin 2 mA
RON Weak pull-up equivalent resistor 20 30 120 kΩ
Stretch applied on
0 426) µs
tw(RSTL)out Generated reset pulse duration external pulse
Internal reset sources 20 30 426) µs
4)
th(RSTL)in External reset pulse hold time 2.5 µs
tg(RSTL)in Filtered glitch duration 5) 200 ns

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 103. RESET pin protection when LVD is enabled.1)2)3)4)

VDD ST72XXX

Required Optional RON

(note 3) INTERNAL
EXTERNAL RESET
RESET Filter

0.01µF
1MΩ WATCHDOG
PULSE
GENERATOR
LVD RESET

Figure 104. RESET pin protection when LVD is disabled.1)

Recommended for EMC VDD ST72XXX

VDD VDD

RON
USER 0.01µF 4.7kΩ INTERNAL
EXTERNAL RESET
RESET Filter
CIRCUIT
0.01µF
PULSE
WATCHDOG
GENERATOR
Required

Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the VIL max. level specified in section 12.9.1 on page 185. Otherwise the reset will not be taken into account
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
section 12.2.2 on page 166.
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.

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CONTROL PIN CHARACTERISTICS (Cont’d)

12.9.2 ICCSEL/VPP Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
FLASH versions VSS 0.2
VIL Input low level voltage 1)
ROM versions VSS 0.3xVDD
V
FLASH versions VDD-0.1 12.6
VIH Input high level voltage 1)
ROM versions 0.7xVDD VDD
IL Input leakage current VIN=VSS ±1 µA

Figure 105. Two typical Applications with ICCSEL/VPP Pin 2)

ICCSEL/VPP VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX ST72XXX

Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.

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12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
12.10.1 8-Bit PWM-ART Auto-Reload Timer
Symbol Parameter Conditions Min Typ Max Unit
1 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 125 ns
fEXT ART external clock frequency 0 fCPU/2
MHz
fPWM PWM repetition rate 0 fCPU/2
ResPWM PWM resolution 8 bit
VOS PWM/DAC output step voltage VDD=5V, Res=8-bits 20 mV

12.10.2 16-Bit Timer

Symbol Parameter Conditions Min Typ Max Unit
tw(ICAP)in Input capture pulse time 1 tCPU
2 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 250 ns
fEXT Timer external clock frequency 0 fCPU/4 MHz
fPWM PWM repetition rate 0 fCPU/4 MHz
ResPWM PWM resolution 16 bit

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 ST72F521, ST72521B

12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD, the input/output alternate function characteristics
fCPU, and TA unless otherwise specified. (SS, SCK, MOSI, MISO).

Symbol Parameter Conditions Min Max Unit

Master fCPU/128 fCPU/4
fSCK fCPU=8MHz 0.0625 2
SPI clock frequency MHz
1/tc(SCK) Slave fCPU/2
0
fCPU=8MHz 4
tr(SCK)
SPI clock rise and fall time see I/O port pin description
tf(SCK)
tsu(SS) SS setup time Slave 120
th(SS) SS hold time Slave 120
tw(SCKH) Master 100
SCK high and low time
tw(SCKL) Slave 90
tsu(MI) Master 100
Data input setup time
tsu(SI) Slave 100
ns
th(MI) Master 100
Data input hold time
th(SI) Slave 100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time 90
Slave (after enable edge)
th(SO) Data output hold time 0
tv(MO) Data output valid time 0.25
Master (before capture edge) tCPU
th(MO) Data output hold time 0.25

Figure 106. SPI Slave Timing Diagram with CPHA=0 3)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tf(SCK)
MISO OUTPUT see
see note 2 MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 107. SPI Slave Timing Diagram with CPHA=11)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=1
SCK INPUT

CPOL=0
CPHA=1
CPOL=1

ta(SO) tw(SCKH) tdis(SO)

tw(SCKL) tv(SO) th(SO)
tr(SCK)
tf(SCK)
MISO OUTPUT see see
note 2 HZ MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Figure 108. SPI Master Timing Diagram 1)

SS INPUT
tc(SCK)

CPHA=0
CPOL=0
CPHA=0
SCK INPUT

CPOL=1

CPHA=1
CPOL=0

CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tw(SCKL) tf(SCK)

tsu(MI) th(MI)

MISO INPUT MSB IN BIT6 IN LSB IN

tv(MO) th(MO)

MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2

Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 I2C - Inter IC Control Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD, the input/output alternate function characteristics
fCPU, and TA unless otherwise specified. (SDAI and SCLI). The ST7 I2C interface meets the
requirements of the Standard I2C communication
protocol described in the following table.
Standard mode I2C Fast mode I2C5)
Symbol Parameter Unit
Min 1) Max 1) Min 1) Max 1)
tw(SCLL) SCL clock low time 4.7 1.3
µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0 3) 0 2) 900 3)
tr(SDA) ns
SDA and SCL rise time 1000 20+0.1Cb 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 20+0.1Cb 300
tf(SCL)
th(STA) START condition hold time 4.0 0.6
µs
tsu(STA) Repeated START condition setup time 4.7 0.6
tsu(STO) STOP condition setup time 4.0 0.6 µs
tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 µs
Cb Capacitive load for each bus line 400 400 pF

Figure 109. Typical Application with I2C Bus and Timing Diagram 4)
VDD VDD

4.7kΩ 4.7kΩ 100Ω SDAI

I2 C BUS 100Ω SCLI

ST72XXX
REPEATED START
START
tsu(STA) tw(STO:STA)
START
SDA

tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP

SCK

th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO)

Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
5. At 4MHz fCPU, max.I2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

The following table gives the values to be written in
the I2CCCR register to obtain the required I2C
SCL line frequency.
Table 28. SCL Frequency Table
I2CCCR Value
fSCL fCPU=4 MHz. fCPU=8 MHz.
(kHz) VDD = 4.1 V VDD = 5 V VDD = 4.1 V VDD = 5 V
RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ
400 NA NA NA NA 83h 83 83h 83h
300 NA NA NA NA 85h 85h 85h 85h
200 83h 83h 83h 83h 8Ah 89h 8Ah 8Ah
100 10h 10h 10h 10h 24h 23h 24h 23h
50 24h 24h 24h 24h 4Ch 4Ch 4Ch 4Ch
20 5Fh 5Fh 5Fh 5Fh FFh FFh FFh FFh

Legend:
RP = External pull-up resistance
fSCL = I2C speed
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.

12.11.3 CAN - Controller Area Network Interface

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(CANTX and CANRX).
Symbol Parameter Conditions Min Typ Max Unit
1)
tp(RX:TX) CAN controller propagation time 60 ns

Notes:
1. Data based on simulation results, not tested in production

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12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fADC ADC clock frequency 0.4 2 MHz
VAREF Analog reference voltage 0.7*VDD ≤VAREF ≤VDD 3.8 VDD
1)
V
VAIN Conversion voltage range VSSA VAREF
Positive input leakage current for analog -40°C≤TA≤85°C range ±250 nA
input Other TA ranges ±1 µA
Ilkg VIN<VSS, | IIN |< 400µA
Negative input leakage current on ro-
on adjacent robust ana- 5 6 µA
bust analog pins (ROM devices only)2
log pin
Positive input leakage current for analog -40°C≤TA≤85°C range ±250 nA
input Other TA ranges ±1 µA
Ilkg VIN<VSS, | IIN |< 400µA
Negative input leakage current on ro-
on adjacent robust ana- 5 6 µA
bust analog pins (ROM devices only)2
log pin
RAIN External input impedance see kΩ
CAIN External capacitor on analog input Figure pF
110 and
fAIN Variation freq. of analog input signal Figure Hz
1112)3)4)
CADC Internal sample and hold capacitor 12 pF
Conversion time (Sample+Hold)
tADC 7.5 µs
fCPU=8MHz, SPEED=0 fADC=2MHz
- No of sample capacitor loading cycles 4
tADC 1/fADC
- No. of Hold conversion cycles 11

Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any
conversion being performed on any analog input. Analog pins of flash devices can be protected against negative injection
by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy espe-
cially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC accuracy.

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ADC CHARACTERISTICS (Cont’d)

Figure 110. RAIN max. vs fADC with CAIN=0pF1) Figure 111. Recommended CAIN & RAIN values.2)
45 1000
40 Cain 10 nF
35 2 MHz Cain 22 nF
100
Max. R AIN (Kohm)

Max. R AIN (Kohm)

30 Cain 47 nF
1 MHz
25
10
20

15

10 1

0 0.1
0 10 30 70 0.01 0.1 1 10
CPARASITIC (pF) fAIN(KHz)

Figure 112. Typical A/D Converter Application

VDD
ST72XXX
VT
RAIN 0.6V
AINx 2kΩ(max) 10-Bit A/D
VAIN Conversion

CAIN VT
0.6V IL CADC
±1µA 12pF

Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).

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ADC CHARACTERISTICS (Cont’d)

12.12.1 Analog Power Supply and Reference – Filter power to the analog power planes. It is rec-
Pins ommended to connect capacitors, with good high
Depending on the MCU pin count, the package frequency characteristics, between the power
may feature separate VAREF and VSSA analog and ground lines, placing 0.1µF and optionally, if
power supply pins. These pins supply power to the needed 10pF capacitors as close as possible to
A/D converter cell and function as the high and low the ST7 power supply pins and a 1 to 10µF ca-
reference voltages for the conversion. pacitor close to the power source (see Figure
113).
Separation of the digital and analog power pins al-
low board designers to improve A/D performance. – The analog and digital power supplies should be
Conversion accuracy can be impacted by voltage connected in a star network. Do not use a resis-
drops and noise in the event of heavily loaded or tor, as VAREF is used as a reference voltage by
badly decoupled power supply lines (see Section the A/D converter and any resistance would
12.12.2 General PCB Design Guidelines). cause a voltage drop and a loss of accuracy.
12.12.2 General PCB Design Guidelines – Properly place components and route the signal
traces on the PCB to shield the analog inputs.
To obtain best results, some general design and Analog signals paths should run over the analog
layout rules should be followed when designing ground plane and be as short as possible. Isolate
the application PCB to shield the noise-sensitive, analog signals from digital signals that may
analog physical interface from noise-generating switch while the analog inputs are being sampled
CMOS logic signals. by the A/D converter. Do not toggle digital out-
– Use separate digital and analog planes. The an- puts on the same I/O port as the A/D input being
alog ground plane should be connected to the converted.
digital ground plane via a single point on the
PCB.
Figure 113. Power Supply Filtering

ST72XXX
1 to 10µF 0.1µF VSS

ST7
DIGITAL NOISE
FILTERING
VDD
VDD

POWER
SUPPLY
0.1µF VAREF
SOURCE

EXTERNAL
NOISE
FILTERING VSSA

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10-BIT ADC CHARACTERISTICS (Cont’d)

12.12.3 ADC Accuracy

Conditions: VDD=5V 1)
Symbol Parameter Conditions Typ Max2) Unit
1) 3 4
|ET| Total unadjusted error
1) 2 3
|EO| Offset error
1) 0.5 3 LSB
|EG| Gain Error
1) 1 2
|ED| Differential linearity error CPU in run mode @ fADC 2 MHz.
|EL| Integral linearity error 1) CPU in run mode @ fADC 2 MHz. 1 2
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input. The effect of negative injection current on robust pins is specified in Section
12.12.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC
accuracy.
2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C
to 125°C (± 3σ distribution limits).

Figure 114. ADC Accuracy Characteristics

Digital Result ADCDR EG

(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
AREF SSA
1LSB = --------------------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSSA VAREF

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13 PACKAGE CHARACTERISTICS

13.1 PACKAGE MECHANICAL DATA

Figure 115. 80-Pin Thin Quad Flat Package

mm inches
Dim.
Min Typ Max Min Typ Max
D
A
D1 A2
A 1.60 0.063
A1 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
b 0.22 0.32 0.38 0.009 0.013 0.015
C 0.09 0.20 0.004 0.008
D 16.00 0.630
e

E1 E
D1 14.00 0.551
E 16.00 0.630
E1 14.00 0.551
e 0.65 0.026
θ 0° 3.5° 7° 0° 3.5° 7°

c
L 0.45 0.60 0.75 0.018 0.024 0.030
L1
L L1 1.00 0.039
h
Number of Pins
N 80

Figure 116. 64-Pin Thin Quad Flat Package

D A mm inches
A2
Dim.
D1 Min Typ Max Min Typ Max
A1 A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b b 0.30 0.37 0.45 0.012 0.015 0.018
c 0.09 0.20 0.004 0.008
D 16.00 0.630
e
D1 14.00 0.551
E1 E
E 16.00 0.630
E1 14.00 0.551
e 0.80 0.031
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L
L1 1.00 0.039
L1
c Number of Pins

h N 64

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PACKAGE MECHANICAL DATA (Cont’d)

Figure 117. 64-Pin Thin Quad Flat Package

mm inches
Dim.
D A
Min Typ Max Min Typ Max
D1 A2 A 1.60 0.063

A1
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
b c 0.09 0.20 0.004 0.008
D 12.00 0.472
E1 E D1 10.00 0.394
e
E 12.00 0.472
E1 10.00 0.394
e 0.50 0.020

c
θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.018 0.024 0.030
h
L L1 1.00 0.039
Number of Pins
N 64

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13.2 THERMAL CHARACTERISTICS

Symbol Ratings Value Unit
Package thermal resistance (junction to ambient)
TQFP80 14x14 55
RthJA TQFP64 14x14 47 °C/W
TQFP64 10x10 50

PD Power dissipation 1) 500 mW

2)
TJmax Maximum junction temperature 150 °C

Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.

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13.3 SOLDERING INFORMATION

In accordance with the RoHS European directive, Backward and forward compatibility:
all STMicroelectronics packages will be converted The main difference between Pb and Pb-free sol-
in 2005 to lead-free technology, named ECO- dering process is the temperature range.
PACKTM (for a detailed roadmap, please refer to
PCN CRP/04/744 "Lead-free Conversion Program – ECOPACKTM TQFP packages are fully compat-
- Compliance with RoHS", issued November 18th, ible with Lead (Pb) containing soldering process
2004). (see application note AN2034)
TM – TQFP Pb-packages are compatible with Lead-
■ ECOPACK packages are qualified according
to the JEDEC STD-020B compliant soldering free soldering process, nevertheless it's the cus-
profile. tomer's duty to verify that the Pb-packages max-
■ Detailed information on the STMicroelectronic
imum temperature (mentioned on the Inner box
ECOPACKTM transition program is available on label) is compatible with their Lead-free soldering
www.st.com/stonline/leadfree/, with specific temperature.
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).

Table 29. Soldering Compatibility (wave and reflow soldering process)

Package Plating material devices Pb solder paste Pb-free solder paste
TQFP NiPdAu (Nickel-palladium-Gold) Yes Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.

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14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- shipped to customers with a default content, while
grammable versions (FLASH) as well as in factory ROM/FASTROM factory coded parts contain the
coded versions (ROM/FASTROM). code supplied by the customer. This implies that
ST72521B devices are ROM versions. ST72P521 FLASH devices have to be configured by the cus-
devices are Factory Advanced Service Technique tomer using the Option Bytes while the ROM/FAS-
ROM (FASTROM) versions: they are factory-pro- TROM devices are factory-configured.
grammed HDFlash devices. FLASH devices are

14.1 FLASH OPTION BYTES

STATIC OPTION BYTE 0 STATIC OPTION BYTE 1
7 0 7 0
Reserved

WDG VD OSCTYPE OSCRANGE

PLLOFF
FMP_R

RSTC
PKG0

PKG1
Res.
HALT

SW

1 0 1 0 2 1 0

Default 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1

The option bytes allow the hardware configuration 1: Software (watchdog to be enabled by software)
of the microcontroller to be selected. They have no
address in the memory map and can be accessed OPT5 = Reserved, must be kept at default value.
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the OPT4:3= VD[1:0] Voltage detection
FLASH devices directly using ICP, FLASH devices These option bits enable the voltage detection
are shipped to customers with the internal RC block (LVD, and AVD) with a selected threshold for
clock source. In masked ROM devices, the option the LVD and AVD (EVD+AVD).
bytes are fixed in hardware by the ROM code (see
option list). Selected Low Voltage Detector VD1 VD0

OPTION BYTE 0 LVD and AVD Off 1 1

Lowest Threshold: (VDD~3V) 1 0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated Med. Threshold (VDD~3.5V) 0 1
when entering HALT mode while the Watchdog is Highest Threshold (VDD~4V) 0 0
active. Caution: If the medium or low thresholds are se-
0: No Reset generation when entering Halt mode lected, the detection may occur outside the speci-
1: Reset generation when entering Halt mode fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
OPT6= WDG SW Hardware or software watchdog AVD and LVD threshold levels refer to section
This option bit selects the watchdog type. 12.3.2 on page 168
0: Hardware (watchdog always enabled)

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ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT2 = Reserved, must be kept at default value. OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OPT1= PKG0 Package selection bit 0
This option bit is used to select the package (see OSCTYPE
table in PKG1 option bit description). Clock Source
1 0
Resonator Oscillator 0 0
OPT0= FMP_R Flash memory read-out protection
Read-out protection, when selected, provides a Reserved 0 1
protection against Program Memory content ex- Internal RC Oscillator 1 0
traction and against write access to Flash memo-
ry. External Source 1 1
Erasing the option bytes when the FMP_R option
is selected causes the whole user memory to be OPT3:1 = OSCRANGE[2:0] Oscillator range
erased first, and the device can be reprogrammed. When the resonator oscillator type is selected,
Refer to Section 4.3.1 and the ST7 Flash Pro- these option bits select the resonator oscillator
gramming Reference Manual for more details. current source corresponding to the frequency
Note: Readout protection is not supported if LVD range of the used resonator. Otherwise, these bits
is enabled. are used to select the normal operating frequency
0: Read-out protection enabled range.
1: Read-out protection disabled
OSCRANGE
Typ. Freq. Range
OPTION BYTE 1 2 1 0
OPT7= PKG1 Package selection bit 1 LP 1~2MHz 0 0 0
This option bit, with the PKG0 bit, selects the pack-
age. MP 2~4MHz 0 0 1

Version Selected Package PKG 1 PKG 0 MS 4~8MHz 0 1 0

M TQFP80 1 1 HS 8~16MHz 0 1 1

(A)R TQFP64 1 0 OPT0 = PLLOFF PLL activation

This option bit activates the PLL which allows mul-
Note: On the chip, each I/O port has 8 pads. Pads tiplication by two of the main input clock frequency.
that are not bonded to external pins are in input The PLL must not be used with the internal RC os-
pull-up configuration after reset. The configuration cillator or with external clock source. The PLL is
of these pads must be kept at reset state to avoid guaranteed only with an input frequency between
added current consumption. 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
OPT6 = RSTC RESET clock cycle selection
CAUTION: the PLL can be enabled only if the
This option bit selects the number of CPU cycles
“OSC RANGE” (OPT3:1) bits are configured to
applied during the RESET phase and when exiting
“MP - 2~4MHz”. Otherwise, the device functionali-
HALT mode. For resonator oscillators, it is advised
ty is not guaranteed.
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles

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ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM/FAS- The STMicroelectronics Sales Organization will be
TROM contents and the list of the selected options pleased to provide detailed information on con-
(if any). The ROM/FASTROM contents are to be tractual points.
sent on diskette, or by electronic means, with the 14.2.1 Version-Specific Sales Conditions
S19 hexadecimal file generated by the develop-
ment tool. All unused bytes must be set to FFh. To satisfy the different customer requirements and
to ensure that ST Standard Microcontrollers will
The selected options are communicated to consistently meet or exceed the expectations of
STMicroelectronics using the correctly completed each Market Segment, the Codification System for
OPTION LIST appended. Standard Microcontrollers clearly distinguishes
Refer to application note AN1635 for information products intended for use in automotive environ-
on the counter listing returned by ST after code ments, from products intended for use in non-auto-
has been transferred. motive environments.
It is the responsibility of the Customer to select the
appropriate product for his application.
Figure 118. ROM Factory Coded Device Types
DEVICE PACKAGE VERSION / XXX
Code name (defined by STMicroelectronics)

1 = Standard 0 to +70 °C
3 = Standard -40 to +125 °C
5 = Standard -10 to +85 °C
6 = Standard -40 to +85 °C
A = Automotive -40 to +85 °C
B = Automotive -40 to +105 °C
C = Automotive -40 to +125 °C

T= Plastic Thin Quad Flat Pack

ST72521BR9, ST72521BR6
ST72521BAR9, ST72521BAR6
ST72521BM9

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ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

ST72521B MICROCONTROLLER OPTION LIST
(Last update: December 2004)
Customer: ................................
Address: ................................
................................
Contact: ................................
Phone No: ................................
Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . .
*The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- | ------------------------------------- | -------------------------------------
ROM DEVICE: 60K 32K
--------------------------------- | ------------------------------------- | -------------------------------------
TQFP80: | [ ] ST72521BM9 |
TQFP64 14x14: | [ ] ST72521BR9 | [ ] ST72521BR6
TQFP64 10x10: | [ ] ST72521BAR9 | [ ] ST72521BAR6
--------------------------------- | -------------------------------------- | -------------------------------------
DIE FORM: 60K 32K
--------------------------------- | -------------------------------------- | --------------------------------------
80-pin: | [] |
64-pin: | [] | []
Conditioning (check only one option):
------------------------------------------------------------------------ | -----------------------------------------------------
Packaged Product
------------------------------------------------------------------------ Die Product (dice tested at 25°C only)
| -----------------------------------------------------
[ ] Tape & Reel [ ] Tray | [ ] Tape & Reel
| [ ] Inked wafer
| [ ] Sawn wafer on sticky foil
Version/ Temp. Range (do not check for die product). Please refer to datasheet for specific sales conditions:
----------------------------- | ------------------------------------------- | -------------------------------------------
Standard Automotive Temp. Range
----------------------------- | ------------------------------------------- | -------------------------------------------
[] | | [ ] 0°C to +70°C
[] | | [ ] -10°C to +85°C
[] | [] | [ ] -40°C to +85°C
| [] | [ ] -40°C to +105°C
| [] | [ ] -40°C to +125°C
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Clock Source Selection:

[ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal RC:
[ ] External Clock
PLL [ ] Disabled [ ] Enabled
LVD Reset [ ] Disabled [ ] High threshold [ ] Med. threshold [ ] Low threshold
Reset Delay [ ] 256 Cycles [ ] 4096 Cycles
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
Watchdog Reset on Halt: [ ] Reset [ ] No Reset
Readout Protection: [ ] Disabled [ ] Enabled

Date ................................
Signature ................................

Please download the latest version of this option list from:

http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 30. Orderable Flash Device Types
Flash
Part Number Version Package Memory Temp. Range
(Kbytes)
ST72F521AR6TC 32
TQFP64 10 x 10
ST72F521AR9TC 60
ST72F521R6TC Automotive 32 -40°C +125°C
TQFP64 14 x 14
ST72F521R9TC 60
ST72F521M9TC TQFP80 60
ST72F521AR6T3 32
TQFP64 10 x 10
ST72F521AR9T3 60
ST72F521R6T3 Standard 32 -40°C +125°C
TQFP64 14 x 14
ST72F521R9T3 60
ST72F521M9T3 TQFP80 60
ST72F521AR6T6 32
TQFP64 10 x 10
ST72F521AR9T6 60
ST72F521R6T6 Standard 32 -40°C +85°C
TQFP64 14 x 14
ST72F521R9T6 60
ST72F521M9T6 TQFP80 60

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.3 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware and a specific demo board for ST72521
and software development tools for the ST7 micro- (TQFP64)
controller family. Full details of tools available for ■ STxF-INDART
the ST7 from third party manufacturers can be ob-
tained from the STMicroelectronics Internet site: Flash Programming tools
http//www.st.com. ■ ST7-STICK ST7 In-circuit Communication Kit, a
complete software/hardware package for
Tools from these manufacturers include C compli-
programming ST7 Flash devices. It connects to
ers, evaluation tools, emulators and programmers.
a host PC parallel port and to the target board or
Emulators socket board via ST7 ICC connector.
Two types of emulators are available from ST for ■ ICC Socket Boards provide an easy to use and
the ST725 family: flexible means of programming ST7 Flash
■ ST7 DVP3 entry-level emulator offers a flexible devices. They can be connected to any tool that
and modular debugging and programming supports the ST7 ICC interface, such as ST7
solution. SDIP42 & SDIP32 probes/adapters EMU3, ST7-DVP3, inDART, ST7-STICK, or
are included, other packages need a specific many third-party development tools.
connection kit (refer to Table 31) Evaluation boards
■ ST7 EMU3 high-end emulator is delivered with Three different Evaluation boards are available:
everything (probes, TEB, adapters etc.) needed
■ ST7232x-EVAL ST72F321/325/521 evaluation
to start emulating the ST725. To configure it to
emulate other ST7 subfamily devices, the active board, with ICC connector for programming
capability. Provides direct connection to ST7-
probe for the ST7EMU3 can be changed and
DVP3 emulator. Supplied with daughter boards
the ST7EMU3 probe is designed for easy
interchange of TEBs (Target Emulation Board). (core module) for ST72F321, ST72F324,
ST72325 & ST72F521 (the ST72F32x chips are
See Table 31.
not included)
In-circuit Debugging Kit 1
■ ST7MDT20-EVC/xx with CAB TQFP64 14x14
Two configurations are available from ST: socket
■ STXF521-IND/USB: Low-cost In-Circuit 1
■ ST7MDT20-EVY/xx with Yamaichi TQFP64
Debugging kit from Softec Microsystems. 10x10 socket
Includes STX-InDART/USB board (USB port)
Table 31. STMicroelectronics Development Tools
Emulation Programming
Supported ST7 DVP3 Series ST7 EMU3 series
Products Active Probe & ICC Socket Board
Emulator Connection kit Emulator
T.E.B.
ST72521M, ST7MDT20-T80/
ST72F521M DVP
ST72521AR, ST7MDT20-T6A/ ST7MDT20M-
ST7MDT20-DVP3 ST7MDT20M-TEB ST7SB20M/xx1
ST72F521AR DVP EMU3
ST72521R, ST7MDT20-T64/
ST72F521R DVP

Note 1: Add suffix /EU, /UK, /US for the power supply of your region.

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 32. Suggested List of Socket Types
Socket (supplied with ST7MDT20M- Emulator Adapter (supplied with
Device
EMU3) ST7MDT20M-EMU3)
TQFP64 14 x14 CAB 3303262 CAB 3303351
TQFP64 10 x10 YAMAICHI IC149-064-*75-*5 YAMAICHI ICP-064-6
TQFP80 14 X 14 YAMAICHI IC149-080-*51-*5 YAMAICHI ICP-080-7

14.3.1 Socket and Emulator Adapter TQFP64 10 x 10 and TQFP80 14 x 14 and

Information www.cabgmbh.com for TQFP64 14 x 14)
For information on the type of socket that is sup- Related Documentation
plied with the emulator, refer to the suggested list AN 978: ST7 Visual Develop Software Key Debug-
of sockets in Table 32. ging Features
Note: Before designing the board layout, it is rec- AN 1938: ST7 Visual Develop for ST7 Cosmic C
ommended to check the overall dimensions of the toolset users
socket as they may be greater than the dimen-
sions of the device. AN 1939: ST7 Visual Develop for ST7 Metroworks
C toolset users
For footprint and other mechanical information
about these sockets and adapters, refer to the AN 1940: ST7 Visual Develop for ST7 Assembler
manufacturer’s datasheet (www.yamaichi.de for Linker toolset users

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14.4 ST7 APPLICATION NOTES

Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658 SERIAL NUMBERING IMPLEMENTATION
AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 EMULATED 16 BIT SLAVE SPI
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
AN1753 SOFTWARE UART USING 12-BIT ART
AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY

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 ST72F521, ST72521B

Table 33. ST7 Application Notes

IDENTIFICATION DESCRIPTION
GENERAL PURPOSE
AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES
AN1526 ST7FLITE0 QUICK REFERENCE NOTE
AN1709 EMC DESIGN FOR ST MICROCONTROLLERS
AN1752 ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264
PRODUCT OPTIMIZATION
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
AN1530
TOR
AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
AN1971 ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039 ST7 MATH UTILITY ROUTINES
AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER

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ST72F521, ST72521B

Table 33. ST7 Application Notes

IDENTIFICATION DESCRIPTION
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
AN1179
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION
AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

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 ST72F521, ST72521B

15 KNOWN LIMITATIONS

15.1 ALL FLASH AND ROM DEVICES The symptom does not occur when the interrupts
are handled normally, i.e.
15.1.1 External RC option
when:
The External RC clock source option described in
previous datasheet revisions is no longer support- – The interrupt flag is cleared within its own inter-
ed and has been removed from this specification. rupt routine
15.1.2 Safe Connection of OSC1/OSC2 Pins – The interrupt flag is cleared within any interrupt
routine
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may – The interrupt flag is cleared in any part of the
start and, in this configuration, could generate an code while this interrupt is disabled
fOSC clock frequency in excess of the allowed If these conditions are not met, the symptom can
maximum (>16MHz.), putting the ST7 in an un- be avoided by implementing the following se-
safe/undefined state. Refer to section 6.2 on page quence:
25. Perform SIM and RIM operation before and after
15.1.3 Reset pin protection with LVD Enabled resetting an active interrupt request.
As mentioned in note 2 below Figure 103 on page Example:
186, when the LVD is enabled, it is recommended SIM
not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise reset interrupt flag
on the reset line. RIM
15.1.4 Unexpected Reset Fetch Nested interrupt context:
If an interrupt request occurs while a “POP CC” in- The symptom does not occur when the interrupts
struction is executed, the interrupt controller does are handled normally, i.e.
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the when:
CPU. – The interrupt flag is cleared within its own inter-
Workaround rupt routine
To solve this issue, a “POP CC” instruction must – The interrupt flag is cleared within any interrupt
always be preceded by a “SIM” instruction. routine with higher or identical priority level
15.1.5 Clearing active interrupts outside – The interrupt flag is cleared in any part of the
interrupt routine code while this interrupt is disabled
When an active interrupt request occurs at the If these conditions are not met, the symptom can
same time as the related flag is being cleared, an be avoided by implementing the following se-
unwanted reset may occur. quence:
Note: clearing the related interrupt mask will not PUSH CC
generate an unwanted reset SIM
Concurrent interrupt context reset interrupt flag
POP CC

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ST72F521, ST72521B

KNOWN LIMITATIONS (Cont’d)

15.1.6 SCI Wrong Break duration 15.1.7 16-bit Timer PWM Mode
Description In PWM mode, the first PWM pulse is missed after
A single break character is sent by setting and re- writing the value FFFCh in the OC1R register
setting the SBK bit in the SCICR2 register. In (OC1HR, OC1LR). It leads to either full or no PWM
some cases, the break character may have a long- during a period, depending on the OLVL1 and
er duration than expected: OLVL2 settings.
- 20 bits instead of 10 bits if M=0 15.1.8 CAN Cell Limitations
- 22 bits instead of 11 bits if M=1. Limitation1 Flash ROM
In the same way, as long as the SBK bit is set, Omitted SOF bit x x
break characters are sent to the TDO pin. This CPU write access
may lead to generate one break more than expect- (more than one cycle) x x
ed. corrupts CAN frame
Unexpected Mes-
Occurrence x2
sage transmission
The occurrence of the problem is random and pro- Bus Off State Not En-
portional to the baudrate. With a transmit frequen- x4
tered
cy of 19200 baud (fCPU=8MHz and SCI-
WKPS Functionality x3
BRR=0xC9), the wrong break duration occurrence
is around 1%.
x=limitation present
Workaround 1
For details see section 10.8.5 on page 146
If this wrong duration is not compliant with the 2
communication protocol in the application, soft- Software workaround possible using modified
ware can request that an Idle line be generated WKPS bit.
3Functionality modified for Unexpected Message
before the break character. In this case, the break
duration is always correct assuming the applica- Transmission workaround in Flash.
tion is not doing anything between the idle and the 4
Limitation present on ROM Rev W and Rev Z.
break. This can be ensured by temporarily disa- Not present in Flash and ROM Rev Y.
bling interrupts.
15.1.9 I2C Multimaster
The exact sequence is:
In multimaster configurations, if the ST7 I2C re-
- Disable interrupts ceives a START condition from another I2C mas-
- Reset and Set TE (IDLE request) ter after the START bit is set in the I2CCR register
- Set and Reset SBK (Break Request) and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
- Re-enable interrupts from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication

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 ST72F521, ST72521B

KNOWN LIMITATIONS (Cont’d)

15.2 ALL FLASH DEVICES modes are critical because the I/Os PG[7:0] and
PH[7:0] are forced to output push-pull.
15.2.1 Internal RC Oscillator with LVD
Impact on the Application
The internal RC can only be used if LVD is ena-
bled. The PG and PH I/O ports are forced to output
push-pull during three pulses on ICCDATA. In cer-
15.2.2 I/O behaviour during ICC mode entry tain circumstances, this behaviour can lead to a
sequence short-circuit between the I/O signals and VDD, VSS
Symptom or an output signal of another application compo-
In 80-pin devices (Flash), both Port G and H are nent.
forced to output push-pull during ICC mode entry In addition, switching these I/Os to output mode
sequence. 80-pin ROM devices are not impacted can cause the application to leave reset state, dis-
by this issue. turbing the ICC communication and preventing the
Details user from programming the flash.
To enable programming of all flash sectors, the
device must leave USER mode and be configured 15.2.3 Read-out protection with LVD
in ICC mode. Once in ICC mode, the ICC protocol The LVD is not supported if Readout protection is
enables an ST7 microcontroller to communicate enabled.
with an external controller (such as a PC). ICC
mode is entered by applying 39 pulses on the IC-
CDATA signal during reset. To enter ICC mode,
the device goes through other modes, some

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ST72F521, ST72521B

16 REVISION HISTORY
Table 34. Revision History
Date Revision Description of Changes
Added Figure 82 on page 153
Reinstated “I/O behaviour during ICC mode entry sequence” on page 213
7-Dec-2004 3
Reinstated “BUSOFF not entered” in “CAN Cell Limitations” on page 212
Added “flash only” to PC6 Iinj spec in Section 12.2 and Section 12.8
Added Note on SMbus to Section 10.7
Static current consumption modified in section 12.8 on page 182
4-Mar-2005 4 Updated footnote and Figure 103 and Figure 104 on page 186
Modified VtPOR in section 12.3.2 on page 168
Added note 4 below Table of “CAN Cell Limitations” on page 212
Corrected MCO description in Table 1 and Section 10.2
Updated footnotes and Figure 103 and Figure 104 on page 186.
Updated soldering information in section 13.3 on page 200
18-May-2005 5
Added Suffix 3 to Figure 118 on page 203
Updated partnumbers in Table 30 on page 205
Added “Reset pin protection with LVD Enabled” on page 211

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ST72F521, ST72521B

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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