processes

Article
An Optimal Switching Sequence Model Predictive Control
Scheme for the 3L-NPC Converter with Output LC Filter
Felipe Herrera 1 , Andrés Mora 2 , Roberto Cárdenas 1, * , Matías Díaz 3 , José Rodríguez 4 and Marco Rivera 5,6

1 Electrical Engineering Department, University of Chile, Avda. Beauchef 851, Santiago 8370451, Chile;
felherrera@ug.uchile.cl
2 Electrical Engineering Department, Universidad Técnica Federico Santa María, Valparaíso 2390123, Chile;
andres.mora@usm.cl
3 Electrical Engineering Department, University of Santiago of Chile, Santiago 9170125, Chile;
matias.diazd@usach.cl
4 Engineering Faculty, Universidad San Sebastian, Santiago 4080871, Chile; jose.rodriguezp@uss.cl
5 Power Electronics, Machines and Control (PEMC) Research Group, Department of Electrical and Electronic
Engineering, Faculty of Engineering, University of Nottingham, 15 Triumph Rd, Lenton,
Nottingham NG7 2GT, UK; marcoriv@utalca.cl or marco.rivera@nottingham.ac.uk
6 Laboratorio de Conversión de Energías y Electrónica de Potencia (LCEEP), Universidad de Talca, Merced 437,
Curicó 3341717, Chile
* Correspondence: rcardenas@ing.uchile.cl

Abstract: In some applications of microgrids and distributed generation, it is necessary to feed

islanded or stand-alone loads with high-quality voltage to provide low total harmonic distortion
(THD). To fulfil these demands, an LC filter is usuallyconnected to the output terminals of power
electronics converters. A cascaded voltage and current control loop with pulse-width modulation
schemes are used to regulate the voltages and currents in these systems. However, these strategies
have some drawbacks, particularly when multiple-input–multiple-output plants (MIMO) are con-
trolled using single-input–single-output (SISO) design methods. This methodology usually produces
a sluggish transient response and cross–coupling between different control loops and state variables.
In this paper, a model predictive control (MPC) strategy based on the concept of optimal switching
Citation: Herrera, F.; Mora, A.;
sequences (OSS) is designed to control voltage and current in an LC filter connected to a three-level
Cárdenas, R.; Díaz, M.; Rodríguez, J.;
neutral-point clamped converter. The strategy solves an optimisation problem to achieve control
Rivera, M. An Optimal Switching
of the LC filter variables, i.e., currents and output voltages. Hardware-in-the-loop (HIL) results are
Sequence Model Predictive Control
Scheme for the 3L-NPC Converter
obtained to validate the feasibility of the proposed strategy, using a PLECS–RT HIL platform and
with Output LC Filter. Processes 2024, a dSPACE Microlab Box controller. In addition to the good dynamic performance of the proposed
12, 348. https://doi.org/10.3390/ OSS–MPC, it is demonstrated using HIL results that the control algorithm is capable of obtaining low
pr12020348 total harmonic distortion (THD) in the output voltage for different operating conditions.

Academic Editors: Bahaa Saleh, Fadl

Keywords: model predictive control (MPC); optimal switching sequence (OSS); multilevel inverters;
A. Essa and Hsin-Jang Shieh
optimal control
Received: 10 December 2023
Revised: 28 January 2024
Accepted: 31 January 2024
Published: 6 February 2024 1. Introduction
When power converters are utilised to supply electrical energy to islanded loads, in
microgrids or distributed generation applications, typically an LC filter is connected at
Copyright: © 2024 by the authors.
the converter outputs [1]. For instance, converters augmented by LC filters are used in
Licensee MDPI, Basel, Switzerland. applications such as uninterruptible power supplies (UPS) [2], energy storage systems [3],
This article is an open access article motor drives [4,5], microgrids [6–8], wind energy systems [9], etc.
distributed under the terms and When SISO control tools are utilised to design the control systems of power converters
conditions of the Creative Commons equipped with LC filters, typically two cascaded PI or PR control loops are required:
Attribution (CC BY) license (https:// an outer voltage control loop and an inner current control loop [1,10]. The voltage loop
creativecommons.org/licenses/by/ computes the reference for the inner current loop, and the current loop computes the desired
4.0/). converter voltage to be synthesized by a pulse-width modulation (PWM) scheme. However,

Processes 2024, 12, 348. https://doi.org/10.3390/pr12020348 https://www.mdpi.com/journal/processes

Processes 2024, 12, 348 2 of 25

as discussed in [6], the cascaded interconnection of the voltage and current control loops
has some drawbacks. Firstly, because SISO design tools are used, the inner and outer loops
are separately designed with different bandwidths to avoid cross–couplings between the
dynamics of the voltage and current control loops (usually, the outer loop is one order
of magnitude slower than the inner loop). This produces a relatively slower transient
response. Secondly, the controllers must be carefully tuned because their parameters affect
the system’s dynamic response. To overcome the drawbacks of cascaded linear controllers,
model predictive control schemes, which are MIMO systems, have recently been proposed.
Model predictive control (MPC) has been garnering growing interest in the realm
of power electronics converter applications. Most common applications include grid-
connected converters, inverters with RL loads, inverters with output LC filters, and high-
performance drives [11]. MPC has several advantages, such as simplicity for the inclusion
of nonlinearities, simple treatment of constraints, the multivariable case and stochastic case
can be easily considered [12], dead times can be compensated [13,14], etc. On the other
hand, the disadvantage of some MPC algorithms, for instance, finite set MPC (or FS–MPC),
is their relatively high computational load, particularly in power converter topologies
where a large number of vectors are available. However, the exponential development
in the processing power of microprocessors (such as digital signal processors and field-
programmable gate arrays) has allowed the implementation of MPC algorithms in real-time
platforms [14,15].
A wide variety of MPC algorithms for power electronics converters exist. An MPC
algorithm can be considered, in general terms, as any algorithm that uses a model of
the system to predict its future behaviour and select the most appropriate control action
based on the solution to an optimal criterion [16]. The optimal criterion is evaluated in a
cost function and can be, for example, tracking of the system state variables, minimising
common-mode voltage, or reducing the converter switching frequency [16,17]. After
the optimal criterion has been reached, and consequently the best possible solution to
the optimisation problem has been obtained, the algorithm sends it to the converter to
be synthesised.
MPC algorithms are classified according to the nature of the optimisation variable in
the control problem. In broad terms, these algorithms for power electronics are classified
as direct MPC or indirect MPC methods [17]. In direct MPC methods, the optimisation
variable is an integer-valued vector representing the state of the converter switching device.
Conversely, in indirect MPC the optimisation variable is a real-valued vector representing
the fundamental component of the converter output voltage or duty cycles.
Direct MPC methods are subdivided into three categories: optimal switching vector
MPC (OSV–MPC), MPC with hysteresis bounds, and MPC with an implicit modulator.
OSV-MPC, commonly named finite control set MPC (FCS–MPC) in the literature, was first
proposed to control the output current of a two-level inverter connected to an RL load [18].
Since then, it has been applied to many converter topologies [16]. In this strategy, the
converter switches are directly computed and sent to the converter, thus allowing direct
manipulation of the controlled variables. The advantages of OSV-MPC are an intuitive
design procedure, straightforward implementation, and fast transient response [17]. How-
ever, they come at the cost of high computational complexity, particularly for multilevel
power converters, and variable switching frequency due to the absence of a modulator [19].
Direct MPC methods with implicit modulators have been proposed to overcome
the issue of variable switching frequency introduced by OSV-MPC while maintaining its
advantages [20,21]. These strategies attempt to emulate the behaviour of pulse-width
modulation techniques. In particular, optimal switching sequence MPC (OSS–MPC) and
modulated MPC (M2 PC) introduce the concept of variable switching time instants [17].
According to the concept of variable switching time instants, the position of the converter
switches can change at any moment during a sampling interval. Then, the strategies
compute a sequence of switch positions and their corresponding duty cycles to be applied
during the next sampling interval. Thus, a fixed switching frequency is achieved, resulting
Processes 2024, 12, 348 3 of 25

in a reduction of harmonic distortion [17]. However, M2 PC is prone to suboptimality

because the optimisation problem is solved in two stages: the first stage is to find the
optimal switch positions and the second stage is to compute the duty cycles [22].
OSS–MPC avoids suboptimal solutions by computing the optimal sequence of switch
positions and their corresponding duty cycles in one stage. The strategy was first introduced
for power control of a grid-connected two-level inverter [21]. Then, the strategy was
modified to be used in other converter topologies, such as a three-level neutral-point-
clamped (3L-NPC) inverter and Vienna rectifier [23–26]. In [27], OSS–MPC was used for
voltage control of an LC-filtered two-level inverter, achieving low output voltage ripple
and reduced harmonic content compared to other MPC methods (such as OSV–MPC).
In this paper, the OSS–MPC presented in [26] is extended to three-level neutral-point-
clamped (3L-NPC) inverters with output LC filters in stand-alone operation (such as UPS).
The strategy uses a prediction model based on the improved-Euler method to compute the
future value of the load output voltage and inductor filter current. The predicted values
are compared against the desired reference values in the cost function of an optimisation
problem. The cost function penalises the deviation between the measured values and the
reference values, and also the control effort of the converter. The optimisation problem is
solved offline to compute an optimal switching sequence to be applied by the converter.
The optimal switching sequence is then transformed into a three-phase reference signal,
which is used in an optimisation problem, to compute an optimal common-mode voltage to
balance the DC-link capacitors of the converter. The common-mode voltage is then added
to the three-phase reference signal, using the methodology already discussed in [26], and
the resulting optimal three-phase reference is sent to an in-phase disposition PWM scheme
to generate the pulses of the switching devices.
The contributions of this work are as follows:
• A new OSS–MPC algorithm is proposed for the control of a 3L-NPC converter feeding
an LC-filtered stand-alone load. It is shown that the system is more complex to regulate
than the grid-connected applications discussed in [24,26], where typically only two
state variables, the α − β current components, are regulated. Conversely, for an LC-
filtered stand-alone load, there are two more state variables, the α − β components
of the inductance currents and load voltages, and the system is not reachable using a
one-step horizon OSS–MPC (for a discussion of reachability, see [28]). Moreover, as
discussed in Section 3.2.1, the forward-Euler discretisation algorithm may produce
some performance issues when implementing current and voltage control for an
LC-filtered stand-alone load.
• It is shown in this work that the proposed OSS–MPC, based on the improved-Euler
discretisation method, can simultaneously control the 3L-NPC converter output cur-
rent and load voltage with good tracking of the references (see the final paragraphs of
Section 3.2.1). This is not considered in previously reported OSS–MPCs [27], where
good output-current regulation is neglected, focusing mainly on load-voltage control.
Moreover, in [27] the solution to the optimal problem is obtained using an extensive
search of all the space vectors available in the 3L-NPC converter. Conversely, in this
work a simpler methodology with a much lesser computational burden is applied to
obtain the optimal solution (see Section 5.2).
• It is shown in this work that the proposed methodology can achieve good performance
for linear and nonlinear loads. This is extensively demonstrated using HIL results.
Moreover, in Section 8 it is shown that the OSS–MPC proposed in this work outper-
forms the OSS–MPC strategy reported in [27] for several tests, including applications
involving nonlinear loads.
The rest of this paper is organised as follows. Section 2 presents the 3L-NPC converter
topology, including modelling and modulation issues. Section 3 discusses the OSS–MPC
algorithms used in this work, including state variable modelling of the system and the
forward-Euler and improved-Euler discretisation methods. The advantages of improved-
Euler, when compared to forward-Euler, are further addressed in Section 3.2.1. Section 4
Processes 2024, 12, 348 4 of 25

discusses further details of the OSS–MPC proposed in this work, including the cost function;
meanwhile, solving the optimal problem and reaching the optimal solution are discussed
in Section 5 and Section 5.2, respectively.
Section 6 discusses an optimisation algorithm to calculate the common-mode voltage.
This has already been discussed in [26] but, for completeness, is briefly discussed in this
section. Section 7 presents the hardware-in-the-loop (HIL) system utilized to validate the
proposed control strategy as well as the results obtained with the HIL platform. In Section 8,
the performance of the proposed OSS–MPC algorithm is compared with that obtained with
the state-of-the-art OSS–MPC reported in [27]. Finally, an appraisal of the work is discussed
in the conclusions.

2. The 3L-NPC Inverter

The 3L-NPC inverter was the first multilevel converter topology, proposed by the
group of Akagi in [29]. It was introduced around 1980 to reduce the pulsating torque and
harmonic losses on AC drives, thus improving the efficiency and reducing the cost of the
system. Nowadays, this converter topology is the standard for medium- and high-voltage
applications [30,31]. In the mining industry, for example, 3L-NPC converters are used in
variable frequency drives (VFD) for long belt-conveyor systems carrying ore [32].
As shown in the circuit diagram in Figure 1a, the 3L-NPC converter is composed
of four switches and two clamped diodes per leg, producing a total of 27 three-phase
switching states, uabc , for the whole converter, where uabc ∈U≜{−1, 0, 1}3 . As depicted in
Figure 1b, these switching states produce 19 non-redundant and 8 redundant switching
vectors (SVs), us , in the αβ frame, where us =Tαβ uabc and Tαβ is the amplitude invariant
abc-to-αβ transformation [33].

3L-NPC

LC filter

(a)

-+- 0+- ++-

6
-+0 -0- 00- +0-
0+0 ++0
5
4 2
0 1 1 1
1
3
-00 +++ 0--
-++ +--
0++ 000
--- +00 0 0 1 1

-0+ --0
00+
0-0
+0+ +-0 -1 -1 -1 0

--+ 0-+ +-+

(b) (c)

Figure 1. 3L-NPC converter: (a) topology; (b) space of switching vectors; (c) 7S-SS for the region R6 .

According to the circuit diagram depicted in Figure 1a, the inverter voltages,
 ⊺
vabc = vao vbo vco , are provided by
1
vabc = V u + (1 − |uabc |)vn (1)
2 dc abc
Processes 2024, 12, 348 5 of 25

⊺
where |uabc |= |ua | |ub | |uc | and vn = 12 (vC2 − vC1 ) is the NP-voltage. Using the transfor-


mation, Tαβ , the inverter voltages (1) in the stationary αβ frame can be expressed as

1
V us − Tαβ |uabc |vn .
vs = (2)
2 dc
On the other hand, for a three-phase load with a floating neutral, the NP-voltage
evolves as a function of the NP-current, in , according to

dvn
(C1 +C2 ) = in , in = |uabc |⊺ iabc (3)
dt
⊺
Therefore, for a given output current, iabc = ias ibs ics , as shown in (3), only small- and


medium-size SVs, uS and uM (see Figure 1b) respectively, can affect the NP-voltage [34].
However, to balance the NP voltage, small SVs play a significant role because the redun-
dancy of each SV drives an NP-current of the same amplitude but in the opposite direction.
This tendency impacts vn but not vs when the capacitors are balanced with a negligible
voltage ripple, i.e., vn ≈ 0.
To synthesize a desired inverter output voltage, the three nearest SVs are typically
employed in carrier-based and space-vector PWM techniques [34,35]. Due to the presence
of redundancies, several switching sequences (or switching patterns) can synthesize the
desired output voltage. Therefore, the generation of switching sequences can be used
for several purposes, such as to reduce the switching frequency and to minimize the
NP-voltage ripple [34].
Based on the above analysis, the seven-segment switching sequence (7S-SS) [34] will
be adopted in this work to implement the OSS–MPC strategy for voltage and current
control. This switching pattern consists of four SVs, which are arranged in such a way that
the transition between two adjacent switching states demands only one switching action.
Additionally, each switching period is split into two sub-cycles of duration T0 = Ts /2,
in which the disposition of the second sub-cycle is a reversal of the arrangement of the
first [34], as shown in the example in Figure 1c. Furthermore, the first sub-cycle starts with
an N-type small-size SV (uS− ) and ends with the P-type redundancy (uS+ ). Therefore, each
7S-SS candidate can be defined accordingly as
n o
S ≜ uS− [t0 ], u1 [t1 ], u2 [t2 ], uS+ [2t3 ], u2 [t2 ], u1 [t1 ], uS− [t0 ] (4)

where ti is the time in which the ith switching vector is synthesized by the converter, as
depicted in Figure 1c.
Since the twelve internal regions (highlighted in grey in Figure 1b) have two N-type
small-size SVs, each of them is further partitioned into two sub-regions to reduce the
NP-voltage ripple [34]. Thus, to determine which dominant N-type small-size SV should
be utilised to assemble the desired switching sequence, the space of SVs is divided into
36 regions, as shown in Figure 1b. Then, according to the OSS–MPC principles, a 7S-SS
candidate is denoted as S j , where j ∈ R≜{1, . . . , 36}.

3. OSS-MPC Strategy for Voltage and Current Control

In this work, an OSS–MPC scheme will be employed to simultaneously control the
voltage and current at an LC filter, while maintaining balanced voltages at the capacitors of
the DC-link in a 3L-NPC converter. The overall controller is a predictive control scheme
based on the solution to two optimisation problems.
The proposed control scheme is shown in Figure 2. The first optimisation prob-
lem—hereinafter called the outer optimisation loop—computes the optimal switching
vectors sequence and duty cycles that minimize a cost function. The cost function is de-
signed to track the desired values of the state vector and minimize the control effort of the
converter. The second optimisation problem—hereinafter called the NP-voltage optimisa-
tion loop—computes an optimal common-mode injection signal (see bottom left-hand side
Processes 2024, 12, 348 6 of 25

of Figure 2). The common-mode injection signal is designed to balance the neutral-point
voltage between the DC-link capacitors. Notice that the NP-voltage optimisation loop
presented in this work has already been discussed in [26]. However, for completeness, it is
briefly summarised in Section 6.

Load

PWM
3 Ref.
OSS State
NP-Voltage MPC
Control

Figure 2. Proposed control system, composed of an MPC where the load voltage and the converter’s
output current are controlled in a single-stage MPC. The common-mode voltage is obtained using a
second MPC algorithm, as already discussed in [26].

3.1. Continuous-Time Model

Let us consider a three-phase 3L-NPC converter connected to an LC filter, as shown in
Figure 1a. The system of differential equations describing the dynamics of the LC filter can
be written as
αβ
dis αβ αβ
Lf + R f i s = vs − vo (5a)
dt
αβ
dvo αβ αβ
Cf = is − io (5b)
dt
Assuming that the DC-link NP-voltage is balanced (i.e., vn = 0), the converter output
voltage in (2) is equal to vs = V2dc us . Moreover, by rearranging the equations and defining
β β β
the state, input, and disturbance vectors as xs = [isα is vαo vo ]⊺ , us = [uαs us ]⊺ , and
β
io = [ioα io ]⊺ (The superscripts αβ in the vectors will be avoided to simplify the notation),
the state-space model of the AC side dynamics is then calculated as

ẋs = Axs + Bus + Eio (6a)

y = Cxs (6b)

Matrices A, B, and E contain the parameters of the filter and matrix C is the iden-
tity matrix.
" # " #
− L −1 R − L −1
 V −1 
dc
L 0
A= B= 2 E= (7)
C− f
1
0 0 −C−f 1

The resistance, inductance, and capacitance matrices are defined as follows:

R = R f I2 L = L f I2 C f = C f I2 (8)

The dimensions of the system matrices are A ∈ R4×4 , B ∈ R4×2 , E ∈ R4×2 ,

xs (t) ∈ R4×1 , us (t) ∈ R2×1 , and io (t) ∈ R2×1 .
Processes 2024, 12, 348 7 of 25

3.2. Discrete-Time Model

MPC algorithms use the discrete-time mathematical model of the system to make
predictions of the state-vector trajectory, then utilise the predicted values in an optimisation
problem and compute the best control action that fulfils the control objectives.
Typically, for the discrete implementation of the continuous-time model, the forward-
Euler method is applied, and this is briefly reviewed below. However, the forward-Euler
methodology has some disadvantages for the control of LC-filtered stand-alone loads, and
this is further discussed at the end of Section 3.2.1.

3.2.1. Forward-Euler-Based Discrete Time Model

It is assumed in this work that a 7S-SS is applied to the converter during every
switching cycle. Considering the forward-Euler method, the instantaneous trajectory of the
state vector when a switching vector is applied can be computed as

xs(ℓ+1) = xsℓ + T0 f ( xsℓ , usℓ , ioℓ )dℓ (9)

where ℓ ∈ {0, 1, 2, 3} is the index for the switching vectors of the sequence. The instan-
taneous evolution of the state-vector prediction at the end of the sub-cycle corresponds
to its average trajectory when the seven-segment SS defined by (4) (see [24]) is applied to
the system:
3
dxs
xs [k + 1] = xs [k] + T0 ∑ d (10)
ℓ=0
dt t=ℓ ℓ

To simplify the analysis, every subinterval slope, mℓ = f ( xsℓ , usℓ , ioℓ ), is approxi-
mated using the values of the state and disturbance vector at the sampling instant, k, as
mℓ ≈ f ( xs [k], usℓ , io [k]). Therefore, the prediction of the average trajectory can be ex-
pressed as
3
x s [ k + 1] = A d x s [ k ] + E d i o [ k ] + B d ∑ usℓ dℓ (11)
ℓ=0
where Ad = I4 + T0 A, Ed = T0 E and Bd = T0 B. Because for any N-type seven-segment
SS, us0 = u− +
S , and us3 = uS , the duty cycles d0 and d3 can be combined as ds = d0 + d3 ,
which is the duty cycle for the small vectors of the sequence [24]. Then, the following linear
representation of the average trajectory can be stated as

xs [k + 1] = Ad xs [k ] + Ed io [k] + Bd Ud (12)

where the dwell-time vector, d, and switching matrix, U, are defined as

d2 ∈ D ≜ [0, 1]3
 
d = ds d1 (13a)
 
U = us u1 u2 (13b)

Even when the forward-Euler discretisation algorithm is widely used for the imple-
mentation of MPC algorithms, there are some issues which are produced when this method-
ology is applied to LC-filtered stand-alone loads. Some of these issues are as follows:
• For these sort of applications, usually two cascaded MPC algorithm are implemented [36]
to regulate the voltages and currents. An outer MPC regulates the voltages and an
inner MPC regulates the converter’s output currents; in this case, the standard forward-
Euler algorithm performs well. Nevertheless, when nested cascaded MPC loops are
implemented, two cost functions are required and a global optimum is not necessarily
reached. This is further discussed in [37].
• To obtain a global optimum, a single cost function is recommended, which has to
consider the tracking errors of the currents and load voltages. However, an LC-filtered
load is a plant which is not reachable in a single-step horizon, i.e., the output currents
Processes 2024, 12, 348 8 of 25

and load voltages cannot reach their reference values in one step because the B matrix
of (11) is not squared (see [28]). To solve this issue when the forward-Euler discretisa-
tion method is used, an MPC algorithm with a two-step horizon has been proposed
in [37]; nevertheless, this larger prediction horizon may produce a relatively large
computer burden, which can be justifiable for a large and costly modular multilevel
converter but is hardly convenient for a smaller stand-alone application.
• Moreover, one of the main disadvantages of forward-Euler-based MPC algorithms
for single-stage implementation (i.e., the application presented in this work) is the
unconstrained solution obtained from the cost solution of (30). The matrices Ad and
Bd obtained using the forward-Euler discretisation method (see (12)) are prone to
producing an unconstrained solution for Ud which is very weakly related to the load-
voltage tracking error. Therefore, when forward-Euler is applied to the system of
Figure 1b, poor performance or even a complete lack of control could be obtained
for the regulation of the load voltage. Conversely, when the improved-Euler method
is used to discretise (6a) and (6b), more exact matrices are obtained for Ad and Bd
(see (17)) and the unconstrained solution for Ud can be tuned (by adjusting the cost
weights) to be dependent on both the tracking error of the load voltage as well as on
the tracking error of the 3L-NPC converter output current.
Based on the comparison presented above, in this work the discretisation of the
continuous-time model is performed using the improved-Euler method [38]. This is further
discussed in the next section.

3.2.2. Improved-Euler-Based Discrete Time Model

The improved-Euler method is a second-order Runge–Kutta method to compute the
solutions of ordinary differential equations [38]. In this method, the weighted average
of the approximations to the derivative at intermediate points on the solution curve is
computed. Specifically, the improved-Euler method uses the extreme points of the solution
interval (i.e., kth and (k + 1)th points). Higher-order Runge–Kutta methods use more
intermediate points to increase the accuracy of the solution.
Once again, it is assumed that a 7S-SS is applied by the converter during the complete
switching cycle. Considering the improved-Euler method, the instantaneous evolution of
the state vector is given by the following equation:
" #
Ts
xs(ℓ+1) = xsℓ + f ( xsℓ , usℓ , ioℓ ) + f ( xsℓ [k + 1], usℓ [k + 1], ioℓ [k + 1]) dℓ (14)
2

The average slope is multiplied by Ts because it is the time length between predictions
in the interval [k, k + 1] and predictions in the interval [k + 1, k + 2]. To simplify (14), some
assumptions about the states and inputs used for computational purposes are required.
Firstly, the slope of the system at the kth time instant is computed with the values measured
at the time instant k (i.e., f ( xsℓ , usℓ , ioℓ ) ≈ f ( xs [k ], usℓ , io [k])). Secondly, the slope at the
(k + 1)th time is computed with the predicted state vector, xs [k + 1], using the forward-
Euler approximation defined by (12). The switching sequence applied is the same as that
of time instant k (i.e., f ( xsℓ [k + 1], usℓ [k + 1], ioℓ [k + 1]) ≈ f ( xs [k + 1], usℓ , io [k + 1])). The
disturbance vector is assumed to be constant during the switching cycle but different
between switching cycles (i.e., io [k] ̸= io [k + 1]). Considering these assumptions, the
state-vector trajectory is described by
" #
Ts
xs(ℓ+1) = xsℓ + f ( xs [k], usℓ , io [k ]) + f ( xs [k + 1], usℓ , io [k + 1]) dℓ (15)
2

The slopes mℓ [k ] = f ( xs [k], usℓ , io [k]) and mℓ [k + 1] = f ( xs [k + 1], usℓ , io [k + 1]) are
described by the following equations:
Processes 2024, 12, 348 9 of 25

mℓ [k] = Axs [k ] + Busℓ + Eio [k] (16a)

mℓ [k + 1] = Axs [k + 1] + Busℓ + Eio [k + 1] (16b)
Replacing xs [k + 1] in (16b), the expression for the slope mℓ [k + 1] is obtained as follows:
 
1 1 1
mℓ [k + 1] = A + Ts A2 xs [k] + Ts ABUd + Ts AEio [k ]
2 2 2 (17)
+ Busℓ + Eio [k + 1]

Then, the average trajectory of the state vector, using the improved-Euler method, is
computed as " #
3
Ts
x s [ k + 1] = x s [ k ] +
2 ∑ m ℓ [ k ] + m ℓ [ k + 1] d ℓ (18)
ℓ=0

Replacing (16a) and (17) into (18), and after some algebraic manipulations, the follow-
ing expression is obtained:
   
1 1
xs [k + 1] = I + Ts A + Ts2 A2 xs + I + Ts A Ts BUd
4 4
  (19)
1 1 1
+ I + Ts A Ts Eio [k ] + Ts Eio [k + 1]
2 2 2

Equation (19) is useful when an observer-predictor computes io [k + 1], and the dif-
ference between io [k ] and io [k + 1] is sufficiently large. However, if it is assumed that
io [k] ≈ io [k + 1] then the average prediction model is simplified to
   
1 1
xs [k + 1] = I + Ts A + Ts2 A2 xs + I + Ts A Ts BUd
4 4
  (20)
1
+ I + Ts A Ts Eio [k]
4

The discrete-time model in (20) can be

 written as the linear
 representation
 (12) with
Ad = I + Ts A + 14 Ts2 A2 , Bd = I + 14 Ts A Ts B, and Ed = I + 14 Ts A Ts E. This discrete-
time model will be used in this work.

4. OSS-MPC Formulation for Voltage and Current Control

The main objective of the controllers is to keep the voltage of the LC filter capacitors
as sinusoidal non-distorted waveforms. Meanwhile, the converter currents are controlled
as a secondary objective. In this regard, the reference voltage vector is

v∗o [k + 1] = V ∗ e jω [k+1]Ts (21)

where V ∗ is the magnitude of the reference voltage vector and ω is the fundamental
frequency of the output voltage (ω = 2π f 0 ).
The reference current is obtained as a function of the reference voltage. Replacing the
reference voltage vector into the dynamic equation of the output voltages yields [39]

dv∗o 1 ∗
= (i − i o ) (22)
dt Cf s

Solving the equation for i∗s , the converter reference current vector is obtained:

i∗s = ωC f Jv∗o + io (23)

Processes 2024, 12, 348 10 of 25

where the matrix J is defined as  

0 −1
J= (24)
1 0
It is desirable to constrain the reference current to a maximum value, Imax . When the
amplitude of the reference current is less than the specified limit, the reference current vector
is described by Equation (23). In the other case, the reference current vector is saturated
at Imax . Therefore, the constrained reference current is represented by the following piece-
wise function:
ωC f Jv∗o + io ∥i∗s ∥2 < Imax
(
∗
is = Imax ∗ (25)
i
∥i ∗ ∥ s
∥i∗s ∥2 ≥ Imax
s 2

Thus, the reference state vector is

i∗s
 
x∗s [k + 1] = (26)
v∗o

4.1. Cost Function

At the heart of the MPC strategy lies the cost function. In the cost function, the variables
related to the control objectives are weighted to choose the best possible action. In FCS-MPC
schemes, the cost function is most commonly designed to minimize the tracking error [5,16];
however, it has been shown that FCS-MPC strategies without penalization of the control
effort are equivalent to quantised deadbeat controllers [19]. Deadbeat controllers feature
fast dynamic response [28], but they have poor robustness against model mismatches,
parameter uncertainties, and noise on measured variables [40]. To alleviate the unwanted
effects of deadbeat controllers, the control effort is usually penalised in the cost function [28].
In the control proposed in this work, the OSS–MPC control has two objectives: minimise
the tracking error between the state vector and its reference and penalize the control effort.
Therefore, the following cost function is defined:

J (U j , d j ) = ∥ xs [k + 1] − x∗s [k + 1]∥2Q + λu ∥u[k ] − uss [k]∥22 (27)

The positive-definite matrix Q = diag(λi ,λi ,λv ,λv ) is used to trade-off the control
objectives of the state-vector tracking. Similarly, the weighting factor, λu , is used to penalize
the control effort. The optimisation variable of the problem is the average switching vector,
u(k ). The average switching vector is the product between the switching matrix and the
duty cycle vector, u(k) = Ud.
Firstly, the term of the cost function used to penalize the reference tracking error will
be reformulated as a function of the average switching vector, u(k). Replacing (12) in (27)
yields
∥Bd u − ( x∗s [k + 1] − Ad xs [k] − Ed io [k])∥2Q (28)
| {z }
: =κ [ k ]

where the value of κ can be obtained using (12). If x∗s [k + 1] = Ad xs [k ] + Ed io [k] + Bd Ud,
then the required Bd Ud to produce x∗s [k + 1] is equal to x∗s [k + 1] − Ad xs [k] − Ed io [k ]. This
is defined as κ in (28).
The second term of the cost function in Equation (27) has the vector uss . Vector uss is
the steady-state control action. The steady-state control action is the input vector needed
to drive the system towards the steady-state solution. The expression for this vector is
obtained by solving the circuit of Figure 3 for uss . The steady-state control input, uss , is
defined as
     
2  
uss = 1 − ω 2 L f C f I2 + ωR f C f J v∗o + R f I2 + ωL f J io (29)
Vdc
Processes 2024, 12, 348 11 of 25

Figure 3. Circuit diagram to obtain the steady–state control action.

Finally, the cost function for the optimisation problem can be written as

Jj (U j , d j ) = ∥Bd u[k] − κ∥2Q + λu ∥u[k ] − uss [k]∥22 (30)

4.2. Optimisation Problem

In OSS–MPC, the optimal switching sequence (OSS) is obtained by solving an optimi-
sation problem. The solution must comply with constraints such that the sum of leg duty
cycles is equal to one, and each duty cycle must be equal to or greater than zero. Therefore,
the optimisation problem to be solved is as follows:
n o
{U ⋆ , d⋆ } = arg min min Jj (U j , d j ) (31a)
Uj dj

s.t. 1⊺ d = 1 (31b)
dj ≥ 0 (31c)

The optimisation problem has the same form as the one solved in [26]. Therefore,
the same optimiser will be used. Thus, the usual strategy to solve MPC problems with
3L-NPC converters of evaluating each region, R j ∈ {R1 , . . . , R24 }, of the space of vectors
is avoided.

5. Optimal Solution
In this section, the optimisation problem presented in (31a), (31b) and (31c) will
be solved to obtain the optimal switching vector sequence and its corresponding duty
cycles to be applied during the next sampling instant. Two cases of the problem are
distinguished: first, the linear modulation stage where the duty cycles are positive, and
second, the overmodulation stage where the duty cycle of the small switching vectors
becomes negative.

5.1. Non-Negative Duty Cycles: The Linear Modulation Stage

To relax the optimisation problem, the inequality constraints are removed from the
problem formulation. Thus, the solution is assumed to be in the linear modulation stage,
where the duty cycles are always non-negative. The relaxed optimisation problem is then
stated as

min Jj (U j , d j ) (32a)
d
s. t. 1⊺ d j = 1 (32b)

Expanding the cost function (30) yields

Jj = (Bd u − κ)⊺ Q(Bd u − κ) + λu (u − uss )⊺ (u − uss ) (33)

The following expression is obtained:

Jj = u⊺ Q′ + λu I2 u − 2u⊺ B⊺d Qκ + λu uss + λu u⊺ss uss + κ⊺ Qκ

(34)
Processes 2024, 12, 348 12 of 25

where Q′ is the modified weight matrix, Q′ = B⊺d QBd . The elements of the switching
matrix, U j ∈ R2×3 , are the vectors of the switching sequence:
 
u u1α u2α
U j = sα (35)
usβ u1β u2β
Considering the equality constraint of the relaxed optimisation problem, the duty
cycles for the small switching vectors, as a function of the remaining duty cycles, can be
written as
dSj = 1 − d1j − d2j (36)
An auxiliary variable, dηj , is defined to eliminate the dependent variable dS from the
optimisation vector d j :  ⊺
dηj = d1j d2j (37)
The relationship between d j and dηj is as follows:
   
−1 −1 1
dj = 1 0 dηj + 0
  (38)
0 1 0
| {z } |{z}
M N

⊺
Then, u = Ud = U Mdηj + N = U Mdηj + U N and u⊺ = d⊺ U ⊺ = Mdηj + N U ⊺ =


 
d⊺ηj M ⊺ + N ⊺ U ⊺ . The cost function in terms of dηj is

J = d⊺ηj M ⊺ U ⊺ Q′ + λu I 2 U Mdηj

+ 2dηj M ⊺ U ⊺ Q′ + λu I 2 U N


(39)
− 2dηj M ⊺ U ⊺ B⊺d Qκ + λu uss + N ⊺ U ⊺ Q′ + λu I 2 U N

− 2N ⊺ U ⊺ B⊺d Qκ + λu uss + κ⊺ Qκ + λu u⊺ss uss

Computing the gradient of J with respect to dηj and making it equal to zero yields

∇ J dηj = 2M ⊺ U ⊺ Q′ + λu I 2 U Mdηj

+ 2M ⊺ U ⊺ Q′ + λu I 2 U N


(40)
− 2M ⊺ U ⊺ B⊺d Qκ + λu uss = 0

Reorganizing (40) to leave the terms related to the duty cycles on the left, (41) is obtained:

M ⊺ U ⊺ Q′ + λu I 2 U Mdηj =


(41)
M ⊺ U ⊺ B⊺d Qκ + λu uss − M ⊺ U ⊺ Q′ + λu I 2 U N

Solving the equation for dηj yields

dηj = [U M ]−1 uunc − [U M ]−1 U N (42)

Therefore, the unconstrained control action (uuc ) is defined as

−1  ⊺ 
uuc = Q′ + λu I 2 Bd Qκ + λu uss (43)

Now, it is necessary to map the solution back to its original variables. Replacing (42)
in (38) yields
h iu 
−1 −1 uc
drj = M (U M ) N − M (U M ) U N (44)
1
The optimal duty cycles for the linear modulation stage are computed using the
(3 × 3) matrix:
Processes 2024, 12, 348 13 of 25

u − u2β u2α − u1α u1 × u2 uuc,α

  
1 1β
drj =  u2β − usβ usα − u2α u2 × us uuc,β  (45)
∆
usβ − u1β u1α − usα u s × u1 1

where ∆ is the determinant of matrix product (U M )−1 :

∆ = u S × u1 + u2 × u S + u1 × u2 (46)

with u x × uy = u xα uyβ − u xβ uyα denoting the cross product.

5.2. Handling the Negative Duty Cycles: The Overmodulation Stage

In the previous section, the relaxed solution to the optimisation problem was calculated.
The relaxed duty cycles vector, drj , is the local solution for each region, R j ∈ R, of the
control hexagon, V. The relaxed solution computed with (32a) and (32b) fulfills the equality
constraint 1⊺ d = 1. Thus, all regions can be mapped onto uuc in the αβ-plane. However,
only one region fulfils the non-negativity constraint [24]. The non-negativity constraint
can then be considered in the solution with a simple methodology (as reported in [24,26]).
The methodology introduced therein also reduces the computational burden, avoiding the
search over all 24 regions of the control region V to only four. The methodology will be
explained in this section.
Firstly, considering the αβ-plane shown in Figure 4a with the space of vectors of the
3L-NPC converter is divided into 12 regions. The algorithm seeks the region where uuc is lo-
cated, and then the three sectors in that region are evaluated in the control algorithm. Given
that uuc is the desired solution of the optimisation problem, its angle is used to find the
optimal region in the plane. The optimal sector, S ⋆ , is obtained from the following equation:
( )
−1 uuc,β

⋆ 6
S = floor tan +1 (47)
π uuc,α

Figure 4. Control region of the 3L-NPC converter. (a) Hexagon divided into 12 sectors to reduce the
computational burden of the OSS–MPC algorithm, and (b) close-up look into sectors S1 –S2 .

When the optimal sector is calculated, the duty cycles of the switching sequences
contained in it are evaluated. The sector whose duty cycles complies with the non-negativity
constraint is the optimal sector, and thus the optimal switching sequence is found.
The conventional enumeration algorithm can be reduced to only three regions after
the sector has been identified. Each sector has three candidate switching sequences, but
only one of them fulfils the non-negativity constraint. Thus, the optimal pair {U ⋆ , d⋆ }
is found by evaluating the non-negativity condition over the duty cycles vector of each
(2)
candidate region. However, if uuc falls outside control region V (e.g., see uuc in Figure 4b)
then none of the candidate switching sequences fulfil the non-negativity constraint.
The aforementioned case occurs during a transient operation. The candidate switching
sequence is then reduced to one and is built by the medium and large switching vectors
belonging to the only outer region that intersects the optimal sector. The case is further
analyzed in the next subsection.
Processes 2024, 12, 348 14 of 25

5.2.1. Relaxed Optimisation Problem

The unconstrained average switching vector goes outside the hexagon, thus the duty
cycle for the small switching vector becomes negative. Defining dSj = 0, the optimisation
variable becomes  
0
d j = d1j 
 (48)
d2j
Consider the equality constraint

1⊺ 0
 
d1j d2j = 1 (49)

Notice that one of the two optimisation variables is dependent. Thus, if we set d2j to
be dependent of d1j , we can find an auxiliary vector to reduce the equality-constrained
optimisation problem into an unconstrained optimisation problem:
   
0 0
d j =  1  d1j + 0 (50)
−1 1
| {z } |{z}
M′ N′

⊺
Then, u = Ud = U M ′ d j + N ′ = (u1 − u2 )d1 + u2 and u⊺ = d⊺j U ⊺ = M ′ d j + N ′ U ⊺

(u1 − u2 )⊺ d1 + u⊺2 . The cost function is

J = (u1 − u2 )⊺ Q′ + λu I 2 (u1 − u2 )d21

+ 2( u1 − u2 )⊺ Q ′ + λ u I 2 u2 d1

− 2(u1 − u2 )⊺ B⊺d Qu′db + λu uss d1

(51)
⊺ ′

⊺ ⊺

+ u2 Q + λu I 2 u2 − 2u2 Bd Qκ + λu uss
+ κ⊺ Qκ + λu u⊺ss uss

5.2.2. Solution of the Relaxed Optimisation Problem

The unconstrained optimisation problem is solved by setting to zero the derivative of
the cost function with respect to the optimisation variable:

d
J = 2( u1 − u2 )⊺ Q ′ + λ u I 2 ( u1 − u2 ) d1


d(d1j )
(52)
+ 2( u1 − u2 )⊺ Q ′ + λ u I 2 u2

− 2(u1 − u2 )⊺ B⊺d Qκ + λu uss = 0

Solving this for d1 yields

(u1 − u2 )⊺ B⊺d Qκ + λu uss ( u1 − u2 )⊺ Q ′ + λ u I 2 u2



d1 = − (53)
( u1 − u2 )⊺ Q ′ + λ u I 2 ( u1 − u2 ) ( u1 − u2 )⊺ Q ′ + λ u I 2 ( u1 − u2 )

The matrix Q′ + λu I 2 corresponds to a scalar multiplied by the identity matrix.

−1 ⊺
Bearing on mind that uuc = Q′ + λu I 2 Bd Qκ + λu uss , the optimal duty cycle, d1⋆ , is

⋆ (u1 − u2 )⊺ (uuc − u2 )
d1j = (54)
( u1 − u2 )⊺ ( u1 − u2 )
Notice that the denominator of d1j ⋆ is the length between a large and the medium

vector in the hexagon frontier (see Figure 4b), thus,

4
∥∆u∥22 = (u1 − u2 )⊺ (u1 − u2 ) = (55)
9
Processes 2024, 12, 348 15 of 25

Then, the optimal solution for the overmodulation stage is:

( )
⋆ 9
d1j = mid 0, (u1 − u2 )⊺ (uunc − u2 ), 1 (56a)
4
⋆
d2j = 1 − d1j (56b)

6. NP-Voltage Control and PWM Modulator

The objective of the NP-voltage control loop is to compute an optimal common-mode
signal, u0⋆ , to balance the DC-link capacitors of the 3L-NPC converter.
The strategy assumes that a PWM stage is used to synthesize the solution obtained
from the outer optimisation loop. To this end, the OSS S⋆ is mapped into a three-phase
reference signal, D abc = [ Da Db Dc ]⊺ ∈ [−1, 1]3 , obtained as [26]

1  
D abc = d1⋆ u⋆abc,1 + d2⋆ u⋆abc,2 + d⋆S u⋆abc,0 + u⋆abc,3 (57)
2
−1 ⋆
in which u⋆abc,ℓ = Tαβ usℓ are the three-phase switching states that produce the OSS.
Finally, the three-phase reference signals sent to the PWM modulator are

D ⋆abc = D abc + u0⋆ (58)

where u0⋆ is the optimal common-mode signal to be injected to reduce the NP-voltage
tracking error. For further analysis and discussion of the methodology proposed to obtain
the common-mode signal, the reader is referred to [26].

7. Hardware-in-the-Loop (HIL) Results

In this section, hardware-in-the-loop (HIL) results are shown to validate the proposed
controller. The 3L-NPC converter, LC filter, and loads are emulated using PLECS-RT box 1
HIL platforms with a time-step of 5 µs. The control system is separately implemented using
a dSPACE MicroLabBox platform. This dSpace controller is equipped with a Freescale
QorIQ P5020 dual-core 2 GHz processor (DSpace Gmbh, Paderborn, Germany), for number
crunching, and a Kintex-7 XC7K325-T FPGA. The FPGA handles the AD conversion,
performs an in-phase disposition PWM strategy, and implements a dead time of 1 µs for
each switching device; the HIL system is shown in Figure 5a. The processor computes
the Clark transform of the measured three-phase variables, executes the optimisation
algorithm, and computes the appropriate three-phase reference signals for the modulator.
The loads considered for the study are a three-phase resistive load bank and a nonlinear load
implemented using a three-phase diode rectifier with a capacitor and resistor connected in
parallel at the DC side, as shown in Figure 5b. The parameters of the system are shown in
Table 1 and are similar to those used in a previous work (see [27]).
Table 1. System Parameters.

Parameter Value
Switching and sampling frequency f s = 20 kHz
DC-link voltage Vdc = 700 V
LC filter R f = 1 mΩ L f = 2.4 mH C f = 15 µF
Load resistance R L = 30 Ω
Nonlinear load Ln = 1.8 mH Cn = 2.2 mF Rn = 60 Ω
Filter current weight factor λi = 0.25
Load-voltage weight factor λv = 0.02
Processes 2024, 12, 348 16 of 25

Figure 5. (a) HIL platform used to perform the experiments, (b) topology of the nonlinear load.

For the HIL results discussed in this section, the current of the nonlinear load used
in some tests, corresponds to that shown in Figure 6; notice that the non-linear current
is estimated in the processor using the auto-regressive model provided by the Lagrange
polynomial shown in Equation (61). For the results shown in Figures 7–10, the weight
related to the control effort is set to λu = 0. The effects of using different values of λu in the
performance of the proposed control system are discussed using Figures 11 and 12.

Figure 6. Estimated and measured current when a nonlinear load is connected: (a) α−component of
the load current, (b) β−component of the load current.
Processes 2024, 12, 348 17 of 25

Figure 7. Steady–state results for different load conditions: (a,d,g) load output voltage without load,
with resistive load and with nonlinear load, (b,e,h) load output current without load, with resistive
load and with nonlinear load, (c,f,i) DC–link capacitor voltages without load, with a resistive linear
load and nonlinear load.

10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency

Figure 8. Harmonic spectrum of (a) load output voltage and (b) load output current when a nonlinear
load is connected.

Figure 9. Transient operation of the system for reference voltage step: (a) voltage step from 300 (V) to
100 (V), (b) voltage step from 100 (V) to 300 (V).
Processes 2024, 12, 348 18 of 25

Figure 10. Transient operation of the system for a load step: (a) load output voltage, (b) filter inductor
current.

Figure 11. System performance over variation of λu : (a) Percentage of the effective (RMS) load
voltage tracking error respect to the λu variation, (b) Total harmonic distortion of the load voltage,
considering a wide λu variation.

Figure 12. Transient operation of the system for different values of λu .

The performance of the controllers is evaluated using the following goodness factors:
RMS error (RMSE), percentage of voltage error (Ev ), and total harmonic distortion (THD).
The percentage of error is defined as follows:
s
100 1
∥v∗ ∥ Np k∑
Ev [%] = ∥v(k) − v∗ (k)∥22 (59)
∈P

where P = {1, 2, . . . , Np } is the set of indices of the measurements vector and Np = T1 /Ts
is the total number of elements in the vector. T1 is the period of the fundamental frequency
and Ts is the period of the sampling frequency. Whenever the desired reference amplitude
is unknown, the root-mean-square error (RMSE) will be used. The RMS error is defined
as follows:
s
1
Np k∑
∗
RMSE( x − x ) = ∥ x(k) − x∗ (k)∥22 (60)
∈P

A one-step delay compensation is carried out to compensate for the computational

delay introduced by the digital platform. The state vector, xs [k + 1], is computed using (20)
with the values measured at the kth instant and the switching sequence applied during the
Processes 2024, 12, 348 19 of 25

previous switching interval. The voltage reference, vo [k + 1], is computed by shifting the
phase of the reference signal one step ahead. The load output current, io [k + 1], is estimated
using the Lagrange extrapolation technique. The Lagrange extrapolation technique uses
the actual and past measurements of the signal to estimate its future value. The load output
current, io [k + 1], is computed as follows [41]:

io [k + 1] = 4io [k] − 6io [k − 1] + 4io [k − 2] − io [k − 3] (61)

The estimated load output current has an RMS error of 0.0603 (A) in the α-component,
and 0.0640 (A) in the β-component for the worst-case scenario (nonlinear load). The
estimated and measured load output current are shown in Figure 6. As shown in this figure,
the estimated current tracks the measured current relatively well.
In Figure 7a, the output voltages when the system operates without load are shown.
The reference voltage has an amplitude of 300 V with a frequency of 50 Hz. For this
condition, the load output voltages have a voltage error of 2.04% and a THD of 1.74%. Then,
a three-phase resistive load is connected as in Figure 7d. In this condition, the voltage error
is 2.05% and the THD is 1.03%. When a nonlinear load is connected, as in Figure 7g, the
voltage error is 2.83%. The harmonic spectrum for the load output voltage and load output
current are shown in Figure 8a,b. The voltage THD in this case is 2.73% with the presence
of 5th and 7th harmonics, which are produced by the bridge rectifier. In Figure 7b–h, the
load output current is shown for the three aforementioned cases. Finally, in Figure 7c–i
the DC-link capacitor voltages are shown. The control strategy is capable of keeping the
DC-link voltages balanced and well regulated for all operating conditions, with very small
oscillations.
The transient operation of the controlled system is studied in Figure 9, considering
changes in the reference voltage amplitude with λu = 0. The variables are presented in the
synchronous reference frame to verify the settling time of the load output voltage.
The settling time is computed as the time required by the output voltage to reach
and stay within 5% of the desired voltage. In Figure 9a, the reference voltage receives a
step variation from 300 V to 100 V at t = 0.2 s. The voltage error amounts to 5.98% under
steady-state conditions. The rise in voltage error results from the reduction in the amplitude
of the reference voltage. In Figure 9b, the reference voltage varies from 100 V to 300 V
at t = 0.2 s. In this case, the load output voltage manages to stay within the band of 5%
around the desired voltage. Thus, the settling time is approximately 1.03 ms .
Notice that a relatively low steady-state error is presented in the HIL results shown in
Figure 9a,b. This small steady-state error is produced because there is not an integrator in
the MPC algorithm [42,43]. If the steady-state error is a must, then the state-space matrix, A
(see (7)), must be augmented with additional states to represent the integrator [42]; however,
this topic is considered to be outside the scope of this work.
Figure 10 shows the operation of the system for a load step. A dip occurs in the load
output voltage, as shown in Figure 10a, and takes approximately 1 ms to recover. Notice
that there is a sudden increase in the inductor reference current to approximately 10 A, and
the current features a fast dynamic response to the step change.
The cost function of (30) has two terms: the first term penalizes the deviation of the
system states from a reference vector and the second term penalizes the control effort of
the converter. The control effort is penalized in the cost function by the deviation between
the optimisation variable, u(k ), and the steady-state control effort, uss . The weight of this
deviation on the optimisation problem is set by the parameter λu . Increasing λu will lead
the converter’s response to move closer to open-loop operation since us s depends only
on the load reference voltage and load output current. The system’s performance with
a logarithmic variation of parameter λu is shown in Figure 11. The results are obtained
considering a three-phase resistive load at the LC filter terminals. The best trade-off in
terms of voltage error between open-loop and closed-loop operation of the converter is
achieved when λu = 10, as shown in Figure 11a. When λu is increased, the response of the
Processes 2024, 12, 348 20 of 25

system tends toward uss , which does not penalize the voltage error. Thus, the voltage error
increases.
As shown in Figure 11b, the voltage THD presents slight variations around 1%, as
shown in Figure 11b. The system’s transient response is also dependent on the value of λu .
A trade-off between settling time and overshoot must be reached, as shown in Figure 12.
Increasing λu up to 100 will reduce the settling time of the system but increase the voltage
overshoot. However, for λu >> 100, the system response will present a damped sinusoidal
oscillation which increases the settling time.

8. Comparison with a Previously Reported OSS-MPC Algorithm

In this section, the proposed scheme is compared with the prior OSS–MPC method
discussed in [27]. In that publication, it is proposed to regulate the voltage in the LC-filtered
load without considering a term weighting the control effort. This is similar to using λu = 0
in (30). In addition to ignoring the control effort, regulation of the converter’s output
current is not considered in [27]. For the comparison, simulation work using PLECS 4.7
software has been performed.
Figure 13 shows simulation results considering a step change from 0 to 300 V in the
load voltage for both control strategies, i.e., the one published in [27] and that proposed
in this work. In this case, the value λu in (30) has been set to 0. As shown in Figure 13a,
the proposed method presents neither overshoot nor noticeable oscillation in the load
voltages, as opposed to the results obtained with the OSS–MPC of [27] (see Figure 13a,c).
The smooth transition in the load voltage is obtained by the utilisation of the cost function
of (30), which considers the inductor current and output voltage tracking errors. Moreover,
the utilisation of a term in the cost function weighting the output-current tracking error
produces a considerably smaller current peak (16.35 A, see Figure 13b) when compared to
the 32.1 A obtained for the method of [27] (see Figure 13d). The proposed method also has
a slightly faster response, taking 0.81 ms to reach steady-state in Figure 13. Meanwhile, the
prior OSS–MPC method takes 0.83 ms to reach steady-state.

Figure 13. Simulation of the system performance when the reference voltage is changed from 0 V
to 300 V: (a) output capacitor voltages with the proposed method, (b) inductor currents with the
proposed method, (c) output capacitor voltages with prior OSS–MPC [27], (d) inductor currents with
prior OSS–MPC [27].

An amplified view of Figure 13 is shown in Figure 14. The effects produced by

neglecting an output current-related term, in the cost function of [27], are clearly shown in
Figure 14c,d. A large peak current, as well as relatively large undamped current oscillations,
are produced for ≈1.2 ms after the step change. These large current oscillations affect the
quality of the load-output voltage. Notice the smooth variation in the output voltages
produced when the control method proposed in this work is applied. This is shown in
Figure 14a,b.
Processes 2024, 12, 348 21 of 25

Figure 14. Amplification of Figure 13: (a) output capacitor voltages with the proposed method,
(b) inductor currents with the proposed method, (c) output capacitor voltages with prior OSS–
MPC [27], (d) inductor currents with prior OSS–MPC [27].

The performance of the control systems has also been tested considering a balanced
load step of 30 Ω in t = 0.1 s. Before the step, the system is operating without a load parallel
connected with the capacitor of the LC-filter. Figure 15a,b shows the performance obtained
with the OSS–MPC strategy proposed in this work; meanwhile, Figure 15c,d shows the
results obtained with the work reported in [27]. Again, the peak current overshot shown
in Figure 15b is smaller than that of Figure 15d, with peak values of approximately 14.5 A
and 21.5 A, respectively. The control strategy of [27] has a smaller dip in the load voltage
for the step in t = 0.1 s; however, this better performance is obtained because neither the
control effort nor the peak currents are considered in the cost function reported in that
work. Moreover, as discussed previously for the results presented in Figure 14d, lightly
damped current oscillations are produced after the load step, as depicted in Figure 15d.
These current oscillations also affect the load voltage, as shown in Figure 15c, for the time
immediately after t = 0.1 s. It is concluded that, for the load step change, the performance
of the proposed control system is better than that of [27], which is shown in Figure 15c,d.
The peak current is lower and the lightly damped oscillations in the currents and voltages
are completely avoided, as depicted in Figure 15a,b.

Figure 15. Simulation of the system performance when a linear load is connected: (a) output capacitor
voltages with the proposed method, (b) inductor currents with the proposed method, (c) output
capacitor voltages with prior OSS–MPC [27], (d) inductor currents with prior OSS–MPC [27].

The performance of the proposed control system is also clearly superior to that re-
ported in [27], when the nonlinear load of Figure 5b is connected at the output of the
Processes 2024, 12, 348 22 of 25

LC-filter. The simulation results are shown in Figure 16a,b; before t ≈ 0.05, the capaci-
tor at the nonlinear load is completely discharged and it is equivalent to a short circuit
immediately after the nonlinear load is connected at t ≈ 0.05 s. Therefore, the control
system reported in [27] has a bad performance because neither current control nor current
limitation is considered in the cost function reported in that paper. Hence, the current
shown in Figure 16b reaches a peak value of 297.2 A; meanwhile, the peak current achieved
by the OSS–MPC algorithm reported in this work is 33 A. Of course, with this large current
the control strategy of [27] manages to regulate the load voltage in approximately 20 ms
vs. 80 ms for the proposal, but it is unlikely that the power converter and LC filter could
withstand this large output current surge. Therefore, the lack of current regulation is
certainly a very strong drawback of the control strategy being compared with the MPC
scheme reported in this work.

Figure 16. Simulation of the system performance when a nonlinear load is connected at the output
of the LC filter: (a) inductor currents with the proposed method, (b) inductor currents with prior
OSS–MPC [27].

9. Conclusions
In this paper, an optimal switching sequence MPC algorithm was proposed for a three-
level neutral-point-clamped inverter with an output LC filter. The strategy is an extension
of the cascaded optimal switching sequence MPC proposed in the literature for current
and direct power control of active front-end 3L-NPC inverters. The control objectives
of the algorithm were twofold: (1) achieve good tracking performance for the LC filter
variables (current and voltages) and (2) maintain a balanced neutral-point voltage between
the DC-link capacitors of the converter using the algorithm already reported in [26]. To
achieve the objectives, the strategy solves two cascaded optimisation problems. The first
optimisation problem—called the outer optimisation loop—computes the optimal sequence
of switching vectors and their corresponding duty cycles to achieve the objectives related
to tracking the AC side variables. Then, the optimal solution of the outer optimisation loop
reported previously in [26] is used to compute an optimal common-mode signal designed
to balance the neutral-point voltage between the DC-link capacitors.
As discussed in the final paragraphs of Section 3.2.1 of this work, the standard forward-
Euler implementation typically used for predictive control has some problems implement-
ing a single-stage OSS–MPC algorithm regulating the current and voltage of a load con-
nected to an LC-filtered 3L-NPC converter, because the unconstrained solution is weakly
dependant on the load-voltage tracking error. Therefore, a two-step horizon has to be
considered, or another discretisation methodology, as the improved forward-Euler has to
be selected. Therefore, a discrete-time model based on the improved-Euler discretisation
method was used to predict the future values of the state-vector trajectory. Notice that this
methodology allows the implementation of a single-stage MPC algorithm to regulate the
load voltage and the converter output current.
Experimental results are provided to validate the performance of the proposed strategy
using the PLEXIM hardware-in-the-loop (HIL) platform RT Box 1 to emulate the power
electronics stage, and the control algorithm was executed by the dSPACE MicroLabBox
control platform. Three cases were considered in steady-state operation: (1) system perfor-
mance without load, (2) system performance with linear load, and (3) system performance
Processes 2024, 12, 348 23 of 25

with nonlinear load. In all cases, the MPC algorithm is capable of achieving good tracking
of the load-voltage reference with a small error and low THD. In addition, the strategy is
capable of maintaining well-balanced voltages at the DC-link capacitors. Moreover, the
performance of the proposed control system has been compared with that obtained from
the work reported in [27] using simulations. For all the tests performed, i.e., step changes
in the output voltage, step changes in the load voltage, and operation with a nonlinear
load at the output, the proposed control system has consistently outperformed the results
obtained with the control strategy of [27].

Author Contributions: Conceptualization, F.H., A.M., R.C. and J.R.; formal analysis, F.H., A.M.,
R.C., M.D. and M.R.; funding acquisition, R.C., M.D. and J.R.; investigation, F.H., J.R. and M.R.;
methodology, A.M. and R.C.; project administration, R.C.; resources, M.D.; software, F.H., M.D. and
M.R.; supervision, A.M. and R.C.; validation, F.H., A.M. and R.C.; writing—original draft, F.H. and
A.M.; writing—review and editing, A.M., R.C., M.D., J.R. and M.R. All authors have read and agreed
to the published version of the manuscript.
Funding: This research was funded by ANID Fondecyt grants, numbers 1221392, 1231030 and
1220556. The support of Fondequip EQM210117 and Basal grant FB0008 is kindly acknowledged.
The financial support of the Junta de Andalucía (CTEICU, SGU) project ProyExcel-00381 was also
important for the successful completion of this research work. Finally, the work of F. Herrera was
supported by anid grant ANID-PCHA/Doctorado Nacional/2022-21220759.
Data Availability Statement: The original contributions presented in the study are included in the
article, further inquiries can be directed to the corresponding author.
Conflicts of Interest: The authors declare no conflicts of interest. The funders had no role in the design
of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or
in the decision to publish the results.

Abbreviations
The following abbreviations are used in this manuscript:

7S-SS Seven Segments Switching Sequence

DC Direct Current
AC Alternate Current
FPGA Field Programmable Gate Array
FCS-MPC Finite Control Set Model Predictive Control
M2 PC Modulated Model Predictive Control
HIL Hardware-in-the-Loop
LC-filter Inductance Capacitor Filter
MIMO Multiple-Input–Multiple-Output
MPC Model Predictive Control
NPC Neutral Point Clamped
OSS Optimal Switching Sequence
OSV Optimal Switching Vector
PWM Pulse Width Modulation
RT Real Time
SISO Single-Input–Single-Output
THD Total Harmonic Distortion
UPS Uninterruptible Power Supply
VFD Variable Frequency Drives

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