A 71.

5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip

Bit-Weight Calibration
Chao Chen, Zhu Yuan, Peng Cao, Jiawei Xu, Zhiliang Hong
State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China

Abstract loop path thus enhancing CM stability. The local CMFB loop,
This paper presents a 13-bit 475-MS/s single-channel consisting of an inverter-based amplifier and CS1, sets the 1st
pipelined SAR ADC, which utilizes a ring amplifier (ringamp) stage CM output close to VCM for optimal headroom. Fig. 2(c)
for residue amplification through an improved bias scheme and shows the measured SNDR and THD versus input CM
common-mode feedback (CMFB). Moreover, the ADC variation, demonstrating the effectiveness of CMFB loops.
exploits an on-chip bit-weight calibration with signal- The bit weights of the 1st-stage SAR can be calibrated using
dependent pseudo-random noise (PN) injection and a window signal-dependent PN injection [7]. However, the time-domain
detector to correct the interstage gain error and DAC mismatch, detector [7] requires each SAR comparison to wait until the
requiring only 4096 PN-injected samples to calibrate the gain detection is complete, limiting the speed of the asynchronous
error in the background. As a result, this work achieves a peak SAR, while using extra comparators [8] consumes extra power
SNDR of 71.5dB and consumes 9.93mW from a 1V supply. and gives rise to significant parasitic capacitance. To mitigate
This corresponds to a state-of-the-art FoMS of 175.3dB and these challenges, as shown in Fig. 3(a), we propose a
FoMW of 6.8fJ/conv-step. comparator with an auxiliary latch that performs quantization
Introduction as well as PN-injection window detection. The PN injection is
Pipelined ADCs with 1-to-500Msps sample rate and 8-to- enabled when the output results of the two latches are different,
16bit resolution have been widely used for ultrasonic medical and the residue transfer curve is shown in Fig. 3(b). This
imaging, base stations, and fast Ethernet. By employing SAR approach has minimal impact on conversion speed as the
ADCs as sub-ADCs within the pipeline, an outstanding trade- resolving times of both latches are similar. Moreover, reusing
off between speed and power dissipation can be achieved [1- the pre-amplifier saves power and avoids adding input parasitic
3]. However, the residue amplifier (RA) in a pipelined SAR compared to using an additional comparator.
ADC has limitations in terms of speed and accuracy. Ringamp The on-chip calibration algorithm is an improved version of
is capable of achieving both high bandwidth and linearity with [7] and achieves faster convergence. As depicted in Fig. 3(b),
great energy efficiency, but its stability and appropriate biasing DBE0 represents the middle code of the 2nd SAR outputs and
remain a key challenge [1-6]. Additionally, mismatch of the 1st appears as a large offset within the injected outputs. Since the
DAC and gain error of the RA also deteriorate the achievable large DBE0 is also involved in the correlation with the PN signal,
accuracy, necessitating complicated calibration [1]. To address the convergence speed of the conventional algorithm is slow.
these issues, this paper proposes a ringamp-based pipelined The proposed calibration functional diagram, illustrated in Fig.
SAR ADC with on-chip digital calibration, achieving 71.5dB 3(c), separates the injected back-end outputs and averages
SNDR at 475MS/s. them based on the corresponding PN value. The two averaged
Architecture and Circuits Implementation results, both including DBE0, are then subtracted to obtain the
The architecture and timing of the proposed ADC are shown desired weight information. Therefore, DBE0 is intrinsically
in Fig. 1. The ADC consists of a 1st-stage 5-bit SAR ADC, a eliminated, and this enables a fast convergence with only 4096
ringamp for interstage residue amplification of 16×, a 2nd-stage PN-injected samples for background gain error calibration. By
9-bit SAR ADC, and a bit-weight calibration block to correct reusing this background calibration circuit through a
the 1st DAC mismatch and interstage gain error. There is a 1b multiplexer, on-chip foreground calibration is implemented to
redundancy between two stages and the overall resolution is 13 obtain the 1st DAC mismatch factors.
bits. To limit kT/C noise, a differential capacitor DAC of 4pF Measurement Results
is employed in the 1st-stage SAR. The pipelined SAR ADC was fabricated in a 22nm CMOS
Fig. 2 illustrates the circuits and timing of the ringamp. The process (Fig.4). The ADC core consumes 9.93mW from a 1V
1st stage is fully differential, and the 2nd and 3rd stages are AC- supply at 475MS/s, while the ring amplifier and digital
coupled to realize optimal bias. However, directly biasing the calibration consume 4.14mW and 3.64mW, respectively (Fig.
AC-coupled capacitors in the sampling phase [2] requires 4). In Fig. 5, the ADC achieves 71.5dB SNDR and 84.0dB
complicated clock generation to prevent saturation in the 1st SFDR with a 10.7MHz input, and 65.9dB SNDR and 73.0dB
stage of ringamp and significant sampling jitter. To address this SFDR with a 234.9MHz input. Fig.6 (top) shows that the
issue, a switched-capacitor bias scheme based on charge calibration improves SNDR and SFDR by more than 15dB.
transfer is proposed. The bias voltage is sampled on the Fig.6 (bottom) shows the DR, and the INL and DNL after
switched-capacitor CS2 (Fig.2) and subsequently transferred to calibration are 1.22LSB and 0.51LSB, respectively. Table I
the AC-coupled capacitors CB2, avoiding the signal-dependent compares this work with state-of-the-art pipelined ADCs of
component on CB2 and eliminating the requirement for the similar speed. Even when including on-chip calibration power
dedicated clock phase. Besides, the rapid start-up scheme [3] consumption, the proposed ADC achieves the best-in-class
can power on and off the 2nd stage of ringamp, while this design SNDR and highly competitive FoMW and FoMS for both low
features an additional non-overlapped control to minimize frequency (LF) and Nyquist inputs.
interference on the bias. In this work, inverter-based amplifiers References
are utilized for discrete-time common-mode (CM) error [1] J. Lagos, VLSI, 2021. [2] M. Zhan, ISSCC, 2022.
[3] T.-C. Hung, ISSCC, 2020. [4] B. Hershberg, ISSCC, 2019.
amplification in the CMFB loops. Unlike [4], the global CM [5] B. Hershberg, ISSCC, 2019. [6] J. Lagos, VLSI, 2017.
error is fed back to the 2nd stage of ringamp, which can combine [7] Y. Zhou, JSSC, 2015. [8] Y.-S. Shu, JSSC, 2008.
with the switched-capacitor bias. This also reduces the CMFB [9] K.-J. Moon, VLSI, 2017.
 φS C1=2pF φA Clk phase gen.,
C2=430fF
0.237mW
VCM 186μm
145μm 1st SAR,
••• •••
VCM Clk Phase 1.07mW

φS
Gen. 2nd SAR,
0.847mW

145μm
CRA=125fF φA
2nd

91μm
VIP Digital Cal.
VREF st Digital Cal.,
VCM 1 SAR RA 3.64mW
VREF SAR & SPI
Ring Amp.,
4.135mW
Clk1 Clk2
Dm RA Bias
PN 1st SAR Logic φrst2
Gen. & PN Injection
Ringamp 2nd SAR Logic
Da Total 9.93mW
Fig. 4. Chip photograph (left) and power consumption (right).
( The other side) w/o Cal. w/ Cal.
Fs=475MHz
SNR 55.4 dB 72.1 dB
DFE[4:0] Flaginject [4:0] DBE[8:0] Fin=10.7MHz
SNDR 50.3 dB 71.5 dB
Points=16384
SFDR 53.4 dB 84.0 dB
On-Chip Bit-Weight Digital Calibration DOUT
2 3
φS Samp. Samp. Samp.

Clk1

φA Amp. Amp.

Clk2
w/o Cal. w/ Cal.
φrst2 Fs=475MHz
SNR 50.5 dB 67.1 dB
Fin=234.86MHz
SNDR 47.5 dB 65.9 dB
Fig. 1. Block and timing diagrams of the proposed ADC. Points=16384
SFDR 54.6 dB 73.0 dB

1st Stage 2 3
VBP2 2nd & 3rd 5
VIP VIM φA φA
Stage Current Bias Rapid Start-up
VBP1
VBP3
φS CS2 φS EN
CR1 CR2
CB2 M1p VCM
VOM VCM
VBP3 VBN3 VOP VBP1 VBP2
R1 R2 φA
EN

CFBp
Fig. 5. Measured output spectrums for LF/Nyquist inputs.
CB2 φ EN
VOP φS φS S

VOM φS CB1 φS φA CS2 φA

CFBm
φA CS1 φA VBN2 Sampling Frequency Sweep (Fin=10.7MHz) Input Frequency Sweep (Fs=475MHz)
VBN1 90 90
CF
VBN1 VBN2 φA
EN 80 80
φA
φA φS φS φS VOP VCM
VCM M1n
VCM 70 70
VOM CR1 CR2

(a) CM error Amp. VBN3 60 60

φS 50 50

40 SNDR w/ Cal. SNDR w/o Cal. 40 SNDR w/ Cal. SNDR w/o Cal.
φA SFDR w/ Cal. SFDR w/o Cal. SFDR w/ Cal. SFDR w/o Cal.
30 30
φA 100 150 200 250 300 350 400 450475 0 50 100 150 200 235
Sampling Frequency [MHz] Input Frequency [MHz]
EN
Input Amplitude Sweep (Fs=475MHz, Fin=10.7MHz) DNL/INL (13b) @Calibration ON
0.6
EN 70 72 DNL=-0.51/+0.22LSB
(b) (c)
60 0
Fig. 2. (a) Implementation and (b) timing diagram of the ringamp; (c) 50
70

Measured SNDR/THD versus input CM voltage variation. 40 68 SNR

-0.6
0 2000 4000 6000 8000
-3 -2 -1 0
Vres ΔV Vres 30 SNDR Output code
os
Clk1 ENinject
Clk1 Clk1
PN=0 20 1 INL=-1.22/+1.17LSB
Dmn Dmp Dap Dan
VIP VIM Middle code of 10 0
Back-end DR=72.1dB
••• ••• 0
Vin
output -1
Clk1
PN=1 -80 -70 -60 -50 -40 -30 -20 -10 0 0 2000 4000 6000 8000
Input Amplitude [dBFS] Output code
Pre-amplifier Main latch Aux. latch

(a) (b)
DBE0 DBE Fig. 6. Measured performance
DBE[8:0]
TABLE I PERFORMANCE SUMMARY AND COMPARISON
J. Lagos B. Hershberg J. Lagos K. -J. Moon
(MSB) DFE[4] This work
PNcode=1 DFE[3]
W4
VLSI'21 [1] ISSCC'19 [5] VLSI'17 [6] VLSI'17 [9]
Datain
Average
Resultout
IN
D OUT
Q DFE[2]
W3
Process [nm] 22 16 16 28 28
PNcode EN W2
Flaginj[0:4] Update
DFFs DFE[1] Ringamp Ringamp Ringamp Ringamp Gm-cell
W1 Architecture
IN Counting Done
CLK DFE[0] DOUT Pipelined SAR Pipelined SAR Pipelined Pipelined Pipelined SAR
EN W0
0 to 2^M
1
Supply [V] 1 0.9 0.85 0.9 1
Reset
2 Fs [MS/s]
×2 475 500 600 600 500
3
PNcode=0
4 Datain ×2 Resolution [bits] 13 11.5 11 12 10
Resultout
k Average IN OUT
EN 71.5
Update SNDR LF input - 60.4 58.1 56.7
×2
[dB] Nyquist 65.9 62.3 60.2 56.3 56.6
Select which IN Counting Done EN
to 2^M
mismatch factor
SFDR LF input 84.0 - 83.1 67.5 73.1
to be calibrated Reset Normalized 1st DAC
foreground. f1 f2 f3 f4 mismatch factors [dB] Nyquist 73.0 75.5 78.3 69.2 69.2
th
(Flaginj[k]=1 when PN injection occurs in the k bit) y x 2
(k=0 in background mode, M=11 in this work.) y=1/x 0
Core area [mm ] 0.038 0.0084 0.037 0.62 0.015
Foreground control 1
W0=W0 2 Gain Calibration On-chip Off-chip Off-chip Off-chip On-chip
3
Bit-Weight Cal. W1=W0(1+f1) Include Cal. Power? Yes No No No No Yes
4
W0: Background W2=W0(2+f1+f2)
f1-f4: Foreground W3=W0(4+2f1+f2+f3)
k Power [mW] 9.93 6.29 3.3 6.0* 14.2 6.0*
W4=W0(8+4f1+2f2+f3+f4) FoMS LF input 175.3 177.3 - 167.4 161.3 162.9
[dB] Nyquist 169.7 171.7 171.1 167.2 159.5 162.8
(c)
FoMW LF input 6.8 4.3 - 11.7 36.0 21.5
Fig. 3. (a) Comparator of 1st SAR with PN-injection window detection; [fJ/c.s.] Nyquist 13.0 8.2 6.2 12.0 44.3 21.7
(b) Residue transfer curve; (c) Digital calibration functional diagram. -Not reported; *Including a clock buffer.