Digital Design and Computer Organization (BCS302)

Module-5 Basic Processing Unit

Fundamental Concepts


 Processor fetches one instruction at a time, and performs the operation specified.
 Instructions are fetched from successive memory locations until a branch or a jump instruction is
encountered.
 Processor keeps track of the address of the memory location containing the next instruction to be fetched
using Program Counter (PC).
 Instruction Register (IR): When an instruction is fetched, it is placed in the instruction register
 The sequence of operations involved in processing an instruction constitutes an instruction cycle, which
can be subdivided into 3 major phases:
o Fetch cycle
o Decode cycle
o Execute cycle
Executing an Instruction
Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded
into the IR (fetch phase).
IR← [[PC]]
Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase).
PC← [PC] + 4
Carry out the actions specified by the instruction in the IR (execution phase).

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

 The registers Y, Z and Temp are used only by the processor unit for temporary storage during the
execution of some instructions.
 These registers are never used for storing data generated by one instruction for later use by another
instruction.
 The programmer cannot access these registers.
 The IR and the instruction decoder are integral parts of the control circuitry in the processing unit.
 All other registers and the ALU are used for storing and manipulating data.
 The data registers, ALU and the interconnecting bus is referred to as data path.
 Register R0 through R(n-1) are the processor registers.
 The number and use of these register vary considerably from processor to processor.
 These registers include general purpose registers and special purpose registers such as stack pointer,
index registers and pointers.
 These are 2 options provided for A input of the ALU.
 The multiplexer (MUX) is used to select one of the two inputs.
 It selects either output of Y register or a constant number as an A input for the ALU according to the
status of the select input.
 It selects output of Y when select input is 1 (select Y) and it selects a constant number when select input
is 0(select C) as an input A for the multiplier.
 The constant number is used to increment the contents of program counter.
 For the execution of various instructions processor has to perform one or more of the following basic
operations:

o Transfer a word of data from one processor register to another or to the ALU.
o Perform the arithmetic or logic operations on the data from the processor registers and store the
result in a processor register.
o Fetch a word of data from specified memory location and load them into a processor register.
o Store a word of data from a processor register into a specified memory location.

REGISTER TRANSFERS
Each register has input and output gating and these gates are controlled by corresponding control signals.
The input and output gates are nothing but the electronic switches which can be controlled by the control signals
. When signal is 1, the switch is ON and when the signal is 0, the switch is OFF.

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

Example
Suppose we wish to transfer the contents of register R1 to register R4. This can be accomplished as follows

 Enable the output of registers R1 by setting R1out to 1. This places the contents of R1 on the processor
bus.
 Enable the input of register R4 by setting R4out to 1. This loads data from the processor bus into register
R4.

All operations and data transfers within the processor take place within time periods defined by the processor
clock.
The control signals that govern a particular transfer are asserted at the start of the clock cycle.

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

Performing an Arithmetic or Logic Operation
 The ALU is a combinational circuit that has no internal storage.
 ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.
 What is the sequence of operations to add the contents of register R1 to those of R2 and store the result
in R3?
 R1out, Yin
 R2out, SelectY, Add, Zin
 Zout, R3in

All other signals are inactive.

 In step 1, the output of register R1 and the input of register Y are enabled, causing the contents of R1 to
be transferred over the bus to Y.
 Step 2, the multiplexer’s select signal is set to Select Y, causing the multiplexer to gate the contents of
register Y to input A of the ALU.
 At the same time, the contents of register R2 are gated onto the bus and, hence, to input B.
 The function performed by the ALU depends on the signals applied to its control lines.
 In this case, the ADD line is set to 1, causing the output of the ALU to be the sum of the two numbers at
inputs A and B.
 This sum is loaded into register Z because its input control signal is activated.
 In step 3, the contents of register Z are transferred to the destination register R3. This last transfer cannot
be carried out during step 2, because only one register output can be connected to the bus during any
clock cycle.

FETCHING A WORD FROM MEMORY

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

The processor has to specify the address of the memory location where this information is stored and request a
Read operation.
This applies whether the information to be fetched represents an instruction in a program or an operand
specified by an instruction.
The processor transfers the required address to the MAR, whose output is connected to the address lines of the
memory bus. At the same time, the processor uses the control lines of the memory bus to indicate that a Read
operation is needed.
When the requested data are received from the memory they are stored in register
MDR, from where they can be transferred to other registers in the processor.
The response time of each memory access varies (cache miss, memory-mapped I/O…).
To accommodate this, the processor waits until it receives an indication that the requested operation has been
completed (Memory-Function-Completed, (MFC))

Move (R1), R2
 MAR← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2← [MDR]
 The output of MAR is enabled all the time.
 Thus the contents of MAR are always available on the address lines of the memory bus.
 When a new address is loaded into MAR, it will appear on the memory bus at the beginning of the next
clock cycle.
 A read control signal is activated at the same time MAR is loaded.
 This means memory read operations requires three steps, which can be described by the signals being
activated as follows

 R1out, MAR in, Read
MDRinE, WMFC
MDRout,R2in.

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

STORING A WORD IN MEMORY

Writing a word into a memory location follows a similar procedure.
The desired address is loaded into MAR. Then, the data to be written are loaded into MDR, and a write
command is issued.
Example
Executing the instruction
Move R2, (R1) requires the following steps
1 R1out,MARin
2.R2out,MDRin,Write
3.MDRoutE,WMFC

Execution of a Complete Instruction

Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the memory location pointed to by R3)
Perform the addition
Load the result into R1

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

Execution of Branch Instructions

 A branch instruction replaces the contents of PC with the branch target address, which is usually
obtained by adding an offset X given in the branch instruction.
 The offset X is usually the difference between the branch target address and the address immediately
following the branch instruction.
 Conditional branch

First 3 steps are same as in the previous example.

Step 4: The contents of PC are transferred to reg ister Y by activating PC signals.
Step 5: The contents of PC and the offset field of IR register are added and result is saved in register Z by
activating corresponding signals.
Step 6: The contents of register Z are transferred to PC by activating Z and PC in signals

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

MULTIPLE BUS ORGRANIZATION

Single bus only one data word can be transferred over the bus in a clock cycle.
This increases the steps required to complete the execution of the instruction.
To reduce the number of steps needed to execute instructions, most commercial process provide multiple internal paths
that enable several transfer to take place in parallel.
3 buses are used to connect registers and the ALU of the processor.

All general purpose registers are shown by a single block called register file.

 There are 3 ports, one input port and two output ports.
 So it is possible to access data of three register in one clock cycle, the value can be loaded in one
 register from bus C and data from two register can be accessed to bus A and bus B.
 Buses A and B are used to transfer the source operands to the A and B inputs of the ALU.
 After performing arithmetic or logic operation result is transferred to the destination operand over bus C.
 To increment the contents of PC after execution of each instruction to fetch the next instruction, separate
unit is provided. This unit is known as incrementer.
 Incrementer increments the contents of PC accordingly to the length of the instruction so that it can
point to next instruction in the sequence.
 The incrementer eliminates the need
 Let us consider the execution of instruction, Add R1. R2, R3
 This instruction adds the contents of registers R2 and the contents of register R1and stores the result in
R1.

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 Digital Design and Computer Organization (BCS302)
Module-5 Basic Processing Unit

 With 3 bus organization control steps required for execution of instruction Add R1,R2, R3 are as
follows:
1. PCout, MARin
2. MARout, MDRinM, Read
3. MDRoutP, IRin
4. R2out, R3out, Add, R1in
Step 1: The contents of PC are transferred to MAR through bus B.
Step 2: The instruction code from the addressed memory location is read into MDR.
Step 3: The instruction code is transferred from MDR to IR register. At the beginning of step 4, the instruction
decoder interprets the contents of the IR. This enables the control circuitry to activate the control signals for step
4, which constitute the execution phase.
Step 4: two operands from register R2 and register R3 are made available at A and B inputs of ALU through bus A
and bus B.

These two inputs are added by activation of Add signal and result is stored in R1 through bus C

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