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i7525BN
2.5 Gbps Burst Mode
Laser Driver & Post Amplifier

Rev. B
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Introduction
General Description
The i7525BN is a combined burst mode laser driver and limiting amplifier for use within fiber optic
modules for FTTX applications.

The transmit block includes a high frequency modulator and a bias current generator. The bias
current can be controlled either by a fast settling APC loop, dual close loop or in open loop mode
which uses a temperature lookup table.

The receiver includes a limiting amplifier with programmable bandwidth. A Signal Detect/Loss Off
Signal function is implemented using the input signal modulation amplitude with user selectable
threshold and hysteresis.

Operating with a 3.3V supply and rated from -40 to +85°C ambient, the i7525BN is housed in a
28pin, 4X4mm, ROHS compliant, QFN package.

Features
1. Burst-Mode common anode laser driver with up to 90mA modulation and 100mA bias current

2. 5ns output switching in Burst Mode operation.

3. Single Closed, dual closed or open loop bias mode with temperature lookup table.

4. Limiting amplifier with programmable low pass filter and output swing

5. Device settings stored in external 8Kb EEPROM

6. Support CSFP multi-slave device address

7. Support TX-SD，TSSI and Rogue ONU alarm function

8. Eye safety for Laser Diode shutdown voltage control

9. Integrate Sample and Hold circuit for TX power monitor.

10. Integrate Digital Filter for abnormal Los pulse output.

11. Support TX power leveling (0dB,-3dB,-6dB)

12. Full compliance with SFF-8472 and SFP MSA

13. Provide I2C slave interface with speed up to 400KHz

14. Slave I2C internal pull up 10K resistance enable/Disable option

15. Support power down and sleep mode function

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Pin Description

GND

i7525BN Pin Description

Pin Name Direc Type Description
tion

1 LOS/SD O/P Open Drain Los of Signal Indication / Signal Detect output,

2 RX_OUTN O/P CML Limiting amplifier serial data output

3 RX_OUTP O/P CML Limiting amplifier serial data output

4 VCC_RX V Power Receiver Power supply

5 SDA_S I/O LVTTL I2C Slave interface data and 10k pull up on chip.

6 SCL_S I/O LVTTL I2C Slave interface clock and 10k pull up on chip.

7 SDA_M I/O OD I2C Master data (Support 8K bit EEPROM) and 10k pull up on chip.

8 SCL_M I/O OD I2C Master clock (Support 8K bit EEPROM) and 10k pull up on chip.

9 TX_DIS I/O CMOS Laser enable / disable

10 TX_INP I/P PECL Laser driver serial input

11 TX_INN I/P PECL Laser driver serial input

12 BENP I/P Any Level Burst enable signal

13 BENN I/P Any Level Burst enable signal

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14 MPD I/P Analog Monitor photodiode input (MPD)

15 BIASN O/P Open Drain Laser bias current output (complementary to IBIASP).

16 BIASP O/P Analog Laser bias current output

17 VCC_TX VDD Power Transmitter Power supply.

18 TX_OUTN O/P Analog Laser driver serial output

19 TX_OUTP O/P Analog Laser driver serial output

20 TX_FAULT O/P Open Drain Laser fail alarm

21 TX_SD O/P Open Drain Transmitter signal detect

22 APD_DAC I/P Analog APD BOOST circuit Feed Back. Inside built a current sink or source
DAC

23 RSSI I/P Analog Receiver signal strength indicator input from preceding TIA.

24 TSENSE I/P Analog ADC input, and Temperature sensor monitor

25 RX_INN I/P CML Limiting amplifier serial data input

26 RX_INP I/P CML Limiting amplifier serial data input

27 RX_SLEEP V CMOS Rx sleep enable

28 VCC_RX V Power Receiver Power supply

CP EPAD V GND Exposed Paddle (connect to GND)

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Package outline information

PACKAGE TYPE
JEDEC OUTLINE MO-220
PKG CODE VQFN(Y427)
SYMBOLS MIN. NOM. MAX.
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF.
b 0.15 0.20 0.25
D 4.00 BSC
E 4.00 BSC
e 0.40 BSC
K 0.20 - -
E2 2.50 2.60 2.65
D2 2.50 2.60 2.65
L 0.30 0.40 0.50

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Main Specifications
Absolute Maximum Ratings
Parameter Rating Units

Power supply (VCC-GND) -0.5 to +3.6 V

Operating ambient -40 to +85 ℃

Storage Temperature -65 to +150 ℃

Maximum laser bias current 100 mA

Maximum laser modulation current 100 mA

These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be
damaged. Reliable operation at these extremes for any length of time is not implied.

Chip Electrical Characteristics

(VCC = +2.97V to +3.63V, TA = -40°C to +85°C. Typic al values are at VCC = +3.3V, TA = +25°C, IBIAS =
50mA, IMOD = 30mA, unless otherwise noted.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VSUPPLY Supply Voltage 2.97 3.63 V

Excluding output bias

ICC Supply Current current and modulation 95 mA
current

DR Data rate 155 2500 Mbps

Transmitter DC Electrical Characteristics

(VCC = +2.97V to +3.63V, TA = -40°C to +85°C. Typic al values are at VCC = +3.3V, TA = +25°C, IBIAS = 5 0mA,
IMOD = 30mA, unless otherwise noted.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Transmitter input and output

VID Differential Input Swing AC couple 0.2 2.4 Vp-p

VCM Common-Mode input 1.8 V

VHI Disable Input High 2 V

VLO Disable Input Low 0.8 V

Fault Output Low Sinking 1mA, open collector 0.4 V

VTX_FAULT_HI TX_FAULT output voltage high 2 V

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VTX_FAULT_LO TX_FAULT output voltage low 0.4 V

IFAULT_TTL_HI TX_FAULT current high -4 mA

IFAULT_TTL_LO TX_FAULT current low 4 mA

VTX_SD_HI TX_SD output voltage high 2 V

VTX_SD_LO TX_SD output voltage low 0.4 V

ITX_SD_HI TX_SD output current high 2 mA

ITX_SD_LO TX_SD output current low 0.4 mA

VBENCM BEN Common mode input voltage 1.4 V

IBEN Maximum current on BEN pin 20 mA

VLASER Laser forward voltage 1.5 2 V

BIAS OUTPUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IBIAS Bias current setting range 1 100 mA

Bias off current 0.1 mA

Bias current monitor ratio 80

Bias Current Accuracy -15 15 %

Modulation Output

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IMOD Modulation current setting range 1 100 mA

Modulation current disabled 100 uA

Modulation-current Temperature
150 ppm
stability

Modulation-current setting error 20 ％

APC Loop

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

MD reverse voltage Respect to VCC 1.6 V

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MD Current Monitor Ratio IMD/IPCMON 0.9 mA/mA

IMD = 50uA -750 +750 ppm/℃

MD setting stability
IMD = 2200uA -500 +500 ppm/℃

IMD = 50uA -25 25

MD Setting accuracy %
IMD = 2200uA -15 15

APC burst initial time Note 1 Burst

Monitor-Diode input Current range 25 2200 uA

VMPD_IN Voltage at MPD relative to ground 1 V

ER Loop

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMD_MAX Maximum monitor For dual closed loop Ibias

photodiode capacitance for and Imodulation control 15
APC loop stability for dual
For closed loop average pf
loop mode. Includes all
Ibias or Imodulation control
associated parasitic 50
capacitances.

IMD_DCL Monitor photodiode current Dual Closed loop Ibias

adjustment range control 0 to 2200 uA
(dual close loop)

IMD_SCL Monitor photodiode average Single Closed loop

current adjustment range bias current control 0 to 2200 uA
(single close loop)
Note: With CCh bit3 turning on, the bias current setting of the first burst is loaded from the look up table.

Transmitter AC Electrical Characteristics

(VCC = +2.97V to +3.63V, TA = -40°C to +85°C. Typic al values are at VCC = +3.3V, TA = +25°C, IBIAS = 5 0mA,
IMOD = 30mA, unless otherwise noted.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Output edge speed 100 ps

Output overshoot 6 ％

RJTX Random jitter,RMS 1.5 ps

DJTX Deterministic Jitter, pk-pk 15 40 ps

TINIT Initial time delay 80 ms

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TRESET Minimum reset timing width 1 ms

TRISE Modulation current rise times 60 80 ps

TFALL Modulation current fall times 60 80 ps

TON TX_DISABLE assert time 10 us

TOFF TX_DISABLE De-assert time 1 ms

TBEN_ON Burst Enable Time 5 12.8 ns

TBEN_OFF Burst Disable Time 5 12.8 ns

Burst Length 100 ns

Burst interval 100 ns

TFAULT TX_FAULT assert time 100 us

Time TX_DISABLE must be

TRESET 10 us
asserted to reset TX_FAULT

TX-SD Delay Time 1 us

TX-SD width variation 100 ns

Receiver DC Electrical Characteristics

(VCC= +2.97V to +3.63V,TA=-40℃ to 85℃,unless otherwise noted. Typical values are at VCC= +3.3V ,TA=25℃)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Single-ended: 2 600
VIN Input Signal Voltage mV
Differential: 4 1200

Vos Eqvilent Input Offset Voltage 50 µV

VRXCM Common mode input voltage 1.4 V

Input Level Detect 7
VTH Vi=2.5Gbits/sPRBS2 -1 5 100 mV
Programmable Range
7
HYS LOS Hysteresis Range (optical) Vi=2.5Gbits/sPRBS2 -1 2 2.5 3 dB

VOUTCM Common mode output voltage 1.8 V

Differential, 4-bit
VOUTDIFF00 Minimum output swing 180 200 220 mVpp
programmable
Differential, 4-bit
VOUTDIFF01 Maximum output swing 800 880 960 mVpp
programma+ble
VOH CML Output High VCC V

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VLOSHIGH LOS/SD output voltage high 2 V

VLOSLOW LOS/SD output voltage low [10,11] 0.4 V

ILOS_OD LOS pin Max current (Open Drain) 20 mA

ILOS_TTL_HI LOS output current high (TTL) -4 mA

ILOS_TTL_LO LOS output current low (TTL) 4 V

APD DAC control

APDSOURCE Full scale DAC source current 2 mA

APDSink Full scale DAC sink current 512 uA

APD output compliance(sinking) 0.8 V

APD output
Vcc-1 V
compliance(sourcing)

Receiver AC Electrical Characteristics

(VCC=VCCA=VCCE=+2.97V to +3.63V,TA=-40℃ to 85℃,unless otherwise noted. Typical values are at
VCC=VCCA=VCCE=+3.3V ,TA=25℃)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

BW Input Bandwidth 2100 MHz

High pass 3dB point for
fH Input low frequency cutoff 10 kHz
RX system
RIN Input Resistance Single-ended 50 Ω

CIN Input Capacitance 2 pF

Output rise/fall time
Tr,Tf 20% to 80% 90 100 pS
(No Slew)
Output rise/fall time
Tr,Tf 20% to 80% 160 200 pS
(Fast Slew)

RXCrossing Eye crossing point 45 50 55 %

Tpwd Pulse-Width Distortion 20 pS

DJRx Deterministic jitter, pk-pk 15 40 pS

RJRx Random jitter, rms 3 pS

TLD Level Detect Time Constant 0.5 2 uS

Tloss_on LOS ASSERT Time 100 uS

Tloss_off LOS DE-ASSERT TIME 100 uS

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2-wire Serial Interface
The i7525BN has a pair of 2-wire serial interfaces: a slave for interfacing to a host for module
setup and programming, and a master for interfacing to an external EEPROM and for device
configuration after reset. Both interfaces communicate using the protocol described in this
section.
AC Characteristics
SYMBOL PARAMETER MIN TYP MAX UNITS

fSCL Clock frequency,SCL 400 KHz

tLOW Clock pluse width low 1.3 us

tHIGH Clock pulse width high 0.6 us

tAA Clock low to data out valid 0.1 0.9 us

Time the bus must be free
tBUF 1.2 us
before a new transmission can start
tHD.STA Start hold time 0.6 us

tSU.STA Start setup time 0.6 us

tHD.DAT Data in hold time 0 us

tSU.DAT Data in setup time 100 us

tSU.STO Stop setup time 0.6 us

tDH Data out hold time 50 ns

Digital Diagnostic Monitoring & Interface

Digital Diagnostic Monitoring & Interface section Characteristics

SYMBOL PARAMETER MIN TYP MAX UNITS

TRANGE Temperature sensor range -40 95 ℃

TXPADC Tx POWER monitor range 25 2400 uA

TXBADC Tx bias current monitor range 1 100 mA

VCCADC Supply voltage monitor range 2.6 4.0 V

RSSIADC RSSI monitor input range 1 2048 uA

ADCRANGE ADC input range 0 2.5 V

ADCr ADC INPUT RANGE 1M Ω

PORramp POWER ON RAMP 100 ms

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PORdelay Power-On Reset Delay 20 30 ms

TREADY Time after power-on to READY set 80 ms

TDDMI DDMI monitor sampling cycle time 4 ms

TSLEEP_TX Time to Sleep/Wake on Tx 500 1000 Ns

TSLEEP_TX Time to Sleep/Wake on Rx 1 ms

ISLEEP_TX Tx current in fast sleep mode 3 mA

ISLEEP_RX Rx current during sleep mode 1 mA

t_off Soft TX_DISABLE assert time 100 ms

T_on Soft TX_DISABLE de-assert time 100 ms

t_fault Soft TX_FAULT flag assert time 100 ms

t_loss_on Soft LOS flag assert time 100 ms

t_loss_off Soft LOS flag de-assert time 100 ms

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Functional Description
Functional Block Diagram

Function Block Diagram

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Power-up Sequence

The i7525BN has an on-chip power-on reset circuit to guarantee that the IC powers up correctly.
The digital functions, I2C interface is controlled by a digital state machine. During the period
before TREADY is set the transmitter outputs will be disabled and the receiver outputs will be
squelched. The LOS output will be asserted high. The POR assert level is typically 2.5V with a
hysteresis of around 100 mV. The i7525BN power-up sequence is shown in below and assumes
VCC_TX and VCC_RX are powered at the same time as VCC_Digital.

2.5V

<15ms

Operation mode
The I7525BN is highly configurable and offers multiple set-up configurations to suit various
applications and operating conditions. In particular the modulation and bias currents can be
programmed over temperature using several methods of control: Direct programming of
Modulation and Bias DACs, Temperature indexed Look-Up Table (LUT) control of Modulation and
Bias, Mean Power control using the Automatic Power Control (APC) loop and Automatic
Extinction Ratio control – a closed loop control method for controlling modulation current over
temperature.

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External EEPROM mode
The I7525BN can be interfaced with an external 8K bit EEPROM to provide a completely
re-writable SFF-8472 compliant digital diagnostic monitoring solution. The EEPROM should be an
8k bit device with 16-byte pages. The content of the EEPROM are loaded into the I7525BN
volatile registers at power-up. Note that some registers that contain dynamic data are not backed
up in EEPROM as they are updated on power-up by the state machine.

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Initialization Sequence
The initialization sequence for the i7525BN is shown in the flow chart diagram
below.

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Transmitter Features
The i7525BN transmitter consists of an internally biased differential input stage that can be DC
coupled or AC coupled depending on the mode of operation, a temperature compensated
modulation current output driver, a burst mode controlled high current bias driver and a burst
control input stage. The transmitter also contains sophisticated eye safety circuitry to comply with
single point failure transmitter faults as per IEC-60825 requirements.

Transmitter Input & Output Stage

The I7525BN transmitter input buffer provides the necessary drive to the laser driver output stage.
It includes an internal high impedance bias network (5kΩ), a limiting gain block that allows the
I7525BN to work with a range of input signals from 200 mVpp to 2400 mVpp including standard
LVPECL inputs, and is designed to be DC or AC-coupled. For high frequency applications an
external termination network must be implemented (differential 100Ω).

The laser driver output is designed to drive lasers in the common anode configuration using either
AC or DC coupling. For burst mode operation DC-coupling must be used. The laser driver circuit
delivers a maximum peak to peak modulation current of 100mA measured at the device output pin
TX_OUTP or TX_OUTN. By default the transmitter is non-inverting; however, to simplify the PCB
layout of differential signals the polarity of the data can be inverted by setting
TX_DATA_POLARYITY D1h <1> to ‘0’ or ‘1’.

Modulation current control

The modulator stage comprises of a switched current source capable of switching up to 90 mA of
modulation current through either the LASER+ or LASER- outputs. The modulation current is set
digitally and can be automatically adjusted to compensate for laser efficiency changes over
temperature.
For burst-mode operation and fast laser turn on times the laser modulation outputs must be DC
coupled to a common anode laser. The outputs can be either DC or AC coupled for non-burst
applications such as SFP modules.

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The modulation current can be controlled by two other control methods: (1) A temperature
indexed Modulation Look-up Table or (2) Automatic Extinction Ratio control that uses closed loop
feedback of the monitor photodiode current to generate an error signal to set and maintain a
constant transmitter extinction ratio over temperature and lifetime operating conditions of the
attached laser.

MOD_DAC
The MOD_DAC register is a 16-bit register that controls a 10-bit DAC. Therefore only the upper
10 bits of the register are actually used to program the DAC,

The modulation current is set directly from a 10-bit MOD_DAC, which has four possible modes of
operation. The available modes are shown in the table below.

MOD_DAC_SETUP D5h <3:2> DAC Mode

00 40mA Linear
01 90mA Linear
10 100mA Linear
11 100mA Pseudo-Logarithmic
MOD_DAC modes

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The modulation current follows the relationship described by one of the four equations below:

40mA Linear mode: Mod current(mA) =Offset + MOD_DAC[9:0]*0.0376 mA

90mA Linear mode: Mod current(mA) =Offset + MOD_DAC[9:0]*0.0891 mA
100mA Linear mode: Mod current(mA) =Offset + MOD_DAC[9:0]*0.1055 mA
109mA Pseudo-Logarithmic mode:
MOD current(mA) =
1. I=0.287+MOD_DAC[9:0]*0.03004 mA 0 ~255
2. I=7.98 +MOD_DAC[9:0]*0.050856mA 256~511
3. I=21+MOD_DAC[9:0]*0.097264 mA 512~767
4. I=45.9+MOD_DAC[9:0]*0.234764 mA 768~1023

The following chart shows actual transfer curve of modulation current against the MOD_DAC
register value.

i7525 MOD DAC

110
LOG 109mA
Linear 109mA
100
Linear 106mA
Linear 48mA
90

80

70

60
mA
50

40

30

20

10

0
0 100 200 300 400 500 600 700 800 900 1000
Code

Modulation LUT
A temperature indexed modulation current Look-Up Table (LUT) is available for use at address
A2h Table04. The LUT is enabled by setting bit MOD_LUT_EN D4h<6>

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MOD_MAX
The MOD_MAX function is provided to allow the user to set a maximum modulation current limit
beyond which a TX_FAULT condition will be asserted. The MOD_MAX function provides an 8-bit
control for setting the upper mod current. The I7525BN is designed to produce modulation currents
up to 100 mA.

Modulation Current Maximum (mA) = (MOD_MAX) * 256 * 2 * 0.001mA

Active Back Termination

The TX_OUTP and TX_OUTN modulator outputs have programmable back termination to
improve the optical output performance by optimizing the matching between the i7525BN and
laser diode component. The back termination helps to manage the overshoot in the modulated
current switched through the laser diode by minimizing reflections. The back termination is
composed of trimming network on the output driver, which adjusts the time constant of the output
damping on TX_OUTP/N. It is controlled by the value in BACK_TERM D2h <5:0>, and the setting
table is showing below.

BACK_TERM D2h<5:0> Ω)
R (Ω C (fF)
<111111> OPEN OPEN
<111110> 117.67 526
<111100> 85.1 526
<111000> 66.66 526
<110000> 54.79 526
<100000> 46.51 526
<000000> 40.4 526
Modulator Back Termination Settings

Bias Current Control

Bias control current of the i7525BN can operate with open or closed loop bias control. In either
mode the current setting for the bias DAC can be observed by reading BIAS_DAC_UPPER (ABh)
and BIAS_DAC_LOWER (ACh).

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Function Block of APC Block

BIAS_DAC
The BIAS_DAC register is a 16-bit register that controls a 12-bit DAC. Therefore only the upper 12
bits of the register are actually used to program the DAC,

The contents of both BIAS_DAC MSB and BIAS_DAC LSB are only transferred to the DAC when
BIAS_DAC LSB is written. This is done to ensure that all bias DAC updates occur in a single step,
even when a new value requires both registers to be changed.

The bias current is set directly from a 12-bit BIAS_DAC, which has four possible modes of
operation. The available modes are shown in the table below.

BIAS_DAC_SETUP DAh <7:6> DAC Mode

00 28mA Linear
01 78mA Linear
10 106mA Linear
11 106mA Pseudo-Logarithmic
BIAS_DAC modes

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The bias current follows the relationship described by one of the four equations below:

28mA Linear mode: Bias current(mA) =BIAS_DAC[11:0]*0.0071 mA

78mA Linear mode: Bias current(mA) =BIAS_DAC[11:0]*0.0208 mA
106mA Linear mode: Bias current(mA) =BIAS_DAC[11:0]*0.028 mA
106mA Pseudo-Logarithmic mode:
Bias current(mA) =
1. I=BIAS_DAC[11:0]*0.007 mA 0 ~1023
2. I=7.27 +BIAS_DAC[11:0]*0.0136 mA 1024~2047
3. I=21.4+BIAS_DAC[11:0]*0.032 mA 2048~3071
4. I=54.2+BIAS_DAC[11:0]*0.062 mA 3072~4095

The following chart shows actual transfer curve of bias current against the BIAS_DAC register
value.

i7525 BIAS DAC

110
LOG 106mA
Linear 106mA
100
Linear 78mA
Linear 28mA
90

80

70

60
mA
50

40

30

20

10

0
0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000
Code

Bias LUT
A temperature indexed bias current Look-Up Table (LUT) is available for use at address A2h
Table 5. The LUT is enabled by setting bit BIAS_LUT_EN D4h <7>.
The bias LUT contains 64 locations for BIAS_DAC values that are temperature indexed in 2.5°C
steps over the internal junction temperature range of -40°C to 120°C. The i7525BN uses the

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calibrated temperature value to index the LUT.
The i7525BN can also be set to interpolate between each of the 64 temperature locations so that
the BIAS_DAC is actually updated with a new temperature dependent bias current value every
1.25°C. This effectively turns the 64 location LUT into a 128 location LUT. This feature can be
enabled by setting bit BIAS_LUT_INTERPOL D4h <5>.

BIAS MAX
The BIAS_MAX function is provided to allow the user to set a maximum bias current limit beyond
which a TX_FAULT condition will be asserted. The BIAS_MAX function provides an 8-bit control
for setting the upper bias current. The i7525BN is designed to produce bias currents up to 100 mA.
If BIAS_MAX D8h <7:0> is set to FFh then the i7525BN will apply no upper limit to the bias
current output stage.
Bias Current Maximum (mA) = (BIAS_MAX) * 256 * 2 * 0.001mA

MD MAX
The MD_MAX D7h <7:2> function is provided to allow the user to set a maximum monitor
photodiode current limit beyond which a TX_FAULT condition will be asserted. The MD_MAX
D7h <7:2> function provides a 6-bit control for setting the upper monitor photodiode current. For
example, the MD_MAX register is set to EAh, the monitor current could go above 2400µA.

Maximum Monitor Current (uA) = (MD_MAX) *256 * 0.04

TX_SD status output

The i7525BN features a TX_SD LVTTL status output pin to indicate whether the laser is currently
activated or disabled. The i7525BN uses the monitor photodiode current to ascertain whether the
laser is transmitting light. The proportion can be selected via the TX_SD_MPD_THRESH DBh
<4:2> register, to values between 2.5% and 20% of IMPD_APCSET. If the actual monitor current
is greater than the threshold current then TX_SD will be asserted. The polarity of the TX_SD
function can be inverted by setting TX_SD_POLARITY DBh <0>

TX_SD_MPD_THRESHOLD DBh <4:2> MD_TX threshold

<000> 2.5%
<001> 5.0%
<010> 7.5%
<011> 10.0%
<100> 12.5%
<101> 15.0%

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<110 17.5%
<111> 20.0%

As the TX_SD function is derived directly from the monitor photodiode current it will assert high as
soon as a photocurrent is detected to be greater than the threshold current.

The default stimulus for the TX_SD monitor is an internally generated copy of the monitor
photodiode diode current. It is possible to configure the TX_SD to react to changes in the laser
forward voltage as an alternative method of generating the TX_SD monitor. To do this, set the
TX_SD_MODE bit. When using the TX_SD in this mode, the TX_SD assert threshold can be
adjusted by controlling TX_SD_VF_THRESHOLD CFh <7:4>. The table below shows these
controls in detail.

TX_SD_VF_THRESHOLD CFh <7:4> TX_SD threshold

<0111> VCC-1.3V
<0110> VCC-1.2V
<0101> VCC-1.1V
<0100> VCC-1.0V
<0011> VCC-0.9V
<0010> VCC-0.8V
<0001> VCC-0.7V
<0000> VCC-0.6V

Rogue ONU monitor

The internal TX_SD status monitor is asserted high for longer than the time pre-set in register
TX_SD_ROGUE_TIME B8h <7:4> then the i7525BN sets the ROGUE_ONU flag bit and the
I7525BN can also be set to indicate a hardware fault and/or disable the transmitter. Setting
TX_SD_ROGUE_TIME B8h <7:4> to 0h inhibits this function.

The BEN inputs are asserted high for a period longer than BEN_ROGUE_TIME B8h<3:0> then
the i7525BN sets the ROGUE_ONU flag bit and the i7525BN can also be set to indicate a
hardware fault and/or disable the transmitter. Setting BEN_ROGUE_TIME B8h <3:0> to 0h
inhibits this function.

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The Tx Power Low Alarm flag event occurs then this can also be used to trigger a ROGUE_ONU
flag and the i7525BN can also be set to indicate a hardware fault and/or disable the transmitter.
Setting the ROGUE_TXP_LO_EN C5h <1> bit will enable this function otherwise it will be
disabled.

The user can setup the i7525BN to assert a TX_FAULT upon a ROGUE_ONU condition occurring
by setting the ROGUE_FAULT bit. The user can reset the latched ROGUE_ONU condition by
ensuring the TX_DIS_ONU_CLR_EN C5h <0> bit is set and then toggling the TX_DISABLE
function.

A ROGUE_ONU condition is defined as either the Tx Power falling below a pre-defined level and
therefore asserting an Alarm flag or either the internal TX_SD function or BEN inputs remaining
high for a period longer than that defined by the register settings shown in the table below

Value (binary) BEN_ROGUE_TIME (B8h <3:0>) TX_SD_ROGUE_TIME (B8h <7:4>)

0000 Inhibited Inhibited
0001 1.64 ms 1.64 ms
0010 3.28 ms 3.28 ms
0011 6.55 ms 6.55 ms
0100 13.1 ms 13.1 ms
0101 26.2 ms 26.2 ms
0110 52.4 ms 52.4 ms
0111 105 ms 105 ms
1000 210 ms 210 ms
1001 419 ms 419 ms
1010 839 ms 839 ms
1011 1.68 sec 1.68 sec
1100 3.36 sec 3.36 sec
1101 6.72 sec 6.72 sec
1110 13.44 sec 13.44 sec
1111 26.88 sec 26.88 sec

Once a ROGUE_ONU condition has been detected the i7525BN can be programmed to respond
in a number of ways: The TX_SD output and/or TX_FAULT outputs can be asserted high to
indicate the ROGUE_ONU condition. i7525BN can be programmed to occur after a
pre-determined time set by the timer functions located in A2h Lower memory, registers
ROGUE_ONU_SETUP_TIMER 88h<7:0> (1uint=2mS) and ONU_FAULT_DELAY_TIMER 89h
<7:0>.

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ONU Fault delay time (mS)= ROGUE_ONU_SETUP_TIMER 88h<7:0> x ONU Fault Delay Timer
89h<7:0>

i7525BN can also be programmed to disable the transmitter after a pre-determined time set by the
timer functions located in A2h Lower memory, registers ROGUE_ONU_SETUP_TIMER
88h<7:0> (1uint=2mS) and TX_OFF_DELAY_TIMER 89h <7:0>.

TX off delay time (mS)= ROGUE_ONU_SETUP_TIMER 88h<7:0> x TX Off Delay Timer 89h<7:0>

If the timers in A2h lower memory are set to zero, then response time will be immediate for both of
these functions.

GPON power leveling

The i7525BN features a GPON Power Leveling mode which can automatically reduce the
transmitted output power by -3dB and -6dB as required by the ITU GPON standard. The table
below shows how the GPON power leveling function operates.

Power Level BEh <1:0>

GPON Power Level
BEh<1> BEh<0>
0 0 0 dB (default)
0 1 -3 dB
1 1 -6 dB
1 0 Not Used

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The power leveling function only applies to APC closed loop operation with Auto ER control or
Modulation LUT control and the register HOST_PON_EN C5h<2> must be setting enable . The
power leveling function cannot be used with bias current LUTs.

TX Cross point Adjust

The transmitter crossing level can be adjusted using the register TX_CROSSING CFh <3:0>
control . This gives a 4-bit control over the transmitter crossing point..
The crossing point versus the TX_CROSSING adjust control code is monotonic and is shown in
below table.

TX_CROSSING CFh<3:0> CROSSING

TX_CROSSING <3> TX_CROSSING <2> TX_CROSSING <1> TX_CROSSING <0> (%)
0 0 0 0 11
0 0 0 1 13
0 0 1 0 15
0 0 1 1 17
0 1 0 0 19
0 1 0 1 21
0 1 1 0 23
0 1 1 1 48
1 0 0 0 50
1 0 0 1 51
1 0 1 0 53.5
1 0 1 1 56
1 1 0 0 58.5
1 1 0 1 61
1 1 1 0 63.5
1 1 1 1 65

Eye safety stage

The i7525BN features in-built IEC-60825 Eye Safety circuitry that can be programmed as required
for the target application.

The i7525BN includes a TX_DISABLE hardware input and software control via I2C and a
TX_FAULT hardware output with software pin status indicator.

Programmable maximum bias and monitor current limits provide both eye safety and laser
end-of-life alarms.

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The APC loop and Auto ER loop are protected by a single-point of failure check such that any
opens or shorts to these control loops causes a TX_FAULT condition as required by IEC-60825.

If an APC/Auto ER loop fault occurs, then the TX_FAULT output will be asserted. In the same
instance, the bias and modulation currents will be internally disabled to turn off the laser.
In the case of an APC/Auto ER loop fault, the TX_FAULT output can only be reset and the outputs
enabled again by either cycling the I7525BN power supply or by toggling the TX_DISABLE input
for a duration greater than 10 µs.

The APC loop and Auto ER loops are protected against single-point failures by using the
BIAS_MAX D8h <7:0>, MD_MAX D7h <7:2> and MOD_MAX D9h <7:0> maximum limit
functions for bias current, monitor photodiode current and modulation current respectively. These
functions are described in more detail in their own sections within this datasheet and in the
memory map.

The i7525BN safety logic circuit diagram is shown in below. The safety logic can be completely
disabled by setting FAULT_INHIBIT DCh <2>. Any latched faults can be changed to non-latching
faults by setting LATCH_INHIBIT DCh <3>. The supply voltage monitor can also be disabled
such that any over or under voltage events on TX_VCC do not cause a TX_FAULT condition by
setting VCC_FAULT_INHIBIT DCh <6>.

The laser safety circuit monitors the device for potential faults. If a fault is detected, the pin FAULT
is asserted.

Eye safety Function Block

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A transmit fault can be raised by the following:
1. The temperature monitor detects that the measured temperature has gone out of range.
2. The bias current monitor detects that the measured transmit bias current has gone out of range.
3. The internal controller logic detects that a DMA from EEPROM has failed.
4. The bit of SOFT_TX_DISABLE 6Eh <6> is set to ‘1’
5. The voltage reference monitoring circuit detects that the supply voltage is incorrect.
6. The supply monitoring circuit detects that the power supply voltage is incorrect.

Before boot sequence completes, the fault will stay de-asserted soon after transmit fault condition
vanishes. After boot sequence completes.

If LATCH_INHIBIT DCh <3> = ‘0’ then a transmit fault condition will cause the FAULT pin to stay
asserted even if the fault condition goes away. The pin will stay asserted until either the chip is
power cycled or the pin DISABLE is set to ‘1’ or the register SOFT_TX_DISABLE 6Eh <6> is set
to ‘1’ or LATCH_INHIBIT DCh <3> is set to ‘1’.

If LATCH_INHIBIT DCh <3> = ‘1’ then the FAULT pin is de-asserted when the fault condition
goes away.

The i7525BN contains circuitry to shutdown the transmitter bias and modulation current if a
problem is detected. The conditions to cause a shutdown are:
1. The voltage reference monitoring circuit detects that the reference voltage is incorrect
2. The supply monitoring circuit detects that the power supply voltage is incorrect
3. The SOFT_TX_DISABLE 6Eh <6> is set to ‘1’
4. The internal controller logic has not successfully completed its initialization
5. The pin DISABLE is asserted

If a shutdown condition occurs, the modulation and bias currents are disabled. Conditions 1-4 can
be disabled from contributing to shutdown by setting SHUTDOWN_INHIBIT DCh <4> = ‘1’ . This
feature should be used with great caution.

The polarity of the DISABLE pin can be inverted by setting TX_DISABLE_POL BFh <2> .

The register bit TX_DISABLE_STATE 6Eh <7> reflects the status of the pin DISABLE (after
optional inversion using TX_DISABLE_POL BF<2>

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Alarms and Warning
The i7525BN can be set to automatically generate alarms and warnings if any of the five DDMI
monitor values exceed thresholds defined in A2h lower 00h to 27h.

TX_FAULT output
The TX_FAULT output can be configured by setting TX_FAULT_TYPE DCh <1> as either an
open drain output or a LVTTL output. When used in open drain mode, the TX_FAULT output pin
should be pulled high to TX VCC using a 4.7kΩ to 10kΩ resistor.

Initial Start-up
At power up or after the pin DISABLE is de-asserted the i7525BN can use a fast startup algorithm
to quickly settle the mean power control loop to the desired bias level. The algorithm can only be
invoked in closed loop, DC-coupled mode and after it has completed the low bandwidth digital
mean power control loop takes over to maintain the optical output power.

Timing Diagram of APC Block initial state

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Receiver Features
The i7525BN receiver section consists of input amplifier, which is followed by a programmable low
pass filter. The filtered signal is passed to a limiting stage and the receiver output is a CML driver.
Offset cancellation is provided by DC-feedback.

A Signal Detect (SD)/Loss Of Signal (LOS) alarm is provided to detect if the amplitude of the
AC-signal at the receiver input is below a programmable threshold. For a trans-impedance amplifier
with a constant gain, the LOS threshold corresponds to particular Optical Modulation Amplitude
(OMA).

Function Block Diagram of Receiver

Receiver Input Stage

The receiver input stage includes internal 50Ω single-ended termination resistors and is designed to
be AC-coupled to the trans-impedance amplifier. By default the receiver is non-inverting; however,
to simplify the PCB layout of differential signals the polarity of the data can be inverted by setting
RX_DATA_POLARITY BAh <0> to ‘0’ or ‘1’.

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Receiver Output Stage
The i7525BN data outputs are CML compliant and may be terminated using an AC-coupled
differential termination scheme. The CML output stage has two slew rate settings, selected by
RX_SLEW BEh <3>. The switching speed can be reduced in order to minimize electromagnetic
radiation by setting RX_SLEW BEh <3> to a ‘0’. Setting RX_SLEW BEh <3> to ‘1’ maximizes the
slew rate of the output. The possible settings are shown in the table below.
RX_SLEW BEh <3> Receiver Rate setting
1 90 ps
0 150 ps

The signal swing can also be adjusted. Setting OUTPUT_SWING BAh <4:3> to <11> results in a
highest receiver differential output swing. Setting OUTPUT_SWING BAh <4:3> to <00> results in a
lowest output swing. The levels available are shown in the table below.

OUTPUT_SWING BAh <4:3>

(RX Swing enhancement Bah<5>=0) Differential Output Swing (mV)
Output_Swing <4> Output_Swing <3>
0 0 320
0 1 400
1 0 680
1 1 840

For other application, Setting RX Swing enhancement Bah<5> to ‘1’, the RX output signal swing
OUTPUT_SWING BAh <4:3> is been enhanced to 1.5X，. The levels available are shown in the
table below.
OUTPUT_SWING BAh <4:3>
(RX Swing enhancement Bah<5>=1) Differential Output Swing (mV)
Output_Swing <4> Output_Swing <3>
0 0 480
0 1 600
1 0 1020
1 1 1260

RXOUTP/N can also be disabled by setting RX_SLEEP_ASSERT BFh <5> to a ‘1’ . The i7525BN
can automatically disable RXOUTP/N if a LOS condition is detected. To enable this function
LOS_TO_JAM should set RX_SQUELCH BBh <2> to ‘1’ . The i7525BN can be set-up so that the
transmitter outputs can be disabled on detection of a receiver loss of signal (LOS) condition. The
function is selected by setting TX_DISABLE_ON_RX_LOS D1h <7>.

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Receiver Filter Stage
The receiver signal path contains a digitally programmable low pass filter to provide band limiting in
the receive signal path and can be used to improve the system sensitivity when a higher bandwidth
TIA is used. The bandwidth of the filter is set to 0.7 x signal data rate selected and is controlled by a
2-bit control word RX_FILTER BAh <7:6>.The settings are shown the table in below.
RX_FILTER BAh <7:6>
Receiver Rate setting
Rx_Filter<7> Rx_Filter<6>
0 0 2.5Gbps
0 1 1.25Gbps
1 0 622M/155Mbps
1 1 622M/155Mbps

Signal detect / Loss of Signal stage

The i7525BN features a signal status output that is polarity selectable as a LOS or an SD status
output. A signal status function is implemented on-chip that uses a peak to detect by measuring the
optical modulation amplitude (OMA) and then compares this with a tunable reference level, set by
the digital interface. If the input amplitude falls below the preset level then the status output is
asserted.

Setting the LOS assert level

The signal amplitude measured at RXINP/N is compared to an analog threshold level set by the
register LOS_LEVEl BCh <7:0>. The graphics of the LOS Assert and De-Assert levels for all
Hysteresis setting in below. If the received signal amplitude does not exceed the threshold then the
LOS pin is asserted and the LOS indicator bit is set RX_LOS_STATE 6Eh <1>.

LOS/SD output polarity

The polarity of the LOS pin and register indicator bit are controlled by LOS_POLARITY BBh <0>. If
LOS_POLARITY BBh <0> is set to ‘0’ then the LOS pin is set high during a loss of signal condition.
Conversely, if LOS_POLARITY BBh <0> is set to ‘1’ then the LOS pin is set high when a signal is
detected.

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100
De-Assert (1.5dB Hysteresis)
90 Assert (1.5dB Hysteresis)
De-Assert (1.75dB Hysteresis)
80 Assert (1.75dB Hysteresis)
LOS Assert/De-Assert Level (mVpp)

De-Assert (2.0dB Hysteresis)

70 Assert (2.0dB Hysteresis)
De-Assert (2.5dB Hysteresis)
Assert (2.5dB Hysteresis)
60

50

40

30

20

10

0
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210
RX LOS_Level BCh <7:0>

RX LOS_Assert & Deassert Curve (1.25Gbps)

100
De-Assert (1.5dB Hysteresis)
90 Assert (1.5dB Hysteresis)
De-Assert (1.75dB Hysteresis)
80 Assert (1.75dB Hysteresis)
LOS Assert/De-Assert Level (mVpp)

De-Assert (2.0dB Hysteresis)

70 Assert (2.0dB Hysteresis)
De-Assert (2.5dB Hysteresis)
Assert (2.5dB Hysteresis)
60

50

40

30

20

10

0
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
RX Los_Level BCh <7:0>
RX LOS_Assert & Deassert Curve (2.5Gbps)

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Setting the LOS Hysteresis
LOS detection has hysteresis, the level of which can be selected to one of four levels using register
LOS_HYSTERSIS BAh <2:1>. Details are shown in the table below.
LOS_HYSTERSIS BAh <2:1>
HYST Setting (optical)
LOS_HYSTERSIS <2> LOS_HYSTERSIS <1>
0 0 1.50 dB
0 1 1.75 dB
1 0 2.00 dB
1 1 2.50 dB

LOS/SD output type

The LOS/SD pin can be programmed as e￥ither an open drain output or a true LVTTL output. As
an open drain output the LOS/SD pin is typically tied to VCC_RX via a 4.7kΩ to 10kΩ pull-up resistor.
The output type is set using the register control RX LOS TYPE BBh <1>. If RX LOS TYPE BBh <1>
is set to ‘0’ then the LOS pin is open drain output. Conversely, if RX LOS TYPE BBh <1> is set to ‘1’
then the LOS pin is LVTTL output.
When RX LOS is assert, RX DDMI must be reported to -40dB, Setting the register Report -40db
when Rx Losing DCh <7> to ‘1’

Receiver output squelch function

The receiver outputs can be squelched during a Loss of Signal condition. To enable squelching of
the outputs the bit should be set in register RX_SQUELCH BBh <2>.

APD DAC Control

An internal 8 bit digital to analog current sink/source converter is used to help control Avalanche
photo detector. The digital codes to control the DA converter reside in the look up table. The APD
DAC is controlled by setting register bytes APD_DAC 87h <7:0> and APD_DAC_EN DAh <3>.

APD_SINK_SRCN_SEL E3h <3> APD_SRCNCURR_SEL E3h <6:4> APD Source Current

0 <0 0 0> 256 uA
0 <0 0 1> 512 uA
0 <0 1 0> 1024 uA
0 <0 1 1> 1536 uA
0 <1 0 0> 2048 uA

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APD_SINK_SRCN_SEL E3h <3> APD_SINKCURR_SEL E3h <7> APD Sink Current
1 1 256 uA
1 0 512 uA

The output current set can be calculated using the following formula that is shown in below.
Source current mode:
1. 2048uA =APD_DAC[7:0]*8 uA
2. 1536uA =APD_DAC[7:0]*6 uA
3. 1024uA=APD_DAC[7:0]*4 uA
4. 512uA=APD_DAC[7:0]*2 uA
5. 256uA=APD_DAC[7:0]*1 uA
Sink current mode:
1. 256uA =APD_DAC[7:0]*1 uA
2. 512uA =APD_DAC[7:0]*2 uA
The APD DAC can be controlled via a temperature indexed LUT located at A2h Table 6 , C0h to FFh.
When the register APD_DAC_LUT_EN BDh <7> is set to “1” that the APD DAC LUT is enabled, the
i7525BN sets the APD DAC output based on the programmed DAC value indexed to the current
temperature.

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Internal Diagnostic Monitoring
The i7525BN contains a multi-channel 10it auto-ranging A/D converter to digitize the following
analogue monitors within the IC: Supply voltage, Transmitter bias current, Transmitted output power.
The i7525BN also contains an on-chip temperature sensor which is also digitized using the A/D
converter. In conjunction with an external RSSI monitor input, the i7525BN can digitize the received
average power. In addition to the five monitored functions for SFF-8472, the I7525BN also provides
a digitized monitor of the transmitter modulation current.

The flow chart of i7525BN DDMI Calibration is shown in below.

Slope write 1
(0x90~0x9B)
Offset write 0
(0xA0~0xA9)

Read ADC
(0x60~0x69)

Cal.
Slope & offset

Write to slope & offset

(0x90~0x9B)
(0xA0~0xA9)

Check DDMI ADC

(0x60~0x69)

Temperature Monitor
The temperature monitor can theoretically report temperature from -40 °C through to 128 °C
although this is well beyond the absolute maximum operating range of the i7525BN .

External ADC input

An external ADC input channel is available for off-chip monitoring of analogue signals – for example
an external temperature sensor.

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Tx Bias Current Monitor
The Tx bias current monitor can report the transmitter bias current from 0.0 mA through to 100 mA
although the I7525BN is designed to provide up to 100 mA of bias current.
The register DDM_TX_BIAS Table03 64h<7:0> and 65h<7:0> therefore should be interpreted as
follows:
Tx bias Current (mA) = DDM_TX_MOD * 2 uA / 1000

Tx Power Monitor
The i7525BN transmitted power monitor reports the mean transmitter output power as follows:
(1) In non-burst operation the monitor is directly proportional to the mean transmitted output power
derived from the monitor feedback current which is constantly maintained by the automatic power
control loop.
(2) In burst mode operation the monitor is derived from the averaged monitor photocurrent during
successive burst-on periods. During a burst-off period, the transmitted power is assumed to be zero
( digitally detect BEN signal and report 0 during burst off) and therefore excluded from the averaging
function. A voltage proportional to the monitor current is generated internally within the IC and
sampled with a capacitor CMPD only when BEN is high. For non-burst operation, BEN is always tied
high.

Rx Power Monitor
The i7525BN features a receiver signal strength indicator (RSSI) input for monitoring the current
from an external RSSI output from a trans-impedance amplifier (TIA).

The RSSI input monitor can be configured to accept both Sink (default) or Source output monitors
from the preceding TIA. The polarity of the RSSI input is configured to Source mode by setting
RSSI_SOURCE_SINK E2h <6>. This activates an internal current mirror which changes the input
polarity.

The output from the internal RSSI current mirror is fed into an auto-ranging analog-to-digital
converter that can digitize TIA monitor currents from 90 nA up to 2 mA – equivalent to an average
optical input power range of -40 dBm to +3 dBm.

A 10nF capacitor should be connected between the RSSI pin input and ground to reduce noise at
the The Rx Power monitor can report the RSSI current up to 2048 µA.
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Tx Modulation Current Monitor
The Tx modulation current monitor can report the transmitter modulation current from 0.0 mA
through to 100 mA although the i7525BN is designed to provide up to 90 mA of modulation current.
The register DDM_TX_MOD Table03 78h<7:0> and 79h<7:0> therefore should be interpreted as
follows:
Tx Modulation Current (mA) = DDM_TX_MOD * 2 uA / 1000

Control Interface
The host communicates with the i7525BN and the EEPROM via the slave Two Wire Interface
(TWI/I2C) pins of the i7525BN. Slave addresses A2h are supported. If a transaction arriving at the
slave interface is addressed to A2h, then the i7525BN examines the register address in order to
decide how the transaction should be processed.

When the i7525BN comes out of reset, the state machine uses the master two wire interface to read
configuration bytes out of EEPROM. This data is used to configure the internal registers of the
device.

two-wire Serial Interface

The i7525BN has a pair of 2-wire serial interfaces: a slave for interfacing to a host for module setup
and programming, and a master for interfacing to an external EEPROM and for device configuration
after reset. Both interfaces communicate using the protocol described in this section.

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AC Characteristics

BUS Timing
SCL: Serial Clock, SDA: Serial Data I/O

Framing and Data Transfer

The two-wire interface comprises a clock line (SCL) and a data line (SDA). An individual transaction
is framed by a start condition and a stop condition. A start condition occurs when a bus master pulls
SDA low while the clock is high. A stop condition occurs when the bus master allows SDA to
transition low-to-high when the clock is high. Within the frame, the master has exclusive control of
the bus. The i7525BN supports REPEAT START conditions whereby the master may
simultaneously end one frame and start another without releasing the bus by replacing the STOP
condition with a START condition.

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Within a frame, the state of SDA may only change when SCL is low. A data bit is transferred on a
low-to-high transition of SCL. Data is arranged in packets of 9 bits. The first 8 bits represent data to
be transferred (most significant bit first). The last bit is an acknowledge bit. The recipient of the data
holds SDA low during the ninth clock cycle of a data packet to acknowledge (ACK) the byte. Leaving
SDA to float high on the ninth bit signals a not-acknowledged (NACK) condition. The interpretation
of the acknowledge bit by the sender will depend on the type of transaction and the nature of the
byte being received.

Device Addressing
The first byte to be sent after a START condition is an address byte. The first seven bits of the byte
contain the target slave address (MSB first). The eighth bit indicates the transaction type – ‘0’ = write,
‘1’ = read. Each slave interface on the bus is assigned a 7-bit slave address. If no slave matches the
address broadcast by the master then SDA will be left to float high during the acknowledge bit and
the master receives a NACK. The master must then assert a STOP condition. If a slave identifies the
address then it acknowledges the master and proceeds with the transaction identified by the type
bit.

Address decoding example

Write Transaction
Show an example of a write transaction. The address byte is successfully acknowledged by the
slave, and the type bit is set low to signify a write transaction. After the acknowledge the master
sends a single data byte. All signal is controlled by the master except for the SDA line during the
acknowledge bits. During the acknowledge the direction of the SDA line is reversed and the slave
pulls SDA low to return a ‘0’ (ACK) to the master.

Write Transaction

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If the slave is unable to receive data then it should return a NACK after the data byte. This will cause
the master to issue a STOP and thus terminate the transaction. The i7525BN interprets the first data
byte as a register address. This will be used to set an internal memory pointer. Subsequent data
bytes within the same transaction will then be written to the memory location addressed by the
pointer. The pointer is auto-incremented after each byte. There is no limit to the number of bytes
which may be written in a single burst to the internal RAM of the i7525BN. If, however, the write
access is destined for the EEPROM the requirements of page writes specified for the EEPROM
apply.

If the slave is not ready to receive a byte then it may hold SCL low immediately after the
acknowledge bit. When SCL is released the master starts to send the next byte. This is known as
clock stretching. The i7525BN slave interface will not clock stretch at up to 100 kHz SCL frequency.

Read Transaction

Read Transaction

Show an example of a 2 byte read transaction. The address byte is successfully acknowledged by
the slave, and the type bit is set high to signify a read. After the ACK the slave returns a byte from
the location identified by the internal memory pointer. This pointer is then auto-incremented. The
slave then releases SDA so that the master can ACK the byte. If the slave receives an ACK then it
will send another byte. The master identifies the last byte by sending a NACK to the slave. The
master then issues a STOP to terminate the transaction.

Thus, to implement a random access read transaction, a write must first be issued by the master
containing a slave address byte and a single data byte (the register address). This sets up the
memory pointer. A read is then sent to retrieve data from this address.

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I2C Address Change for CSFP application

The i7525BN can be used in CSFP applications and supports multiple channel addressing. The
CSFP standard requires that an SFP form factor module contains two separate SFF-8472 DDMI
channels which are designated Channel 1 and Channel 2.

The i7525BN slave I2C interface responds to address A0h and A2h by default. The default
addresses can be changed so that the i7525BN can respond to other address pairs. To change the
i7525BN I2C address the user writes the new base address to register I2C_ADDRESS (A2h Table
3, C3h <7:2>).

In order for the new I2C address held in C3h to be used by the i7525BN, then the I2C_PASSWORD
byte (A2h Table 3, C2h) should contain the value C5h. If I2C_PASSWORD is not set to value C5h
then the I2C_ADDRESS value will not be valid and the i7525BN will continue to use the default I2C
addressing.

In a CSFP application two i7525BN ICs may be connected to the same host I2C bus. Programming
of the two i7525BN devices can be carried out without the need for powering down one device while
the other is programmed. The i7525BN has a feature that gives the user the ability to disable the
device I2C interface via the TX_DISABLE pin. This feature is enabled by setting register bit
TX_DIS_CSB (A2h Table 3, 80h <1>). Once enabled, the TX_DISABLE pin effectively becomes a
chip select bar (CSB) pin. When the TX_DISABLE pin is held low, the device will respond to I2C
transactions normally. When the TX_DISABLE pin is held high, the device will not respond to I2C
transactions. To program a different I2C slave address on Channel 2 the following sequence needs
to be followed.

1. Power on both i7525BN devices on Channel 1 and Channel 2.

2. Set TX_DIS_CSB register bit to enable. This will take effect in both i7525BN devices.

3. Set TX_DISABLE pin high on Channel 1 and low on Channel 2. This will disable Channel 1 from
I2C communications but still allow I2C communications on Channel 2.

4. Set the I2C_PASSWORD byte (A2h Table 3, C2h) should to value C5h. This will setting the
I2C_ADDRESS value is valid

5. Send required I2C commands to change I2C address in i7525BN device on Channel 2 (Set the
register bits I2C_ADDRESS (A2h Table3 C3h <7:2>) to 101100b).

6. Power on cycle module. The new I2C slave address on Channel 2 will now be in use.

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An example of CSFP channel 2 I2C addresses are shown below

CSFP DDMI
Address “A0 Page” “A2 Page” I2C_ADDRESS (A2h Table3 C3h <7:2>)
Channel
Channel 1 Default A0h A2h 000000b or 101000b
Channel 2 Option 0 B0h B2h 101100b
Option 1 C0h C2h 110000b
Option 2 D0h D2h 110100b
Option 3 E0h E2h 111000b
Option 4 F0h F2h 111100b
Option 5 10h 12h 000100b
Option 6 20h 22h 001000b
Option 7 30h 32h 001100b
Option 8 40h 42h 010000b
Option 9 50h 52h 010100b
Option 10 60h 62h 011000b
Option 11 70h 72h 011100b
Option 12 80h 82h 100000b
Option 13 90h 92h 100100b

Password Protection Levels

The i7525BN supports three levels of password protection so that the i7525BN user can protect the
content of A2h Tables 3, 4, 5 and 6 from the end customer.

The first level of password access only gives the host access to locations at A0h and A2h table 0/1
via the slave I2C interface. The second level of password access gives the host access to all of the
memory map excluding the i7525BN factory settings area at location A2h table 3 (80h to FFh).

PW0 provides the least access to the i7525BN memory locations and is essentially the default
password level set.

The PW1 and PW2 levels can be programmed by the user by setting the 32 bit password level
values at locations B0h~B3 (PW1) and B4~B7h (PW2) in A2h Table 3.

Once the user has determined the i7525BN user settings and set SAFE_MODE_STARTUP D0h
<7:0> byte to value 6Ah then the i7525BN passwords will be set to whatever the content of the
PW1_VALUE and PW2_VALUE bytes are.

Sleep Modes
The transmitter and receiver of the i7525BN can be placed into low power sleep modes using either
software or hardware control.

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Software control of Sleep Modes
The Tx and Rx can be independently placed into sleep mode using the register bits
RX_SLEEP_ASSERT BFh <5>, TX_SLEEP_ASSERT BFh <4> and SOFT_TX_DISABLE 6Eh
<6> . The SOFT_TX_DISABLE 6Eh <6> control of the TX_SLEEP function is enabled by setting the
register TX_SLEEP_MODE BFh <0>.

Hardware control of Sleep Modes

The transmitter and receiver sleep modes can be activated independently via hardware input pins
on the i7525BN.

TX Sleep control
The transmitter can be placed into sleep mode by using the TX_DISABLE input pin (9). The
TX_DISABLE pin can be configured as the Tx sleep control pin by setting bit TX_SLEEP_MODE
BFh <0>. When this bit is set then the TX_DISABLE will place the transmitter into a low power sleep
mode and also disable the transmitter. This applies to both hardware and software TX_DISABLE
assertions. TX_SLEEP must be de-asserted at least 128 µs before TX_DISABLE is de-asserted.

RX Sleep control
The receiver can be placed in a low power sleep mode by asserting the RX_SLEEP pin (27) high
using an external hardware control or by setting RX_SLEEP_ASSERT BFh <5> in the user
registers. By setting bit RX_SLEEP_CONTROL BFh <1> the receiver sleep mode can be entered
via the TX_DISABLE / TX_SLEEP pin or via the soft TX_DISABLE register. Therefore asserting
TX_DISABLE will result in both the Tx and Rx entering a sleep state. The RX_SLEEP hardware
input will also still function when this mode is selected. This allows the user to control both the Tx
and Rx sleep modes with one hardware input (TX_DISABLE) and software control.

Tx and RX hardware Sleep control Polarity inversion

The TX_DISABLE (TX_SLEEP) and RX_SLEEP hardware inputs can be polarity inverted so that
instead of these pins having to be driven logic high to force the Tx and/or Rx into sleep mode the
pins have to be driven low. The TX_DISABLE polarity inversion function TX_DISABLE_POL BFh
<2> inverts the hardware input signal and applies to both TX_DISABLE and TX_SLEEP functions.

The RX_SLEEP polarity inversion function RX_SLEEP_POL BFh <3> inverts the hardware input
signal for RX_SLEEP. The soft control functions are NOT polarity inverted.

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5.Memory and Register Map

i7525BN Memory Map

Byte 7F of address A2h is used to select further tables that appear at addresses A2h 80h-FFh. The
tables that can be addressed along with their functions are described below:

Table 00h/01h User Writeable Area

Table 03h i7525BN Control and Configuration Table
Table 04h ERC LUT and Modulation LUT
Table 05h VF THRESHOLD LUT and Bias LUT
Table 06h APCSET LUT and APD DAC LUT

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A2h Lower (00h to 6Eh) Memory Area Register Map
Address
Function R/W Type NOTES
Dec Hex
000~007 00~07 DDMI TEMPERATURE THRESHOLD SET R/W E High / Low Alarm & High / Low Warning
008~015 08~0F DDMI VCC THRESHOLD SET R/W E High / Low Alarm & High / Low Warning
016~023 10~17 DDMI TX BIAS THRESHOLD SET R/W E High / Low Alarm & High / Low Warning
024~031 18~1F DDMI TX POWER THRESHOLD SET R/W E High / Low Alarm & High / Low Warning
032~039 20~27 DDMI RX POWER THRESHOLD SET R/W E High / Low Alarm & High / Low Warning
040~055 28~37 Bit7~Bit0 : Reserved ----- E -----
056~075 38~4B RX_POWER external calibration constant R/W E Signal precision floating point calibration data
076~079 4C~4F TX_BIAS external calibration constant R/W E Fixed decimal calibration data
080~083 50~53 TX_POWER external calibration constant R/W E Fixed decimal calibration data
TEMPERATURE external calibration
084~087 54~57 R/W E Fixed decimal calibration data
constant
088~091 58~5B VCC external calibration constant R/W E Fixed decimal calibration data
092~094 5C~5E Bit7~Bit0 : Reserved ----- E -----

Byte 5Fh contains the low order 8 bits of the

095 5F CHECKSUM R/W E
sum of bytes 00h-5Eh. Set by the user.
096~097 60~61 DDMI MONITOR FOR TEMP R S
098~099 62~63 DDMI MONITOR FOR VCC R S
100~101 64~65 DDMI MONITOR FOR TX BIAS R S
102~103 66~67 DDMI MONITOR FOR TX POWER R S
104~105 68~69 DDMI MONITOR FOR RX POWER R S
00h=MCU Mode
106 6A OPERATION MODE R S
01h=EEPROM
107~109 6B~6D Bit7~Bit0 : Reserved ----- S -----
Digital state of the TX_DISABLE input pin.
Bit7 : TX_DISABLE STATE R S
Updated within 100ms of change on pin.
Enables direct control of the transmitter via I2C.
Bit6 : SOFT_TX_DISABLE R/W S
1= Disable the transmitter.
1=On the occurrence of a rogue ONU condition.
Bit5 : ROGUE ONU R/W S
0=Reset.
Bit4 : Reserved ----- S -----
Set to 1 if TXP_LO_Flag has been set by alarm
110 6E Bit3 : ROGUE_TXP_LO_FLAG R/W S threshold and the Rogue_TXP_LO_EN bit is
set. Latched or non-latched.
Digital state of the TX_Fault pin out (update
Bit2 : TX_FAULT_STATE R S
within 100 ms)
Digital state of the RX_LOS pin out (update
Bit1 : RX_LOS_STATE R S
within 100 ms)
Indicates i7525BN has achieved power and
Bit0 : DATA_READY_BAR_STATE R S data is ready. Bit stays high until data is ready
at which time the i7525BN sets this bit low.

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A2h Lower (6Fh to 7Fh) Memory Area Register Map
Address
Function R/W Type NOTES
Dec Hex
Bit7~Bit5 : Reserved ----- S -----
Digital state of the RX_SLEEP input pin.
Bit4 : RX_SLEEP_STATE R S
Updated within 100ms of change on pin.
Bit3 : Reserved ----- S -----
111 6F Digital state of the TX_SLEEP input pin.
Bit2 : TX_SLEEP_STATE R S Updated within 100ms of change on pin (only
valid if Tx sleep mode is enabled)
Bit1 : Reserved ----- S -----
Set to reset TSSI counter and will be clear after
Bit0 : TSSI function Reset W/R S
setting 1 : Reset Enable
Bit7 : TEMP. HIGH ALARM FLAG
Bit6 : TEMP. LOW ALARM FLAG
Bit5 : VCC HIGH ALARM FLAG
Bit4 : VCC LOW ALARM FLAG Temperature/ VCC/ Tx Bias/ Tx Power :
112 70 R S
Bit3 : TX BIAS HIGH ALARM FLAG High/Low Alarm Flags
Bit2 : TX BIAS LOW ALARM FLAG
Bit1 : TX PWR HIGH ALARM FLAG
Bit0 : TX PWR LOW ALARM FLAG
Bit7 : Rx Pwr High Alarm Flag
R S Rx Power High/Low Alarm Flags
113 71 Bit6 : Rx Pwr Low Alarm Flag
Bit5~Bit0 : Reserved ----- S -----
114 72 i7525BN SERIAL ID R S i7525BN ID is 28h
115 73 CHIP VERSION R S Chip REV.
Bit7 : TEMP. HIGH WARNING FLAG
Bit6 : TEMP. LOW WARNING FLAG
Bit5 : VCC HIGH WARNING FLAG
Bit4 : VCC LOW WARNING FLAG Temperature/ VCC/ Tx Bias/ Tx Power :
116 74 R S
Bit3 : TX BIAS HIGH WARNING FLAG High/Low Warn Flags
Bit2 : TX BIAS LOW WARNING FLAG
Bit1 : TX PWR HIGH WARNING FLAG
Bit0 : TX PWR LOW WARNING FLAG
Bit7 : RX PWR HIGH WARNING FLAG
R S Rx Power High/Low Warn Flags
117 75 Bit6 : RX PWR LOW WARNING FLAG
Bit5~Bit0 : Reserved ----- S -----
118~119 76~77 CHIP VERSION R S Chip REV.
120~121 78~79 TX MODULATION CURRENT MONITOR R S Monitor TX modulation current
Password Level :
122 7A PASSWORD LEVEL R S
00h=(User)，01h=(PWE1)，02h=(PWE2)
123~126 7B~7E PASSWORD ENTRY W S Set all value is FFh (Default) on power-up.
This byte selects the A2h table memory area to
be accessed via addresses A2h, 80h to FFh.
00h/01h = User Writeable Area
127 7F TABLE SELECT BYTE R/W S 03h= i7525 Control & Status page
04h= ERC LUT and Modulation LUT
05h= VF Threshold LUT and Bias LUT
06h= APCSET and APD DAC LUT

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CH Create i7525BN
A2h Table 03h – i752X Control and Configuration Table
The i752X control settings are contained at address A2h within Table 03h, from 80h to FFh. This is
accessed by writing 03h to the table select byte at address A2h, register 7Fh.

Address
Function R/W Type NOTES
Dec Hex

Bit7~Bit2 : Reserved ----- S -----

Set to enable chip select from Tx_Disable pin
TX_DIS_CSB – When register bit set to 1 the
TX_Disable input pin can be used as a CSB (Chip
Select Bar) input.
128 80 Bit1 : TX_DIS_CSB R/W S When the TX_DISABLE pin is high in this mode the
I2C communications will be disabled. This function
is intended for use in programming different device
I2C addresses on modules where multiple devices
share a common I2C interface.
Bit0 : Reserved ----- S -----

129 81 Bit7~Bit0 : Reserved ----- S -----

130 82 Bit7~Bit2 : Reserved ----- S -----

The modulation DAC current value.

1. When Auto ER enable (D5h<0>=1), this current
MOD_DAC_CURRENT
value is MOD_DAC of auto locked for dual close
130~131 82~83 82h Bit1~Bit0 : MOD_DAC_C(MSB) R/W S
loop.
83h Bit7~Bit0 : MOD_DAC_C(LSB)
2. When AUTO ER disable (D5h<0>=0), MOD_L
UT_EN (D4h<6>=1), the current value is MOD
LUT of real time for open loop.
132 84 Bit7~Bit4 :Reserved R/W S -----

The bias DAC current value.

1. When APC_EN enable (D4h<2>=1), this current
BIAS_DAC_CURRENT
value is BIAS_DAC of auto locked for dual close
132~133 84~85 84h Bit3~Bit0 : BIAS_DAC_C(MSB) R/W S
loop.
85h Bit7~Bit0 : BIAS_DAC_C(LSB)
2. When APC_EN disable (D4h<2>=0),
BIAS_LUT_EN (D4h<7>=1), the current value is
BIAS LUT of real time for open loop.
Sets the target APC reference monitor current

134 86 APCSET_DAC_CURRENT R/W S When MDR_LUT_EN disable (D5h<1>=0) and

APC_LUT_EN enable (D4h<3>=1), the value is
APC LUT of real time for open loop.

Sets the APD DAC value

135 87 APD_DAC R/W S APD_DAC_LUT_EN (BDH<7>= 0)
It can be manual adjust the APD DAC

136 88 ROGUE ONU SETUP TIMER R/W E Rogue ONU Setup Timer (1uint = 2mS)

ONU Fault Delay Time =Rogue ONU Setup

137 89 ONU FAULT DELAY TIMER R/W E
Timer(88h) * ONU Fault Delay Timer

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Address
Function R/W Type NOTES
Dec Hex

Tx Off Delay Time =Rogue ONU Setup Timer(88h) *

138 8A TX OFF DELAY TIMER R/W E
Tx Off Delay Timer

Set to enable DDMI alarm flags

Bit7 : Temp High Alarm Enable
Bit6 : Temp Low Alarm Enable
Bit5 : VCC High Alarm Enable
139 8B ALARM FLAGS ENABLE 1 R/W E Bit4 : VCC Low Alarm Enable
Bit3 : Tx Bias High Alarm Enable
Bit2 : Tx Bias Low Alarm Enable
Bit1 : Tx Power High Alarm Enable
Bit0 : Tx Power Low Alarm Enable

Set to enable DDMI alarm flags

Bit7 : Rx Power High Alarm Enable
140 8C ALARM FLAGS ENABLE 2 R/W E
Bit6 : Rx Power Low Alarm Enable
Bit5~Bit0 : Reserved

Set to enable DDMI warning flags

Bit7 : Temp High Warning Enable
Bit6 : Temp Low Warning Enable
Bit5 : VCC High Warning Enable
141 8D WARNING FLAGS ENABLE 1 R/W E Bit4 : VCC Low Warning Enable
Bit3 : Tx Bias High Warning Enable
Bit2 : Tx Bias Low Warning Enable
Bit1 : Tx Power High Warning Enable
Bit0 : Tx Power Low Warning Enable

Set to enable DDMI warning flags

Bit7 : Rx Power High Warning Enable
142 8E WARNING FLAGS ENABLE 2 R/W E
Bit6 : Rx Power Low Warning Enable
Bit5~Bit0 : Reserved

Test the Tx optical signal status

Bit7 : TSSI TX OPTICAL TEST R/W E 0= TX power disable after TSSI
1=TX power enable after TSSI
143 8F
Bit6~Bit5 : Reserved ----- E -----

00000= Open Loop or Single Close Loop setting

Bit4~0 : IMOD_SET R/W E
10001= Dual Close Loop setting

144~145 90~91 Bit7~Bit0 : Reserved ----- E -----

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Address
Function R/W Type NOTES
Dec Hex

146~147 92~93 VCC SLOPE R/W E VCC Slope calibration constant.

148~149 94~95 TX_BIAS_SLOPE R/W E Tx Bias Slope calibration constant.

150~151 96~97 TX_POWER_SLOPE R/W E Tx Power Slope calibration constant.

152~153 98~99 RX_POWER_SLOPE (C1) R/W E Rx Power Slope C1 calibration constant.

154~155 9A~9B RX_POWER_SLOPE (C2) R/W E Rx Power Slope C2 calibration constant.

Default value for dual close loop must be setting

156~159 9C~9F Bit7~Bit0 : Reserved ----- E
1B 55 77 77

160~162 A0~A1 TEMP OFFSET R/W E Temperature Offset calibration constant.

162~163 A2~A3 VCC OFFSET R/W E Vcc Offset calibration constant.

164~165 A4~A5 TX_BIAS_OFFSET R/W E Tx Bias Offset calibration constant.

166~167 A6~A7 TX_POWER_OFFSET R/W E Tx Power Offset calibration constant.

168~169 A8~A9 RX_POWER_OFFSET (C0) R/W E Rx Power Offset C0 calibration constant.

170 AA Bit7~Bit0 : Reserved ----- E -----

171 AB Bit7~Bit4 : Reserved ----- E -----

1. When APC_EN disable(D4h<2>=0) and

BIAS_LUT_EN disable (D4h<7>=0), the
BIAS_DAC register controls the laser bias current
BIAS_DAC via a 12-bit DAC. Sets the Bias current DAC
171~172 AB~AC ABh Bit3~Bit0 : BIAS_DAC(MSB) R/W E value.
ACh Bit7~Bit0 : BIAS_DAC(LSB) 2. When APC Loop enable (D4h<2>=1), the
transmitter an initial seed value for bias current
that the current value is copied form the register
84h~85h.

173 AD Bit7~Bit2 : Reserved ----- E -----

1. When AUTO_ER disable (D5h<0>=0) and

MOD_LUT disable (D4<6>=0), the MOD_DAC
register controls the modulation current via a
MOD_DAC 10-bit DAC. Sets the modulation current DAC
173~174 AD~AE ADh Bit1~Bit0 : MOD_DAC(MSB) R/W E value.
AEh Bit7~Bit0 : MOD_DAC(LSB) 2. When Auto ER enable (D5h<0>=1), the
transmitter an initial seed value for modulation
current that the current value is copied form the
register 82h~83h
When APC loop enable (D4h<2>=1) and APC_LUT
175 AF APCSET_DAC R/W E
disable (D4h<3>=0)), the value must be set to E0h

The PWE value is compared against the value

176~179 B0~B3 PW1 PASSWORD W E
written to this location to enable PW1 access.

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Address
Function R/W Type NOTES
Dec Hex
The PWE value is compared against the value
180~183 B4~B7 PW2 PASSWORD W E
written to this location to enable PW2 access.

Bit7~Bit4 : TX_SD_ROGUE_TIME Bit7~Bit4 : Threshold Time for the count TX_SD

High (1.64mS~26.88S)
184 B8 R/W E
Bit3~Bit0 : Threshold Time for the count BEN High
Bit3~Bit0 : BEN_ROGUE_TIME
(1.64mS~26.88S)

185 B9 Bit7~Bit0 : Reserved ----- E -----

Set the receiver signal path bandwidth

Bit7~Bit6 : RX_FILTER R/W E
00= 2.5Gbps，01= 1.25Gbps，10/11= 622M/155Mbps

Bit5 : RX SWING ENHANCEMENT R/W E Set to combine with BAh<bit4~3> RX swing X1.5

Set the receiver CML output swing (single end)

Bit4~Bit3 : RX OUTPUT_SWING R/W E 00= 160mV，01= 200mV
186 BA 01= 340mV，11= 420mV

Set LOS detection hysteresis range

Bit2~Bit1 : RX LOS HYSTERSIS R/W E 00= 1.50dB ,01= 1.75dB
10= 2.00dB ,11= 2.50dB

Set to invert RX IN+/- data polarity

Bit0 : RX_DATA_POLARITY R/W E
0=inverse ,1= non-inverse

Bit7~Bit3 : Reserved ----- E -----

Set to squelch RX output when LOS occurs

Bit2 : RX SQUELCH R/W E
0=OFF ,1=ON
187 BB
Set to change the LOS output type
Bit1 : RX LOS TYPE R/W E
0=Open Drain ,1=LVTTL

The polarity of the LOS/SD can be changed from

Bit0 : RX LOS POLARITY R/W E
Loss of Signal (default) to Signal Detect

Set the LOS assert level (LOS DAC out 0~255mV)

188 BC RX LOS_LEVEL R/W E
1LSB=1mV

Enable LUT control of the APD DAC

Bit7 : APD_DAC_LUT_EN R/W E
0=OFF ,1=ON

Bit6 : Reserved ----- E -----

189 BD
Set the TX tuning mode for DCL & SCL
Bit5 : TX Tuning Mode for DCL R/W E
0=OFF ,1=ON

Bit4~Bit0 : Reserved ----- E -----

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Address
Function R/W Type NOTES
Dec Hex

Bit7~4: Reserved ----- E -----

Sets the receiver CML output slew rate.

Bit3 : RX_SLEW R/W E
0=150ps, 1= 90ps

190 BE Sets the receiver signal path bandwidth of 155 M

Bit2:RX INPUT FILTER_155M R/W E
0 = 2.5G/1.25Gbps, 1 = 155Mbps

Sets the GPON power level control:

Bit1~0: GPON POWER LEVEL R/W E
00 = 0dB ,01= -3dB ,11 = -6dB

Sets the LOS output on assertion of RX_SLEEP.

Bit7 : RX LOS_SLEEP_CTRL R/W E 0 = LOS output set HIGH(Default)
1 = LOS output set LOW

Set to enable TSSI function

Bit6 : TX_SD with TSSI function R/W E
0 = OFF , 1 = ON

Assert RX_SLEEP mode

Bit5 : RX_SLEEP_ASSERT R/W E
0 = OFF , 1 = ON

Assert TX_SLEEP mode

Bit4 : TX_SLEEP_ASSERT R/W E
0 = OFF , 1 = ON
191 BF
Set the invert polarity of the RX_SLEEP function
Bit3 : RX_SLEEP_POL R/W E
0= non-inverse ,1=inverse

Set the invert polarity of the TX_DISABLE function

Bit2 : TX_DISABLE_POL R/W E
0= non-inverse ,1=inverse

Set to control RX_SLEEP from the TX_SLEEP

Bit1 : RX_SLEEP_CONTROL R/W E function (Applies to both hard & soft controls)
0=RX ON ,1=RX OFF

Set to use TX_DISABLE pin as TX_SLEEP

Bit0 : TX_SLEEP_MODE R/W E
0=TX ON ,1=TX OFF

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Address
Function R/W Type NOTES
Dec Hex

Selects time power and bias values are latched for

when BEN is de-asserted
Bit7~Bit6 : BEN_TIME_SEL R/W E
00= 5.5ms ~ 8.2ms ,01= 21.8ms ~ 32.8ms
10= 43.7ms ~ 65.5ms ,11= 87.4ms ~ 131.1ms

Set this bit to indicate an error with the last

Bit5 : EE_ACC_ISSUE R/W E
EEPROM update (latched until reset by user)

Set to latch the last valid TX_Bias value during a

Bit4 : TX_BIAS_BEN_LATCH R/W E
BEN de-assert (timing specified by BEN_Time_SEL)
192 C0
Set to report minimum TX power and zero TX bias
Bit3 : TX_POWER_BIAS_ZERO R/W E
on TX_DISABLE

Set to latch the last valid TX power value during a

Bit2 : TX_POWER_BEN_LATCH R/W E
BEN de-assert (timing specified by BEN_Time_SEL)

Write Auxiliary Memory(A0h)

00h: All users can read this area
Bit1~0 : A0_SECURITY_SEL R/W E
01h: Write access for both PW1 and PW2
10h: Write access for PW2 only

Select ADC source to continuously sample

000= TX POWER
001= TX BIAS
010= VCC TX , C1h<3>=0
Bit7~Bit5 : ADC_ADDR R/W E 011= INTERNAL TEMP.
100= RX POWER
101= TX MOD CURRENT
110= VCC RX, C1H<3>=1
111= ADC IN

Enable ADC Channel Check Function from

Bit4 : ADC_SEL R/W E ADC_ADDR C1<7:5> set.
193 C1 0=Disable ,1=Enable

Select which of the VCC monitors is used for DDMI.

Bit3 : VCC_ADC_SEL R/W E
0=TX , 1=RX

Bit2 : EXT_TEMP_SENSOR R/W E Enable external temperature sensor

0 = Result of squared ADC value x slope C2 shifted

Bit1 : RXP_QUAD_SHIFT_SEL R/W E by 29 bits.
1 = Results shifted by 30bits

Bit0 : Reserved ---- E ----

Select value C5h to enable device address in

194 C2 I2C_PASSWORD R/W E I2C_Address (C3h). This new address will be
activated after the next power cycle.

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Sets I2C address pages for the two memory spaces

called A0h and A2h by default. The user can set a
new 6 bit address field for the i7525BN to respond
Bit7~Bit2 : I2C ADDRESS R/W E to. Both A0h and A2h locations are changed
automatically. This is only read and implemented on
power-up. The I2C address does not change
dynamically.

195 C3 Set this bit to disable the i7525BN lower memory

page usually defined at address A0h. This is only
Bit1 : LOW_PAGE_DIS R/W E
read and implemented on power-up. The I2C
address does not change dynamically.

Set this bit to enable a time out function on the I2C

slave interface. If the i7525BN is driving the SDA
Bit0 : I2C_TIMEOUT_EN R/W E
signal low for longer than ~20ms then the i7525BN
I2C interface will reset.

196 C4 Bit7~Bit0 : Reserved ---- E Default value for dual close loop must be setting 11

Bit7~4 : Reserved ---- E ----

Bit3 : Reserved ---- E Set value to 1

Set to enable PON control functions in A2 lower

Bit2 : HOST_PON_EN R/W E
registers: 88h,89h,8Ah,BFh
197 C5
Set to generate a ROGUE_ONU event on TX power
Bit1 : Rogue_TXP_LO_EN R/W E
low alarm assertion

Set to enable clearing of ROGUE_ONU flag by

Bit0 : TX_DIS_ONU_CLR_EN R/W E
toggling of TX_DISABLE function

Bit7~Bit5 : Reserved ---- E ----

Set to disable the transmitter if a

Bit4 : ROGUE_TX_DIS R/W E
ROGUE_ONU_FLAG occurs

Set to assert a TX_FAULT output if a

Bit3 : ROGUE_FAULT R/W E
ROGUE_ONU_FLAG occurs
198 C6
Bit2 : Reserved ---- E ----

Determine what function is enabled at TX_SD output

00/11=Internal TX_SD signal
Bit1~Bit0 : TX_SD_OUT R/W E
01=Rogue ONU TSSI signal
10=TX Shutdown ( DBh<bit7> must be enabled)

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Bit7~Bit3 : Reserved ---- E ----

Bit2 : TABLE00/01 READ LEVEL 0: Read access for PW1 and PW2
R/W E
DEFINE 1: Read access for User, PW1 and PW2
199 C7

Bit1 : EE_TAB3_DIS R/W E Inhibits EEPROM update of Table 3 control setting

Bit0 : EE_UPDATE_DIS R/W E Inhibits EEPROM update of entire memory

0 : Disable internal pull up resistance(10K ohm)

Bit7 : PULL UP RESISTANCE(I2C_S) R/W E
1 : Enable internal pull up resistance(10K ohm)

200 C8 Bit6~Bit3 : Reserved ---- E ----

This byte is automatically loaded into the Table

Bit2~Bit0 : TABLE INITIAL SET R/W E Select byte 7Fh on power up.
011 = Table 03 is selected.

201 C9 Bit7~Bit0 : Reserved ---- E ----

202~203 CA~CB Bit7~Bit0 : TSSI Low time setting R/W E Set to TSSI low time ( 1LSB = 1ms)

204~205 CC~CD Bit7~Bit0 : TSSI High time setting R/W E Set to TSSI high time ( 1LSB = 1ms)

Bit7: 0=Minus, 1=Plus

206 CE Bit7~Bit0 : ER COMPENSATION R/W E
Bit6~Bit0: ER compensation value.

Set the TX_SD threshold level when using laser

forward voltage to trigger the TX_SD monitor

Bit 7~4 : TXSD VF THRESHOLD R/W E 0000=VCC-0.6V, 0100=VCC-1.0V, 0001=VCC-0.7V

0010=VCC-0.8V, 0011=VCC-0.9V, 0101=VCC-1.1V
0110=VCC-1.2V, 0111=VCC-1.3V
Set to adjust modulation output crossing point
0000 = Crossing point at 11%,
0001 = Crossing point at 13%
0010 = Crossing point at 15%
207 CF 0011 = Crossing point at 17%
0100 = Crossing point at 19%
0101 = Crossing point at 21%
0110 = Crossing point at 23%
Bit 3~0 :TX_CROSSING R/W E 0111 = Crossing point at 48%
1000 = Crossing point at 50%
1001 = Crossing point at 51%
1010 = Crossing point at 53.5%
1011 = Crossing point at 56%
1100 = Crossing point at 58.5%
1101 = Crossing point at 61%
1110 = Crossing point at 63.5%
1111 = Crossing point at 65%

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Set value 6Ah to enable transmitter and normal user

208 D0 Bit7~0 : SAFE MODE STARTUP R/W E
mode

Transmitter to be disabled on assertion of RX LOS

Bit7 : TX_DISABLE_ON_RX_LOS R/W E
output

Bit6 : Reserved R/W E Set value to 1

Bit5 : FORCE_BEN_ON R/W E Set to force continuous operation (non-burst)

209 D1 Bit4~Bit3 : Reserved ---- E ----

Bit2 : TX_BURST_POLARITY R/W E Set to invert TX burst polarity

Bit1 : TX_DATA_POLARITY R/W E Set to invert TX data polarity

0= Follow Address CFh<7:4>

Bit0 : TX_SD VF OPTION R/W E
1= VF LUT from the MSB byte of BIAS_LUT

Bit7~6 : Reserved ---- E ----

Set to adjust the value of the passive or active back

termination present at the LASER outputs
111111= R(Ω) = open C(fF)=open
111110= R(Ω) = 117.67 C(fF)=525.986
210 D2
Bit5~Bit0 : BACK_TERM R/W E 111100= R(Ω) = 85.1 C(fF)=525.986
111000= R(Ω) = 66.66 C(fF)=525.986
110000= R(Ω) = 54.79 C(fF)=525.986
100000= R(Ω) = 46.51 C(fF)=525.986
000000= R(Ω) = 40.4 C(fF)= 525.986
Ramp rate used in the APC loop bias current fast
Bit7~0 : Ramp Step Size for APC startup algorithm. Default value for GPON and BOB
211 D3 ---- E
Loop must be setting C0h. the application for SFP must
be setting 03h
Bit7 : BIAS_LUT_EN R/W E Set to enable bias LUT

Bit6 : MOD_LUT_EN R/W E Set to enable modulation LUT

Bit5 : BIAS_LUT_INTERPOL R/W E Set to enable bias LUT interpolation

212 D4 Bit4 : MOD_LUT_INTERPOL R/W E Set to enable modulation LUT interpolation

Bit3 : APC_LUT_EN R/W E Set to enable APC LUT

Bit2 : APC_EN R/W E Set to enable automatic power control

Bit1~Bit0 : Reserved ---- E Set value to 00

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Set the target ER. Form 0000 ~ 1111h,

0000=5 (7.0dB) , 1000=13(11.1dB)
0001=6 (7.8dB) , 1001=14(11.5dB)
0010=7 (8.5dB) , 1010=16(12dB)
Bit7~Bit4 : TARGET_ER_SET R/W E 0011=8 (9.0dB) , 1011=18(12.6dB)
0100=9 (9.5dB) , 1100=20(13dB)
0101=10 (10dB) , 1101=22(13.4dB)
213 D5 0110=11 (10.4dB) ,1110=25(14dB)
0111=12(10.8dB) , 1111=28(14.5dB)

Set full-scale range of MOD DAC

Bit3~Bit2 : MOD_DAC_SETUP R/W E 00: 40mA Linear 01: 90mA Linear
10: 100mA Linear 11: 100mA Pseudo-Logarithmic

Bit1 : Reserved ---- E Set value to 0

Bit0 : AUTO_ER_EN R/W E Set to enable automatic ER control

214 D6 Bit7~Bit0 : Reserved ---- E ----

Sets the maximum allowed monitor photodiode

Bit7~Bit2 : MD_MAX R/W E
current. Setting all 1 to disables this function.

Set to inhibit the BIASMAX function generating a

215 D7 Bit1 : NOFAULT_BIASMAX R/W E
TX_FAULT if the value is exceeded.

Set to inhibit the MODMAX function generating a

Bit0 : NOFAULT_MODMAX R/W E
TX_FAULT if the value is exceeded.

Sets the maximum allowed bias current.

216 D8 Bit7~Bit0 : BIAS_MAX R/W E
Setting FFh disables this function.

Sets the maximum allowed modulation current.

217 D9 Bit7~Bit0 : MOD_MAX R/W E
Setting FFh disables this function.

Set full-scale range and response shape of BIAS

DAC
Bit7~Bit6 : BIAS_DAC_SETUP R/W E
00=28mA Linear, 10=106mA Linear
01=78mA Linear, 11=106mA Pseudo-Logarithmic
218 DA
Bit5~Bit4 : Reserved ---- E ----

Bit3 : APD_DAC_EN R/W E Set to enable APD DAC control.

Bit2~Bit0 : Reserved ---- E ----

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Set this bit to use the TX_SD output as an eye

safety controlled SHUTDOWN output. The
Bit7 : SHUTDOWN_OUTPUT_EN R/W E TXSD_OUT_SEL (C6h<1:0> need to set “10”
When set BFh<bit6>=1 (TSSI function enable)，the
function of this bit is not valid.

Bit6~Bit5 : Reserved ---- E ----

Set the TX_SD threshold when using the MPD input

219 DB to trigger the TX_SD monitor. Setting corresponds to
a proportion of APCSET current
Bit4~Bit2 : TX_SD_MPD_THRESH R/W E
000= 2.5% ,001= 5.0% , 010= 7.5% , 011= 10.0%
100= 12.5% ,101= 15.0% ,110= 17.5% ,111= 20.0%

Set to change the TX_SD monitor trigger from MPD

Bit1 : TX_SD_MODE R/W E
to laser forward voltage

Bit0 : TX_SD_POLARITY R/W E Set to invert the TX_SD output polarity

Bit7 : Report -40db when Rx Losing R/W E Set to RX DDMI report -40 dB if RX LOS Assert

Bit6 :VCC_FAULT_INHIBIT R/W E Set to inhibit VCC fault monitoring

Bit5 : Reserved ---- E ----

Bit4 : SHUTDOWN_INHIBIT R/W E Set the inhibit shutdown of laser current during fault
220 DC
Bit3 : LATCH_INHIBIT R/W E Set the inhibit eye safety latching fault functionality

Bit2 : FAULT_INHIBIT R/W E Set the inhibit eye safety logic functionality

Set to change the TX_FAULT output type for open

Bit1 : TX_FAULT_TYPE R/W E
drain (default) to LVTTL

Bit0 : TX_FAULT_POLARITY R/W E Set to invert the TX_FAULT output pin polarity

Set to turn off the bias current

Bit7 : BIAS_OFF R/W E
0= ON ,1=OFF
Set to turn off the modulation current
Bit6 : MOD_OFF R/W E
0= ON ,1=OFF

Bit5 : WRN_LATCH R/W E Set to enable latching behavior of the warning flags

Bit4 : ALM_LATCH R/W E Set to enable latching behavior of the alarm flags
221 DD
Bit3 : WARN_TEMP_FAULT
Bit2 : WARN_TEMP_DISABLE
Bit3~Bit0 : ALM_WRN_CTRL_1 R/W E Bit1 : ALARM_TEMP_FAULT
Bit0 : ALARM_TEMP_DISABLE
0=Enable 1= Disable

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

Bit7 : WARN_VCC_FAULT
Bit6 : WARN_VCC_DISABLE
Bit5 : ALARM_VCC_FAULT
Bit4 : ALARM_VCC_DISABLE
222 DE ALM_WRN_CTRL_2 R/W E Bit3 : WARN_BIAS_FAULT
Bit2 : WARN_BIAS_DISABLE
Bit1 : ALARM_BIAS_FAULT
Bit0 : ALARM_BIAS_DISABLE
0=Enable 1= Disable

Bit7 : WARN_TXPWR_FAULT
Bit6 : WARN_TXPWR_DISABLE
Bit5 : ALARM_TXPWR_FAULT
Bit4 : ALARM_TXPWR_DISABLE
223 DF ALM_WRN_CTRL_3 R/W E Bit3 : WARN_RXPWR_FAULT
Bit2 : WARN_RXPWR_DISABLE
Bit1 : ALARM_RXPWRS_FAULT
Bit0 : ALARM_RXPWR_DISABLE
0=Enable 1= Disable

Bit7-Bit6 : Reserved ---- E ----

Set de-emphasis value selection

Bit5~Bit4 : SR_DEH R/W E 00 : 0.0dB 01 : 0.8dB (1.7dB)
10 : 1.6dB (3.6dB) 11 : 2.5dB (6dB)
224 E0
Set LPF 3dB value selection.
Bit3 : SR_LP_SETH R/W E
0=10KHz, 1=1KHz

Bit2~Bit0 : Reserved ---- E ----

225 E1 Bit7~Bit0 : Reserved ---- E ----

0: Seed value from Table03

1: Seed value from LUT
Bit7 : The source of Seed value R/W E
Seed Value : BIAS current = ABh~ACh
MOD current = ADh~AEh
226 E2
0= RSSI is sink current
Bit6 : RSSI_SOURCE_SINK R/W E
1= RSSI is source current

Bit5~Bit0 : Reserved ---- E ----

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CH Create i7525BN
Address
Function R/W Type NOTES
Dec Hex

APD sink current select.

Bit7 : APD_SINKCURR_SEL R/W E
0= 512uA, 1= 256uA

APD source current select.

Bit6~Bit4 : APD_SRCNCURR_SEL R/W E 000=256uA, 001=512uA, 010=1024uA
227 E3
011=1536uA, 100=2048uA

0=APD source current

Bit3 : APD_SINK_SRCN_SEL R/W E
1=APD sink current

Bit2~Bit0 : Reserved ---- E ----

Bit7~Bit2 : Reserved ---- E ----

228 E4
Bit1~Bit0 : MD_RES_MSB R/W E MD_RES MSB for APC target power control

229 E5 Bit7~Bit0 : MD_RES_LSB R/W E MD_RES LSB for APC target power control

Bit7~Bit5 : Reserved ---- E ----

0=filter’s bandwidth is 2.5MHz,when use filter

230 E6 Bit4 : FILTER’S BANDWIDTH1 SEL R/W E 2.5Mhz, E7<3:0> must set <0000>
1=OFF

Bit3~Bit0 : Reserved ---- E ----

Bit7~Bit4 : Reserved ---- E ----

0001: filter’s bandwidth=40MHz

0010: filter’s bandwidth=50MHz
231 E7
Bit3 ~Bit0 : FILTER’S BANDWIDTH2 0100: filter’s bandwidth=10MHz
R/W E
SEL
1000: filter’s bandwidth=5MHz
Note: when use filter’s bandwidth 40~5Mhz,
E6<4> must set 1

Bit7 : BEN_STATUS R S Report current status of BEN function

Bit6 : Reserved ---- S ----

Bit5 : TX_SD_PIN R S Report current status of TX_SD pin

232 E8
Bit4~Bit2 : Reserved ---- S ----

Bit1 : DDMI_READY R S 1 to indicate DDMI data ready

Bit0 : EEPROM_PRESENT R S 1 to indicate successful EEPROM communication

233 E9 Bit7~Bit0 : Reserved - S ----

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Address
Function R/W Type NOTES
Dec Hex

234~235 EA~EB ADC_TX_POWER R S Transmitter power (MPD) analogue monitor

236~237 EC~ED ADC_TX_BIAS R S Tx bias current analogue monitor

238~239 EE~EF ADC_VCC_TX R S Transmitter VCC analogue monitor

240~241 F0~F1 ADC_TEMP R S Temperature analogue monitor

242~243 F2~F3 ADC_RX_POWER R S Receiver power (RSSI) analogue monitor

244~245 F4~F5 ADC_MOD R S Tx modulation current analogue monitor

246~247 F6~F7 ADC_VCC_RX R S Receiver VCC analogue monitor

248~249 F8~F9 ADC_IN R S External ADC input analogue monitor

250~255 FA~FF Bit7~Bit0 : Reserved ---- S ----

A2h Table 04h – i7525 ERC / Modulation Look-Up Table

The i7525BN ERC / Modulation Look-Up Table is contained within Table 04h at address A2h,
registers 80h to FFh. This is accessed by writing 04h to the table select byte at address A2h,
register 7F.
Address
Function R/W Type NOTES
Dec Hex

Temperature indexed ER Fine Tune values

ERC LUT ERC LUT=High byte<Bit 7:2>
128~255 80 to FF R/W EEPROM
Modulation DAC LUT Temperature indexed MOD_DAC values
MOD LUT=High byte<Bit 1:0>+Low byte<bit7:0>

The LUT consists of 64 word (16-bit) locations from 80h to FFh covering the temperature range
-40°C to +120°C. The step size for each location is 2.5°C. The temperature step size resolution can
be halved from 2.5°C to 1.25°C by enabling a linear interpolation of the values between two
consecutive look-up table values. If multiple re-writing of this memory area is required then the user
should use an external 8k EEPROM connected to the i7525BN.

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CH Create i7525BN
A2h Table 05h – i7525BN VF Threshold / Bias Look-Up Table
The i752N VF Threshold / Bias Look-Up Table is contained within Table 05h at address A2h,
registers 80h to FFh. This is accessed by writing 05h to the table select byte at address A2h,
register 7Fh.
Address
Function R/W Type NOTES
Dec Dec

Temperature indexed VF threshold values

VF Threshold LUT VF LUT= High byte<Bit 7:4>
128~255 80 to FF R/W EEPROM
Bias DAC LUT Temperature indexed BIAS_DAC values
Bias LUT= High byte<Bit 3:0>+Low byte<bit7:0>

The LUT consists of 64 word (16-bit) locations from 80h to FFh covering the temperature range
-40°C to +120°C. The step size for each location is 2.5°C. The temperature step size resolution can
be halved from 2.5°C to 1.25°C by enabling a linear interpolation of the values between two
consecutive look-up table values. If multiple re-writing of this memory area is required then the user
should use an external 8k EEPROM connected to the i7525BN.

A2h Table 06h – i7525BN APCSET DAC and APD DAC Look-Up Tables
The i7525BN APCSET DAC and APD DAC Look-Up Tables are contained within Table 06h at
address A2h registers 80h to FFh. This is accessed by writing 06h to the table select byte at address
A2h, register 7Fh.
Address
Function R/W Type NOTES
Dec Dec

128~191 80 to BF APCSET LUT bytes PW2 EEPROM Temperature indexed APCSET_DAC values

The APCSET_DAC LUT consists of 64 byte locations from 80h to BFh covering the temperature
range -40°C to +120°C. The step size for each locat ion is 2.5°C.

Address
Function R/W Type NOTES
Dec Hex

192~255 C0 to FF APD_DAC LUT bytes PW2 EEPROM Temperature indexed APD_DAC values

The APD_DAC LUT consists of 64 byte locations from C0 to FFh covering the temperature range
-40°C to +120°C. The step size for each location is 2.5°C.

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CH Create i7525BN
Applications Information
Applications
The following applications circuit diagrams show how the i7525BN can be used in several different
fiber optic transceiver applications.

SFP DDMI Transceiver Module (AC Couple)

VCCR
i7611A
or i7621
0.1uF PIN TIA
ROSA VCCT
0.01uF
VCCR
0.1uF
0.1uF

20 Bead
28
27
26

22
0.1uF 0.1uF
25
24
23
VCCT
ADC_iN
RSSI_IN
APD_DAC
RXINP
VCCR

RXINN
RX_SLEEP

1 21
LOS SD/LOS TX_SD 27 27 TOSA
0.1uF 2 20 Fault
RXOUTN TX_FAULT
RX CML OUTPUT 3 19 0.1uF 12
RXOUTP OUTP
VCCR 0.1uF 4 GND 18
0.1uF VCCD OUTN
5 17 0.1uF 10 VCCT
SDA_S VCCT
TX_DIS/SLEEP

SFP HOST 6 16 47
SCL_S i7525 BIASP
VCCR 7 15
SDA_M BISAN 47
Bead
SCL_M

BENP
BENN
DINN
DINP

MPD

0.1uF
0.1uF 20pF
10
11

13
14
12

8K
9
8

EEPROM
VCCT
100

TX_DISABLE
TX DATA IN

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CH Create i7525BN
GPON Transceiver Module & BOSA on Board (DC Couple)

28
27
26

22
25
24
23
ADC_iN
RSSI_IN
APD_DAC
VCCR

RXINP
RX_SLEEP

RXINN
TX_DIS/SLEEP
SCL_M

BENN
BENP
DINN
DINP

MPD
10
11

13
14
12
9
8

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