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TX

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yvenkataece210463
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10 views1 page

TX

Uploaded by

yvenkataece210463
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module uart_tx (

input wire clk,


input wire reset,
input wire [7:0] data_in, // Data to send
input wire tx_start, // Start transmission
input wire baud_tick, // Baud rate clock
output reg tx, // UART TX line
output reg tx_busy // Transmitter busy flag
);
reg [3:0] bit_idx;
reg [9:0] shift_reg;

always @(posedge clk or posedge reset) begin


if (reset) begin
tx <= 1'b1; // Idle state
tx_busy <= 1'b0;
bit_idx <= 0;
end else if (tx_start && !tx_busy) begin
shift_reg <= {1'b1, data_in, 1'b0}; // Start bit, data, stop bit
tx_busy <= 1'b1;
bit_idx <= 0;
end else if (baud_tick && tx_busy) begin
tx <= shift_reg[0];
shift_reg <= shift_reg >> 1;
bit_idx <= bit_idx + 1;
if (bit_idx == 9) tx_busy <= 1'b0;
end
end
endmodule

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