Verilog DTH - Theory
Uploaded by
khoihchtbVerilog DTH - Theory
Uploaded by
khoihchtbF9 E9 D11 C11 F11 E11 E12 F12
N17 H18 L14 L13
H13 K17 D18 V4
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW0" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "SW1" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "SW2" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "SW3" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
NET "BT0" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BT1" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BT2" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BT3" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
o
module Full_ader( input wire a,b,ci, output wire s,co);
assign s = a^b^ci ;
assign co = ((a^b)&ci) | (a&b) ;
endmodule
o
module Adder_4bits(
input wire [3:0] A,
input wire [3:0] B,
input wire Cin,
output wire Cout,
output wire [3:0] Sum
);
wire c1, c2, c3;
Full_ader add0 (A[0], B[0], Cin ,Sum[0],c1 );
Full_ader add1 (A[1], B[1], c1 ,Sum[1],c2 );
Full_ader add2 (A[2], B[2], c2 ,Sum[2],c3 );
Full_ader add3 (A[3], B[3], c3 ,Sum[3],Cout );
endmodule
module Adder_4bits_test;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
1
// Outputs
wire Cout;
wire [3:0] Sum;
// Instantiate the Unit Under Test (UUT)
Adder_4bits uut (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
);
initial begin
// Initialize Inputs
A = 2;
B = 3;
Cin = 0;
// Wait 100 ns for global reset to finish #100;
// Add stimulus here
end
endmodule
NET "A<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "A<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "A<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "A<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
NET "B<3>" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
NET "B<2>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
NET "B<1>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "B<0]" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
NET "Sum<3>" LOC = "F11"| IOSTANDARD = LVTTL;
NET "Sum<0>" LOC = "F12"| IOSTANDARD = LVTTL;
NET "Sum<1>" LOC = "E12"| IOSTANDARD = LVTTL;
NET "Sum<2>" LOC = "E11"| IOSTANDARD = LVTTL ;
NET "Cin" LOC = "V16"| IOSTANDARD = LVTTL| PULLDOWN;
NET "Cout" LOC = "C11"| IOSTANDARD = LVTTL;
2
o
module Full_ader(
input wire a,b,ci,
output wire s,co
);
assign s = a^b^ci ;
assign co = ((a^b)&ci) | (a&b) ;
endmodule
o
module Adder_3bits(
input wire [2:0] A,
input wire [2:0] B,
input wire Cin,
output wire Cout,
output wire [2:0] Sum
);
wire c1, c2;
Full_ader add0 (A[0], B[0], Cin ,Sum[0],c1 );
Full_ader add1 (A[1], B[1], c1 ,Sum[1],c2 );
Full_ader add3 (A[2], B[2], c2 ,Sum[2],Cout );
endmodule
module Test;
// Inputs
reg [2:0] A;
reg [2:0] B;
reg Cin;
// Outputs
wire Cout;
wire [2:0] Sum;
// Instantiate the Unit Under Test (UUT)
Adder_3bits uut (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
);
initial begin
// Initialize Inputs
Cin=0;
A=3'b000;
B=3'b000;
#100;
3
Cin=0;
A=3'b111;
B=3'b111;
#100;
Cin=0;
A=3'b000;
B=3'b000;
end
endmodule
NET "A<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "A<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "A<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "B<2>" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
NET "B<1>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
NET "B<0>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "Sum<0>" LOC = "F12"| IOSTANDARD = LVTTL;
NET "Sum<1>" LOC = "E12"| IOSTANDARD = LVTTL;
NET "Sum<2>" LOC = "E11"| IOSTANDARD = LVTTL ;
NET "Cin" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
NET "Cout" LOC = "C11"| IOSTANDARD = LVTTL;
4
module SynCounter_4b(
input wire clk, reset,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg;
wire [3:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg;
endmodule
module SynCounter_4b_test;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
SynCounter_4b uut (
.clk(clk),
5
.reset(reset),
.q(q)
);
initial
begin
// Initialize Inputs
clk = 0;
reset = 0;
#100 ;
reset = 1;
#10;
reset = 0;
end
always
begin
#10;
clk=~clk;
end
endmodule
NET "clk" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "q<0>" LOC = "F12"| IOSTANDARD = LVTTL;
NET "q<1>" LOC = "E12"| IOSTANDARD = LVTTL;
NET "q<2>" LOC = "E11"| IOSTANDARD = LVTTL ;
NET "q<3>" LOC = "F11"| IOSTANDARD = LVTTL;
6
module SynCounter_4b(
input wire clk, reset,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg;
wire [3:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg;
endmodule
module button(
input wire reset,clk,btn,
output reg db
);
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3= 3'b011,
one = 3'b100,
wait0_1= 3'b101,
wait0_2 = 3'b110,
wait0_3 = 3'b111;
localparam N = 13;
//signal declaration
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
wire m_tick;
reg [2:0] state_reg, state_next;
// counter to generate 10ms tick
always @(posedge clk)
q_reg <=q_next;
// next state logic
assign q_next = q_reg +1 ;
// output tick
7
assign m_tick = (q_reg==0)?1'b1:1'b0;
//debouncing FSM
//state register
always @(posedge clk, posedge reset)
if(reset)
state_reg <= zero;
else
state_reg <= state_next;
// next state logic and output logic
always @*
begin state_next = state_reg;// default state
db = 1'b0;
case (state_reg)
zero:
if(btn)
state_next = wait1_1;
wait1_1:
if (~btn)
state_next = zero;
else
if (m_tick)
state_next = wait1_2;
wait1_2:
if (~btn)
state_next = zero;
else
if (m_tick)
state_next = wait1_3;
wait1_3:
if (~btn)
state_next = zero;
else
if (m_tick)
state_next = one;
one:
begin
db = 1'b1;
if(~btn)
state_next = wait0_1;
end
wait0_1:
begin
db = 1'b1;
if (btn)
state_next = one;
else
if (m_tick)
state_next = wait0_2;
end
wait0_2:
begin
db = 1'b1;
if (btn)
state_next = one;
else
8
if (m_tick)
state_next = wait0_3;
end
wait0_3:
begin
db = 1'b1;
if(btn)
state_next = one;
else
if (m_tick)
state_next = zero;
end
default: state_next = zero;
endcase
end
endmodule
module FSM(
input wire reset,clk,btn,
output wire [7:0] q
);
wire tick;
button IC1(reset, clk,btn,tick);
SynCounter_4b IC2(tick, reset,q);
endmodule
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "reset" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
NET "btn" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "q<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "q<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
9
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[0];
endmodule
module Test_chiaxung;
// Inputs
reg clk;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
Chiaxung_1hz uut (
.clk(clk),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
end
always
begin
clk = ~clk;
#10;
end
endmodule
10
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "q" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
11
module SynCounter_4b(
input wire clk, reset,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg;
wire [3:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg;
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module Board_1Hz(
input wire clk_50m, reset,
output wire [3:0] led,
output wire clk_1hz
);
wire clk_i;
12
Chiaxung_1hz IC1(clk_50m, clk_i);
SynCounter_4b IC2(clk_i, reset, led);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
module Counter_mod10_ud(
input wire clk, reset, ud,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg;
wire [3:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = (ud==0)?r_reg + 1:r_reg-1;
// output logic
assign q=r_reg;
endmodule
module Test_board_mod10;
// Inputs
reg clk;
reg reset;
13
reg ud;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
Counter_mod10_ud uut (
.clk(clk),
.reset(reset),
.ud(ud),
.q(q)
);
initial begin
clk=0;
reset=1;
ud=0;
#30;
reset=0;
ud=1;
#180;
ud=0;
#180;
ud=1;
#180;
ud=0;
#180;
reset=1;
end
//*************************
always
begin
#10;
clk=~clk;
end
//*************************
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
14
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module Board_1Hz_Mod10(
input wire clk_50m, reset, ud,
output wire [3:0] led,
output wire clk_1hz
);
wire clk_i;
Chia_xung_c2 IC1(clk_50m, clk_i);
Counter_mod10_ud IC2(clk_i, reset, ud, led);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "ud" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
15
module Counter_mod10(
input wire clk, reset,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg=0;
wire [3:0] r_next;
// body, register
always @(posedge clk, negedge reset)
if (!reset)
r_reg <=0;
else
r_reg<=r_next;
// next state logic
assign r_next = (r_reg>8)?0:r_reg+1;
// output logic
assign q=r_reg;
endmodule
module Test_counter_mod10;
// Inputs
reg clk;
16
reg reset;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
Counter_mod10 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial
begin
// Initialize Inputs
clk = 0;
reset = 0;
#20;
reset=1;
end
always
begin
clk = ~clk;
#10;
end
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module COUNTER_MOD10_1HZ(
input wire clk_50m, reset,
output wire clk_1hz,
output wire [3:0] led
);
17
wire clk_i;
Chiaxung_1hz IC1(clk_50m, clk_i);
Counter_mod10 IC2(clk_i, reset, led);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
18
module Counter_mod10(
input wire clk, reset,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg=0;
wire [3:0] r_next;
// body, register
always @(posedge clk, negedge reset)
if (!reset)
r_reg <=0;
else
r_reg<=r_next;
// next state logic
assign r_next = (r_reg<1)?9:r_reg-1;
// output logic
assign q=r_reg;
endmodule
module COUNTER_MOD10(
input wire clk, reset,
output wire [3:0] q,
output wire done
);
// signal declaration
reg [3:0] r_reg1=0;
reg r_reg2=0;
wire [3:0] r_next1;
wire r_next2;
// body, register
always @(posedge clk, negedge reset)
if (!reset)
begin
r_reg1 <=0;
r_reg2 <=0;
end
else
begin
r_reg1<=r_next1;
r_reg2<=r_next2;
19
end
// next state logic
assign r_next1 = (r_reg1>8)?0:r_reg1+1;
assign r_next2 = (r_reg1==8)?1:0;
// output logic
assign q=r_reg1;
assign done=r_reg2;
endmodule
module test;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] q;
wire done;
// Instantiate the Unit Under Test (UUT)
COUNTER_MOD10 uut (
.clk(clk),
.reset(reset),
.q(q),
.done(done)
);
initial begin
clk=0;
reset=0;
#20;
reset=1;
#200;
reset=0;
end
//*************************
always
begin
#10;
clk=~clk;
end
//*************************
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
20
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module Board_1Hz_Mod10_sangso9(
input wire clk_50m, reset,
output wire [3:0] led,
output wire done, clk_1hz
);
wire clk_i;
Chia_xung_c2 IC1(clk_50m, clk_i);
COUNTER_MOD10 IC2(clk_i, reset, led, done);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "done" LOC = "D11"| IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
21
module Counter_mod10_ud(
input wire clk, reset, ud,
output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg=0;
wire [3:0] r_next;
// body, register
always @(posedge clk, negedge reset)
if (!reset)
r_reg <=0;
else
r_reg<=r_next;
// next state logic
assign r_next =(ud==0)?((r_reg<1)?9:r_reg-
1):((r_reg>8)?0:r_reg+1);
// output logic
assign q=r_reg;
endmodule
module Test_board_mod10;
// Inputs
reg clk;
reg reset;
reg ud;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
Counter_mod10_ud uut (
.clk(clk),
.reset(reset),
.ud(ud),
.q(q)
);
initial begin
clk=0;
reset=0;
ud=0;
#30;
reset=1;
22
ud=1;
#180;
ud=0;
#180;
ud=1;
#180;
ud=0;
#180;
reset=0;
end
//*************************
always
begin
#10;
clk=~clk;
end
//*************************
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module Board_1Hz_Mod10(
input wire clk_50m, reset, ud,
output wire [3:0] led,
output wire clk_1hz
);
wire clk_i;
Chia_xung_c2 IC1(clk_50m, clk_i);
Counter_mod10_ud IC2(clk_i, reset, ud, led);
assign clk_1hz = clk_i;
endmodule
23
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "ud" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
24
module Mtt_moore(
input Clock, Resetn, w,
output z,
output reg [1:0] stt
);
reg [2:1] y, Y;
initial
begin
y=0;
Y=0;
end
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the next state combinational circuit
always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = A;
else Y = C;
default: Y = 2'bxx;
endcase
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0)
begin
y <= A;
stt<=A;
end
else
begin
y <= Y;
stt<=Y;
end
25
// Define output
assign z = (y == B);
endmodule
module Board_test;
// Inputs
reg Clock;
reg Resetn;
reg w;
// Outputs
wire z;
wire [1:0] stt;
// Instantiate the Unit Under Test (UUT)
Mtt_moore uut (
.Clock(Clock),
.Resetn(Resetn),
.w(w),
.z(z),
.stt(stt)
);
initial begin
Clock = 0;
Resetn = 0;
w = 0;
#10;
Resetn=1;
w=1;
#40;
w=0;
#20;
w=1;
#20;
end
//***************************
always
begin
#10;
Clock=~Clock;
end
//***************************
endmodule
26
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
module Board_test_1Hz(
input clk_50m, reset, w,
output z, clk_1hz,
output [1:0] stt
);
wire clk_i;
Chiaxung_1hz IC1(clk_50m, clk_i);
Mtt_moore IC2(clk_i, reset, w, z, stt);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "w" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "z" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "stt<0>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "stt<1>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
27
module MTT_moore_mealy
(
input wire clk , reset ,
input wire a , b ,
output wire yl,y0,
output reg [1:0] stt
);
// stt is current state of module//
//symbolic state declaration
localparam [1:0] S0 = 2'b00, S1 = 2'b01 , S2=2'b10;
// signal declaration
reg [1 : 0] state_reg,state_next ;
initial
begin
state_reg<=0;
state_next<=0;
end
// state register
always @ (posedge clk ,posedge reset)
if (reset)
begin
state_reg<=S0;
stt<=S0;
end
else
begin
state_reg<=state_next;
stt<=state_next;
end
//next_state logic
always @*
case (state_reg)
S0: if(a)
if(b)
state_next=S2;
else
state_next=S1;
else
28
state_next=S0;
S1: if(a)
state_next=S1;
else
state_next=S0;
S2: state_next=S0;
default: state_next=S0;
endcase
//Moore outputlogic
assign yl=(state_reg==S0);
//Mealy outputlogic
assign y0=(state_reg==S0)&a&b;
endmodule
module Board_test_bench;
// Inputs
reg clk;
reg reset;
reg a;
reg b;
// Outputs
wire y0;
wire yl;
wire [1:0] stt;
// Instantiate the Unit Under Test (UUT)
MTT_moore_mealy uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.y0(y0),
.yl(yl),
.stt(stt)
);
initial begin
// Initialize Inputs
clk = 0;
//****************************
reset = 1; //current state is S0
a = 1;
b = 1;
#10;
//****************************
reset = 1;
a = 0;
b = 0;
#20;
reset = 0;
a=0;
29
#20;
a=1;
b=1;
#20;
a=1;
b=1;
#20;
a=1;
b=0;
#20;
a=1;
#20;
a=0;
#20;
end
//***************************
always
begin
#10;
clk=~clk;
end
//***************************
endmodule
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk,
output wire q
);
// signal declaration
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
30
module Board_test_1Hz_moore_mealy(
input clk_50m, reset, a, b,
output y1, y0, clk_1hz,
output [1:0] stt
);
wire clk_i;
Chiaxung_1hz IC1(clk_50m, clk_i);
MTT_moore_mealy IC2(clk_i, reset, a, b, y1, y0, stt);
assign clk_1hz = clk_i;
endmodule
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "a" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "b" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk_1hz" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "y1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "y0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "stt<1>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "stt<0>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
31
You might also like
- Rectifier DELTA - Manual Instruction Installation Operation and Troubleshoot WNT DC Power SystemNo ratings yetRectifier DELTA - Manual Instruction Installation Operation and Troubleshoot WNT DC Power System70 pages
- ĐỀ CƯƠNG ÔN TẬP THIẾT KẾ HỆ THỐNG SỐ (1)No ratings yetĐỀ CƯƠNG ÔN TẬP THIẾT KẾ HỆ THỐNG SỐ (1)46 pages
- Bài Thí Nghiệm 2 I. Thí nghiệm 2.1 - Thiết kế bộ cộng hai số 4 bit. 1. Yêu cầu: Thiết kế bộ ALU (Arithmetic and Logic Unit) thực hiện 1. Thiết kế: a) Sơ đồ khối (Block Diagram) - b) VHDL CodeNo ratings yetBài Thí Nghiệm 2 I. Thí nghiệm 2.1 - Thiết kế bộ cộng hai số 4 bit. 1. Yêu cầu: Thiết kế bộ ALU (Arithmetic and Logic Unit) thực hiện 1. Thiết kế: a) Sơ đồ khối (Block Diagram) - b) VHDL Code17 pages
- Essay - Ugoran Prasad For Theatre State by Jompet KuswidanantoNo ratings yetEssay - Ugoran Prasad For Theatre State by Jompet Kuswidananto4 pages
- Vẽ mạch theo sơ đồ nguyên lý như hình vẽNo ratings yetVẽ mạch theo sơ đồ nguyên lý như hình vẽ6 pages
- Dimla Selene S Assignment On Aggregate PlanningNo ratings yetDimla Selene S Assignment On Aggregate Planning3 pages
- Type Hk12 Ks Hook: Non-Standard Sizes or Custom Products Available On RequestNo ratings yetType Hk12 Ks Hook: Non-Standard Sizes or Custom Products Available On Request1 page
- cấu hình chân: #define DDROUT 0 #define DDRIN 1No ratings yetcấu hình chân: #define DDROUT 0 #define DDRIN 18 pages
- An Introduction To Heisenberg Groups in Analysis and GeometryNo ratings yetAn Introduction To Heisenberg Groups in Analysis and Geometry7 pages
- Word Game For Words With Long Vowel SoundNo ratings yetWord Game For Words With Long Vowel Sound3 pages
- Filipino Scientists: GE 07 Science, Technology and SocietyNo ratings yetFilipino Scientists: GE 07 Science, Technology and Society4 pages
- Chuong Trinh Dung AT Mega 8535 Do Nhiet DoNo ratings yetChuong Trinh Dung AT Mega 8535 Do Nhiet Do6 pages
- Induction Type Directional Over Current Relay70% (10)Induction Type Directional Over Current Relay7 pages