Instruction Hazards: Unconditional Branches, Conditional Branches, and Branch

Prediction
Instruction hazards refer to situations where the processor encounters dependencies or
conflicts between instructions that can prevent smooth instruction execution or lead to delays.
These hazards are particularly relevant in pipelines and superscalar processors, where
multiple instructions are being fetched, decoded, and executed simultaneously.
Instruction hazards can be broadly classified into three main types:
1. Data Hazards – Dependencies between instructions due to data being produced or consumed.
2. Control Hazards – Problems arising from branch instructions, which alter the flow of execution.
3. Structural Hazards – Resource conflicts when multiple instructions need the same hardware
resource at the same time.
Since branches are a key source of control hazards, understanding how unconditional and
conditional branches impact instruction flow is important. Branch prediction is a technique
designed to minimize the impact of control hazards by guessing the direction of branches before
the actual condition is evaluated.
Let's explore each aspect in detail:
1. Unconditional Branches
An unconditional branch is a type of instruction that causes the processor to jump to a new
instruction address unconditionally, regardless of any conditions. These types of branches
include:
 Jump instructions (in most ISAs), which unconditionally transfer control to a new address.
 Call instructions in function calls, which push the return address and jump to the called function.
Impact on Instruction Flow:
 When an unconditional branch is encountered, the processor must abandon the current
instruction sequence and fetch the next instruction from the new target address.
 Control hazard: An unconditional branch causes a significant control hazard, as the processor
must stop executing subsequent instructions in the pipeline and load instructions from a new
address. This results in a stall or pipeline flush (where previously fetched instructions must be
discarded).
Solutions:
 Branch target buffer (BTB): A small cache that holds the target addresses of recently
executed jumps, allowing for faster branching.
 Pipeline Flush: After the branch is encountered, previous speculative instructions in the
pipeline may need to be discarded.
2. Conditional Branches
A conditional branch depends on a condition (e.g., whether a value is zero, positive, or
negative). Conditional branches are used in control structures like if statements and loops.
Impact on Instruction Flow:
 Conditional branches introduce control hazards as the processor cannot know the target
address of the next instruction until the branch condition is evaluated (e.g., whether the result of
a comparison is true or false).
 Until the condition is determined, the processor risks fetching the wrong instructions. If the
processor guesses wrong, it has to flush the incorrect instructions from the pipeline, which
results in wasted cycles.
Example:
assembly
Copy code
CMP R0, #0 ; Compare R0 to 0 BEQ target ; Branch if equal ; Other instructions target: ;
Instructions at target
In this case, the BEQ instruction will cause a control hazard that can delay the processor while the
comparison is resolved.
Solutions:
 Pipeline Stalls: Introduce pipeline stalls (delays) until the branch condition is known.
 Branch Delay Slot: Some processors (especially older ones like the MIPS architecture) use a
technique called the branch delay slot, where the instruction immediately following a branch is
always executed, even if the branch is taken. This reduces the penalty of a pipeline flush but
introduces a constraint on how code is written.
3. Branch Prediction
Branch prediction is a technique used to mitigate control hazards by guessing the outcome of a
branch instruction before the branch condition is fully evaluated. The processor continues to
fetch instructions based on this prediction to avoid stalling the pipeline. If the prediction is
correct, performance is maintained; if incorrect, a pipeline flush occurs, but branch prediction
still minimizes the penalty compared to not predicting at all.
Types of Branch Prediction:
1. Static Branch Prediction:
 The processor uses a fixed strategy to predict branches.
 Common strategies:
 Always predict taken: Assume branches will be taken, and fetch the target address.
 Always predict not taken: Assume branches will not be taken, and continue fetching
sequential instructions.
 Static prediction is easy to implement but often suboptimal, especially if the branch behavior is
not uniform.
2. Dynamic Branch Prediction:
 The processor uses runtime information to predict branches, typically by maintaining a history
of branch behavior.
 The most common dynamic branch predictors use the branch history table
(BHT) and pattern history table (PHT) to track branch behavior:
 1-bit predictor: Each branch has a single bit that indicates whether it was recently taken or not.
This is simple but can make incorrect predictions if branches alternate in behavior.
 2-bit predictor: A more sophisticated form, where each branch has two bits to track history,
allowing for better handling of alternating branches.
 Global History Table: Tracks branch behavior globally (across multiple branches) and uses it to
predict future branches.
3. Two-Level Adaptive Predictors:
 Use both global history and local history to make more accurate predictions. These predictors
are based on sophisticated algorithms that track how branches behave not just in isolation, but
as part of the overall flow of the program.
Impact on Performance:
 Accurate Prediction: When the branch predictor is accurate, the processor can keep fetching
instructions without stalling, which is critical for maintaining pipeline throughput.
 Incorrect Prediction: When the prediction is wrong, the pipeline must be flushed and refilled
with the correct instructions, leading to a performance penalty. However, the penalty is usually
smaller than if no prediction were used.
Influence on Instruction Sets: Addressing Modes, Condition Codes, Data Path, and
Control Considerations
The design of an instruction set architecture (ISA) has a profound impact on how a processor
performs computations and interacts with memory. Key elements of an ISA include addressing
modes, condition codes, data path considerations, and control logic. These components
shape the processor’s efficiency, flexibility, and performance.
1. Addressing Modes:
Addressing modes define how the operands for instructions are specified in memory. Different
addressing modes affect the complexity and performance of an instruction set. Common
addressing modes include:
 Immediate Addressing: Operand is part of the instruction itself.
 Register Addressing: Operand is in a register.
 Direct Addressing: Address of the operand is explicitly stated in the instruction.
 Indirect Addressing: Operand’s address is stored in a register or memory location.
 Indexed Addressing: Combines a base address (in a register) with an offset to compute the
effective address.
More flexible addressing modes can lead to more complex instructions, but they allow
for compact code and can reduce the number of instructions needed to perform certain tasks.
2. Condition Codes:
Condition codes are flags that represent the outcome of certain operations
(e.g., zero, negative, carry, overflow). These flags influence branching decisions, allowing
conditional execution to vary based on prior results.
 Example Flags:
 Zero Flag (Z): Set if the result of an operation is zero.
 Carry Flag (C): Set if an arithmetic operation results in a carry out or borrow.
 Overflow Flag (V): Set if an arithmetic operation results in an overflow.
Condition codes are used to make decisions in branching instructions, comparisons, and control
flow. The presence of condition codes enables efficient conditional branching and loops, but they
introduce dependency on previous instructions, which can affect the overall performance,
especially in pipelined processors.
3. Data Path and Control Considerations:
The data path of a processor defines how data flows through the processor during execution. It
includes elements like registers, ALU (Arithmetic Logic Unit), multiplexers, and buses that
connect different functional units.
 Data Path Considerations:
 Efficient instruction execution often depends on how data is transferred between registers and
memory.
 The design of the data path can affect how long it takes to execute an instruction. For example,
a single-cycle design requires that all instructions complete in one clock cycle, while a multi-
cycle design allows different types of instructions to take different amounts of time.
Control considerations define how the processor coordinates the different components of the
data path. Control signals direct data flow between registers, ALUs, memory, and other
functional units. A control unit generates these signals, either through hardwired
logic or microprogramming.
 Control Unit Types:
 Hardwired Control: Faster but less flexible.
 Microprogrammed Control: More flexible but generally slower.
Together, the data path and control unit need to ensure that instructions are executed in the
correct order, operands are correctly fetched and stored, and results are returned to the correct
locations.
Superscalar Operation: Out-of-Order Execution, Execution Completion, Dispatch
Operation
In modern processors, particularly superscalar architectures, several instructions can be
processed in parallel. This leads to higher throughput and better performance, especially for
instruction streams with independent operations.
1. Out-of-Order Execution:
Out-of-order execution (OoOE) refers to the processor's ability to rearrange the execution order
of instructions. This is done to make better use of the processor's resources and avoid idle cycles
when certain operations are delayed (e.g., due to memory latency or waiting for a data
dependency to resolve).
 The instruction scheduler looks ahead at the instruction queue, and instead of waiting for one
instruction to complete, it executes independent instructions that do not depend on the delayed
instruction.
 Data hazards (when an instruction depends on the result of a prior instruction) must be
carefully managed using techniques like register renaming and out-of-order issue.
2. Execution Completion:
 Execution completion refers to the process of retiring instructions that have finished executing.
In a superscalar processor, instructions may complete out of order, but they must be retired in
the correct order to maintain program correctness.
 The processor keeps track of instruction progress through a reorder buffer (ROB) to ensure
that the results are committed in the correct order.
 Instruction retirement is tied to data consistency, as results cannot be committed to memory
or registers until they are sure to be correct.
3. Dispatch Operation:
The dispatch operation in a superscalar processor refers to the process of sending instructions
to the appropriate functional units (e.g., ALU, FPU, memory units). Multiple instructions can be
dispatched simultaneously, depending on the number of execution units in the processor.
 The dispatch unit uses a reservation station to track available execution units and manage
instruction dependencies.
 Instruction issue can happen out of order, but the dispatch unit ensures that each instruction
is sent to the appropriate unit when that unit is free.
RISC & CISC Processors
RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set
Computing) represent two contrasting approaches to processor design.
1. RISC Processors:
RISC processors are characterized by a small, simple instruction set where each instruction
typically takes a single clock cycle to execute. Key characteristics of RISC include:
 Fixed-length instructions: Simpler to decode and pipeline.
 Load/store architecture: Memory access is restricted to load and store instructions, and all
other operations occur between registers.
 Instruction pipelining: Since instructions are simple, they can be pipelined effectively, leading
to better performance.
RISC architectures favor high clock speeds and simpler hardware. They often require more
instructions to perform complex tasks but can still outperform CISC processors due to efficient
pipelining and parallelism.
2. CISC Processors:
CISC processors have a larger, more complex instruction set, with instructions that can
perform multiple operations in a single instruction (e.g., load data, perform an operation, and
store the result in one instruction).
 Variable-length instructions: Some instructions may take more than one cycle to execute,
and this complexity can make pipelining more difficult.
 Addressing modes: CISC processors typically support a variety of addressing modes, which
allow for more flexible memory access.
While CISC processors can reduce the number of instructions needed to perform a task, their
complexity can lead to slower clock speeds and more complicated decoding, limiting their
potential performance in some cases. However, CISC designs tend to have better code density,
requiring fewer instructions to perform a given task.