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Imp Topics Vlsi

The document outlines a comprehensive curriculum on ASIC design, covering topics such as design flow, transistor classifications, MOSFET structures, CMOS technology, scaling models, logic design, and testing methodologies. It includes detailed discussions on various circuit designs, characteristics, and testing techniques relevant to integrated circuits. Each unit emphasizes theoretical concepts, practical applications, and comparisons between different technologies and design strategies.

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Vikramadithya varma Addepalli (22KD1A0403)
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20 views3 pages

Imp Topics Vlsi

The document outlines a comprehensive curriculum on ASIC design, covering topics such as design flow, transistor classifications, MOSFET structures, CMOS technology, scaling models, logic design, and testing methodologies. It includes detailed discussions on various circuit designs, characteristics, and testing techniques relevant to integrated circuits. Each unit emphasizes theoretical concepts, practical applications, and comparisons between different technologies and design strategies.

Uploaded by

Vikramadithya varma Addepalli (22KD1A0403)
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Unit-1

1. Discuss ASIC design flow with neat diagram


2. Explain SSI, MSI, LSI, and VLSI and classify on the basis of transistor count.
3. Discuss the structure of MOSFET, the formation of channel and current conduction in
n-channel MOSFET with neat diagram.
4. Derive IDlinear and IDsat. Explain ID vs VDS curve with different operating conditions
5. Define the requirement of threshold voltage in MOSFET
6. Estimate Pull-up to Pull-down Ratio (Zpu/Zpd) for NMOS inverter driven by another
NMOS inverter & NMOS inverter driven by another NMOS inverter through one or
more pass transistor
7. Derive an equation to demonstrate the trans-conductance in MOSFET.
8. Demonstrate the fabrication of NMOS transistor, PMOS transistor, CMOS inverter
using n-well process with neat diagram
9. Outline the working principle of CMOS inverter with neat diagram.
10. Explain Voltage transfer characteristics (VTC) curve of CMOS inverter
11. Explain the working principle of Bi-CMOS inverter and compare Bi-CMOS
technology with CMOS technology
12. Discuss Latch-up in CMOS circuits and outline the problems associated with Latch-up
13. twin tub
14. cmos & bipolar comparison, advantages etc
15. transconductance,
16. figure of merit
17. alternative pull ups

Unit-2

1. Construct the schematic diagram, stick diagram, and layout diagram of NMOS
inverter, CMOS Inverter, NAND,NOR,XOR, and for Boolean expressions (𝑌 = 𝐴 +
𝐴̅𝐵), (𝑌 = 𝐴𝐶 + 𝐴̅𝐵), (𝑌 = 𝐴 + 𝐵𝐶)
2. Explain the layout design rules associated with Bi-CMOS technology& Construct the
layout diagram of Bi-CMOS inverter
3. Why NMOS transistor is placed in the pull down network?
4. Different forms of pull up network -advantages and disadvantages.
5. stick diagram rules, λ-based layout design rules, different types of µm-based (micro
meter) layout design rules
6. NMOS transistors and design NAND gate, NOR gate
7. 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵 + (𝐶 + 𝐷)(𝐸 + 𝐹 ) + 𝐺𝐻 Using NMOS and CMOS technology.
8. CMOS schematic design style and compare with NMOS design style
9. Difference between lambda based rules and 2 microns and 1.2 micron design rules
10. Explain MOS layers with neat Sketch
Unit-3

1) Significance, advantages of scaling.


2) Develop a scaling model using n-channel MOSFET and show the scaling of all linear
dimensions using different scaling factors.
3) (impact of scaling any four parameters )α and β as scaling factors to estimate scaling
parameters namely
Carrier density in channel,
Gate delay, area, capacitance per unit area,
Operating frequency, maximum operating frequency
Current density,
Switching energy per gate,
Parasitic capacitance,
Channel resistance, length
Saturation current
Power dissipation per gate, per unit area,
Power speed product
4) Types of scaling? Explain each of them briefly.
5) Why scaling is required and write the scaling factors for different types of device
parameters
6) Discuss about scaling MOS circuits and its limitations
7) Explain the limitations on logic levels and supply voltages of MOS Circuits due to
noise
8) Explain the limits of scaling due to
Sub-threshold current,
Interconnects and contact resistances,
Miniaturization,
Depletion width
Power-Speed Product
Switching energy per gate

Unit-4

1) Transmission gate, pass transistor logic- comparisons, advantages, examples


2) Complementary pass transistor logic- AND/NAND, OR/NOR, and XOR/XNOR
3) Mirror adder ?
4) Examine the transistor count of 2:1 multiplexer using pass transistor and transmission
gate & Construct 4:1 multiplexer using 2:1 multiplexer by same logics
5) Compare the CMOS implementation of D-flip-flop with its transmission gate structure.

6) Dynamic CMOS logic, Domino CMOS logic-advantages, disadvantages


7) Construct using dynamic CMOS logic. 𝑌 = 𝐴𝐵 + 𝐴̅𝐶̅ + 𝐴𝐵̅𝐶
8) Compare different types of programmable logic devices with suitable example.
9) Design 𝑌 = 𝐴 + 𝐴̅𝐵 using minimum number of transistors with the help of psedo
NMOS logic.
10) Write in short about properties and architectures of PAL,PLA,CPLD,FPGA
Unit-5
1) Outline the need of testing in IC technology.
2) What are different types of physical defects exhibit in ICs? Outline various problems
associated due to physical defects.
3) Explain different types of electrical and logical faults.
4) What is automatic test pattern generator (ATPG)?
5) How testing of combinational logic circuits is performed using sensitized path based
testing with an example?
6) Explain testing of sequential circuits with effect of memory with a suitable example.
7) Explain LFSR and its use in testing of ICs.
8) Explain the key concepts associated with design for testability.
9) Give a logic circuit example in which either stuck-at-1 fault or stuck-at-0 fault are
indistinguishable.
10) Explain different levels of abstraction of testing.
11) Explain scan architecture in detail.
12) Explain built-in-self test (BIST) in detail. boundary scan testing-advantages,
disadvantages
13) Fault simulation methods and its explanation
14) Signature analyzer in BIST circuits
15) Different DFT techniques
16) Fault models in IC
17) Full scan based for testing combinational circuits

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