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Hard Memories

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Youness Rabah
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24 views14 pages

Hard Memories

Uploaded by

Youness Rabah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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iCE40 embedded Block RAM

❑ Read-before-write (le cas de ice40 fpga)


§ r_data contient l’ancienne valeur qui se trouve dans la
mémoire;
§ un élément mémoire sera écrasé par la valeur de
w_data;

❑ Write-before-read (Autres fpgas)


§ r_data contient la même donnée que w_data ;
§ un élément mémoire sera écrasé par la valeur de
w_data;
iCE40 Embedded Block RAM (4Kb x 32)

ENSAM Casa – Département GE – BABA 2 modifié le 18 Sep. 2024


iCE40 Embedded BRAM – Exemple 1 – 8 x 16
module memory ( input clk, w_en, r_en,
input [3:0] w_addr, r_addr,
input [7:0] w_data,
output reg [7:0] r_data );

reg [7:0] mem [0: 4’hf];


always @(posedge clk) begin
if (w_en)
mem[w_addr] <= w_data;
if (r_en)
r_data <= mem[r_addr];
end

endmodule // memory
ENSAM Casa – Département GE – BABA 3 modifié le 18 Sep. 2024
iCE40 EBRAM – Exemple 1 – Testbench
`timescale 1ns/10ps // 1ns unit & precision 10ps
module memory_tb();
wire [7:0] r_data;
reg clk=0;
reg w_en=0;
reg r_en=0;
reg [3:0] w_addr;
reg [3:0] r_addr;
reg [7:0] w_data;
localparam DURATION = 10000;
always begin
#41.67
clk = ~clk;
end
ENSAM Casa – Département GE – BABA 4 modifié le 18 Sep. 2024
iCE40 EBRAM – Exemple 1 – Testbench
memory uut(.clk(clk), .w_en(w_en), .r_en(r_en),
.w_addr(w_addr), .r_addr(r_addr), .w_data(w_data),
.r_data(r_data) );

initial begin
// test 1: read from address 0x0f (should be garbage)
#(2*41.67)
r_addr = 'h0f;
r_en = 1;
#(2*41.67)
r_addr = 0;
r_en = 0;
// test 2: write to address 0x0f and read it back
#(2*41.67)
ENSAM Casa – Département GE – BABA 5 modifié le 18 Sep. 2024
iCE40 EBRAM – Exemple 1 – Testbench
w_addr = 'h0f;
w_data = 'hA5;
w_en = 1;
#(2*41.67)
w_addr = 0;
w_data = 0;
w_en = 0;
#(2*41.67)
r_addr = 'h0f;
r_en = 1;
#(2*41.67)
r_addr = 0;
r_en = 0;
end // initial begin
ENSAM Casa – Département GE – BABA 6 modifié le 18 Sep. 2024
iCE40 EBRAM – Exemple 1 – Testbench
// run simulation
initial begin
// create simulation output file
$dumpfile("memory_tb.vcd");
$dumpvars(0, memory_tb);
// wait for a given amount of time for simulation to complete
#(DURATION)
// notify and end simulation
$display(" Finished ");
$finish;
end // initial begin
endmodule // memory_tb

$: apio sim #gtkwave doit être préinstallé

ENSAM Casa – Département GE – BABA 7 modifié le 18 Sep. 2024


iCE40 EBRAM – Exemple 1 – Résultats
$: yosys -p "synth_ice40 -top memory -json chip.json" memory.v
2.48. Printing statistics.

=== memory ===

Number of wires: 30
Number of wire bits: 92
Number of public wires: 30
Number of public wire bits: 92
Number of ports: 7
Number of port bits: 27
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 36
SB_DFF 13
SB_DFFE 9
SB_LUT4 13
SB_RAM40_4K 1

ENSAM Casa – Département GE – BABA 8 modifié le 18 Sep. 2024


iCE40 SRAM 1Mb

ENSAM Casa – Département GE – BABA 9 modifié le 18 Sep. 2024


iCE40 SPRAM – Exemple – SB_SPRAM256KA
module spram (input user1, clki, output [2:0] rgb, usb);

assign usb = 3'd0;


SB_GB clkgb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
.GLOBAL_BUFFER_OUTPUT(clk));
SB_WARMBOOT boot1(.BOOT(~user1),.S1(1'b0), .S0(1'b0));

reg [7:0] state;


reg [31:0] counter;
parameter DEPTH=16384;// fixed depth: 16K
parameter ADDRW=$clog2(DEPTH) - 1;
reg [2:0] led;
parameter IDLE=0,RUN=5,
INIT0=1,INIT1=2,INIT2=3,INIT3=4;
ENSAM Casa – Département GE – BABA 10 modifié le 18 Sep. 2024
iCE40 SPRAM – Exemple – SB_SPRAM256KA
//access to spram
reg [ADDRW:0] ram_addr;
reg [15:0] ram_data_in;
wire [15:0] ram_data_out;
reg ram_wren;

SB_SPRAM256KA spram (
.ADDRESS(addr),.DATAIN(data_in),
.MASKWREN({wren, wren, wren, wren}),
.WREN(wren),
.CHIPSELECT(1'b1),
.CLOCK(clk),
.STANDBY(1'b0), .SLEEP(1'b0), .POWEROFF(1'b1),
.DATAOUT(ram_data_out));
ENSAM Casa – Département GE – BABA 11 modifié le 18 Sep. 2024
iCE40 SPRAM – Exemple – SB_SPRAM256KA
SB_RGBA_DRV rgb (
.CURREN(1'b1),
.RGBLEDEN(1'b1),
.RGB0PWM(~led[1]), // Green
.RGB1PWM(~led[0]), // Red
.RGB2PWM(~led[2]), // Blue
.RGB0(rgb[0]), .RGB1(rgb[1]), .RGB2(rgb[2])
);

defparam rgb.CURRENT_MODE = "0b1"; //half_current


defparam rgb.RGB0_CURRENT = "0b000001";// Green @2mA
defparam rgb.RGB1_CURRENT = "0b000001";// Red @2mA
defparam rgb.RGB2_CURRENT = "0b000001";// Breen @2mA

ENSAM Casa – Département GE – BABA 12 modifié le 18 Sep. 2024


iCE40 SPRAM – Exemple – SB_SPRAM256KA
always @(posedge clk) begin INIT3: begin
wren <= 1'b0; addr <= 16'b11;
case(state) data_in <= 16'b111;//White
IDLE: begin end wren <= 1'b1;
INIT0: begin state <= RUN;end
addr <= 16'b00; RUN: begin
data_in <= 16'b001;//Red counter <= counter + 1;
wren <= 1'b1;
state <= INIT1;end //incr. addr every ~sec at 12Mhz
INIT1: begin if(counter == 32'h1000000) begin
addr <= 16'b01; addr[1:0]<=addr[1:0]+1; end
data_in <= 16'b010;//Green //wait 2cycle to have data
wren <= 1'b1; if(counter == 32'h1000002) begin
state <= INIT2; end led <= data_out[2:0];
INIT2: begin counter <= 0; end
addr <= 16'b10; end
data_in <= 16'b100;//Blue endcase
wren <= 1'b1; end
state <= INIT3; end endmodule

ENSAM Casa – Département GE – BABA 13 modifié le 18 Sep. 2024


iCE40 SPRAM – Exemple – Résultats
$: iverilog -B "ice40/ivl" -o x.out -D VCD_OUTPUT= ice40/cells_sim.v spram.v
$: yosys -p "synth_ice40 -top fpga_top -json x.json" spram.v
$: nextpnr-ice40 -r --up5k --package uwg30 --json x.json --asc x.asc --pcf fomu.pcf
Info: Device utilisation:
Info: ICESTORM_LC: 74/ 5280 1%
Info: ICESTORM_RAM: 0/ 30 0%
Info: SB_IO: 6/ 96 6%
Info: SB_GB: 3/ 8 37%
Info: ICESTORM_PLL: 0/ 1 0%
Info: SB_WARMBOOT: 1/ 1 100%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: SB_RGBA_DRV: 1/ 1 100%
Info: ICESTORM_SPRAM: 1/ 4 25%

ENSAM Casa – Département GE – BABA 14 modifié le 18 Sep. 2024

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