QB Coa
QB Coa
Badnera - Amravati
Computer Science & Engineering
Data Science
5KS03 & 5KD03 -Computer Architecture and Organization
UNIT 1:
Q1. Write a note on various functional units of computer with diagram
Q2. What is bus? Explain the single bus structure used in computer organization.
Q3. Explain big endian and little endian, with suitable data structure examples
Q4. What is addressing modes? Explain different addressing modes with example
Q6. Illustrate the connection between processor and memory with the help of typical operating
steps.
Q7. Describe the steps needed to execute following instruction ADD LOC A,R0
UNIT II
Q1. Illustrate the connection between processor and memory with the help of typical operating
steps.
Q2. With a block diagram explain the internal organization of dynamic memory chip.
Q3. Draw CMOS memory cell and explain the operation of dynamic memory
Q5. Explain the organization of 2m*32 memory module using 512k*8 static memory chip.
Q8. Describe the term memory hierarchy with neat and labelled diagram
Q11. What is cache memory? With help of block diagram explain direct mapping function in
cache
UNIT III
Q1. Explain the working of single bus organization of the data paths inside the CPU with neat
diagram.
Q2. Draw and explain the register transfer mechanism of single bus organization
Q3. Explain the sequence of operations needed to perform the following CPU functions
a. Fetching a word from computer.
b. Storing a word into memory.
c. Performing arithmetic and logical operations.
Q4. Explain timing diagram of read operation.
Q5. Explain the execution of a complete instruction.
Q6. Draw and explain three bus organization.
Q7. Explain hardwired control unit with neat, labeled diagram.
Q8. Draw and explain the block diagram of a complete processor.
Q9. Explain microprogrammed control unit with help of neat diagrams.
Q10. What is micro-instruction? Explain vertical and horizontal organization.
Q11. Explain micro-program sequencing in detail.
Q12. Explain wide branch addressing in detail.
UNIT IV
Q1. Explain the I/O interface for an input devices with diagram.
Q2. Explain programmed I/O and interrupt driven I/O with advantages and disadvantages.
Q3. Explain program-controlled I/O.
Q4. What is interrupt? Explain various types of interrupts.
Q5. Explain in brief “interrupt-service routine.
Q6. What is the need for enabling and disabling interrupts.
Q7. Explain techniques to handle multiple devices.
Q8. What is interrupt? Explain interrupt nesting and vectored interrupt with help of neat
diagram.
Q9. Explain various technique to handle simultaneous interrupts request.
Q10. What do you mean by exceptions in instructions execution.
Q11. What is DMA? Explain in detail two channel DMA controller and bus arbitration in DMA.
Q12. What is bus arbitration? Explain different arbitration techniques.
UNIT V
Q1. Design fast adder using n-bit ripple carry adder.
Q2. Draw and explain n-bit ripple carry look ahead adder.
Q3. Draw and explain binary addition subtraction logic unit.
Q4. Describe fast addition with the help of carry lookahead adder.
Q5. Draw and explain 4-bit ripple carry adder.
Q6. Draw and explain 4-bit carry look ahead adder.
Q7. Explain binary multiplication with sequential circuit binary multiplier.
Q8. What is the need of booths algorithm? Describe the booths algorithm for multiplication of
two numbers with suitable example.
Q9. Explain booth algorithm and its advantage and perform booths multiplication for
A(multiplicand)→(+13),B(multiplier)→(-6)
Q10. Explain binary division with restoring division method.
Q11. Differentiate between ripple carry adder and carry look ahead adder in detail.
Q12. Find the following representation of below number in 10 bits
A) sign magnititude B)1’s compliment C)2’s compliment
Numbers :1)27, 2)-64 , 3)-32, 4)49
UNIT VI
Q1. Explain taxonomy of parallel processor architecture.
Q2. Differentiate SIMD and MIMD
Q3. Explain characteristic and advantage of symmetric multiprocessor’s (SMP).
Q4. What are some of the potential advantages of an SMP compared with unipolar.
Q5. List and explain designed consideration required for multiprocessor system.
Q6. What is cache coherence problem? Discuss the software and hardware approach for cache
coherence.
Q7. What is the meaning of each of the four states in the MESI protocol?
Q8. Explain different approaches of multithreading.
Q9. Explain four general organization for multicore systems.
Q10. What is the basic idea used in pipelining. Explain with example and neat diagram.
Q11. What are pipeline hazards explain data hazards, control hazards and structural hazards in
brief.
Q12. Explain PCI bus, SCSI bus and USB bus in detail.