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Vlsi d2

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15 views7 pages

Vlsi d2

Uploaded by

nivaspenta910
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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NAME: VUTUKOORI SAI PRANATHI DATE:

ROLL NO: 20EG104259 PAGE NO:

EXPERIMENT-2
DESIGN OF FULL ADDER USING 3 MODELING STYLES.
Aim: To realize a full adder using Xilinx vivado with Verilog HDL for 3 modeling styles.
Tools Required:
Software: ISE Xilinx vivado
Hardware: Personal Computer

Theory:
A Full adder is a digital circuit that performs addition. Full adders are implemented with logic
gates in hardware .A full adder adds three one-bit binary numbers,two operands and a carry
bit.The adder outputs two numbers ,a sum and a carry bit .The term is contrasted with a half
adder,which adds two binary digits
Full adder: Sum S=a^b^c;
Carry C_out=(a&b)|(b&c)|(a&c);

Source Code:Full Adder

1.Data flow Model:


module fulladder(
input a,
input b,
input c,
output s,
output c_out
);
assign s=a^b^c;
assign c_out=(a&b)|(b&c)|(a&c);
endmodule

Test Bench:
module fulladder_tb();
reg a,b,c;
wire s,c_out;
fulladder uut(a,b,c,s,c_out);
initial begin
a=0;b=0;c=0;#100
a=0;b=0;c=1;#100;
a=0;b=1;c=0;#100;
a=0;b=1;c=1;#100;
a=1;b=0;c=0;#100;
a=1;b=0;c=1;#100;
a=1;b=1;c=0;#100;

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

a=1;b=1;c=1;#100;
end
endmodule

2.Gate level Model:


module fulladder12(
input a,
input b,
input c,
output sum,
output cout,
wire p,
wire q,
wire r );
xor u1(p,a,b);
xor u2(sum,p,c);
and u3(q,p,c);
and u4(r,a,b);
or u5(cout,r,q);
endmodule

Test Bench :

module fulladder12_tb();
reg a,b,c;
wire sum,cout;
fulladder12 uut(.a(a),.b(b),.c(c),.sum(sum),.cout(cout));
initial begin
a=0;b=0;c=0;#100;
a=0;b=0;c=1;#100;
a=0;b=1;c=0;#100;
a=0;b=1;c=1;#100;
a=1;b=0;c=0;#100;
a=1;b=0;c=1;#100;
a=1;b=1;c=0;#100;
a=1;b=1;c=1;#100;
end
endmodule

3.Behavioral Model:

module full(A,B,Cin,S,Cout);
input wire A, B, Cin;
output reg S, Cout;
always @(A or B or Cin)
begin
if(A==0 && B==0 && Cin==0)
begin
S=0;

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

Cout=0;
end
else if(A==0 && B==0 && Cin==1)
begin
S=1;
Cout=0;
end
else if(A==0 && B==1 && Cin==0)
begin
S=1;
Cout=0;
end
else if(A==0 && B==1 && Cin==1)
begin
S=0;
Cout=1;
end
else if(A==1 && B==0 && Cin==0)
begin
S=1;
Cout=0;
end
else if(A==1 && B==0 && Cin==1)
begin
S=0;
Cout=1;
end
else if(A==1 && B==1 && Cin==0)
begin
S=0;
Cout=1;
end
else if(A==1 && B==1 && Cin==1)
begin
S=1;
Cout=1;
end
end
endmodule

Test Bench:
module full_tb();
reg A, B, Cin;
wire S, Cout;
full uut(A,B,Cin,S,Cout);
initial begin
A=0;B=0;Cin=0;#100;
A=0;B=0;Cin=1;#100;
A=0;B=1;Cin=0;#100;
A=0;B=1;Cin=1;#100;

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

A=1;B=0;Cin=0;#100;
A=1;B=0;Cin=1;#100;
A=1;B=1;Cin=0;#100;
A=1;B=1;Cin=1;
end
endmodule

Procedure:
1. Open Xilinx Vivado software tool and click on new project.
2. Select Verilog HDL language and proceed to next.
3. Create the file same name as filename.
4. Select Zedboard. A file will be selected write the code and save the file.
5. Select the Constraints inputs and outputs used for design.
6. A file will be created,then write the code and save the code.
7. Check for errors, if any correct them.
8. Now add a source file for writing test bench code.
9. Write Test bench code and obtained RTL schematic &run simulation.
10. Now run behavioral simulation for output waveform.

Applications:
1. A Full Adder’s circuit can be used as a part of many other larger circuits like Ripple
Carry Adder, which adds n-bits simultaneously.
2. Full Adders are used in ALU- Arithmetic Logic Unit.
3. The dedicated multiplication circuit uses Full Adder's circuit to perform Carryout
Multiplication.

Result:
Realized a full adder using Xilinx vivado with Verilog HDL for 3 modeling styles.

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

Output:
1.Data flow Model:
RTL Schematic

Simulation waveform

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

2.Gate level Model:

RTL Schematic

Simulation waveform

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT


NAME: VUTUKOORI SAI PRANATHI DATE:
ROLL NO: 20EG104259 PAGE NO:

3.Behavioral Model:
RTL Schematic

Simulation waveform

ANURAG UNIVERSITY VLSI DESIGN LAB ECE DEPARTMENT

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