Interrupts (1)

Lecture 9

Yeongpil Cho

Hanynag University
Topics
• Interrupt Handling Basics
• Priority Management

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Interrupt Handling Basics

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Interrupts
• Motivation
▪ Inform processors of some
external events timely

• Polling:
▪ You pick up the phone every
three seconds to check
whether you are getting a call.
• Interrupt:
▪ Do whatever you should do
and pick up the phone when
it rings.

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ARMv7-M Interrupt Handling
• One Non-Maskable Interrupt (NMI) supported
• Up to 511 (496 external and 15 internal ones)
prioritizable interrupts/exceptions supported
▪ Interrupts can be masked
▪ Implementation option selects number of interrupts supported
• Nested Vectored Interrupt Controller (NVIC) is tightly co
upled with processor core

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Interrupt Service Routine Vector Table
Address
• First entry contains initial Main SP 0x40 + 4*N External N
… …
• All other entries are addresses for 0x40 External 0
▪ exception/interrupt handlers 0x3C SysTick
▪ Must always have LSBit = 1 0x38 PendSV
(for Thumb) 0x34 Reserved
• Table can be relocated 0x30 Debug Monitor
▪ Use Vector Table Offset Register 0x2C SVC
0x1C to 0x28 Reserved (x4)
▪ Still require minimal table entries at
0x18 Usage Fault
0x0 for booting the core
0x14 Bus Fault
• Table can be generated using C 0x10 Mem Manage Fault
code 0x0C Hard Fault
0x08 NMI
0x04 Reset
0x00 Initial Main SP
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Interrupt Service Routine Vector Table
of Cortex-M processors

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Interrupt Handling Process

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Stacking & Unstacking
• Current mode (either Thread mode or Handler mode)’s
stack is used for stacking/unstacking.
Old SP SP + 0x20 xxxxxxxx
SP + 0x1C xPSR
• Stacking: The processor
SP + 0x18 PC (r15)
automatically pushes these eight
SP + 0x14 LR (r14) registers into the stack before an
Full
Descending SP + 0x10 r12 interrupt handler starts
Stack SP + 0x0C r3
• Unstacking: The processor
SP + 0x08 r2 automatically pops these eight
SP + 0x04 r1 register out of the stack when an
interrupt hander exits.
New SP SP + 0x00 r0

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Stacking & Unstacking

Interrupt
Exit
Interrupt Handler
Interrupt
Unstacking
Signal

User Program User Program

Stacking
Time
Thread Mode Handler Mode Thread Mode

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Stacking & Unstacking
Interrupt Interrupt
Signal Exit

Handler Program Interrupt Handler Handler Program

Stacking Unstacking

Time
Handler Mode Handler Mode Handler Mode

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Exception Exits
• When the EXC_RETURN is loaded into the PC at the end of the
exception handler execution, the processor performs an exception
return sequence
• EXC_RETURN is generated and set to LR by processors when an
exception arises.
• There are three ways to trigger the interrupt return sequence:

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Registers
• Handler mode and Thread mode
▪ Handler mode always use MSP
▪ Thread Mode uses either PSP or MSP
– Control[1] = 0, SP = MSP (default)
– Control[1] = 1, SP = PSP

MSP: Main Stack Pointer

PSP: Process Stack Pointer
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Which stack to use
when exiting an interrupt?
• EXC_RETURN indicates processor mode and stack type to be
activated when exiting an interrupt
• EXC_RETURN is generated dynamically according to
processor mode and stack type on that point
No FP extension:
EXC_RETURN Return Mode Return Stack
0xFFFFFFF1 Handler SP = MSP
0xFFFFFFF9 Thread SP = MSP
0xFFFFFFFD Thread SP = PSP
With FP extension:
EXC_RETURN Return Mode Return Stack
0xFFFFFFE1 Handler SP = MSP
0xFFFFFFE9 Thread SP = MSP
0xFFFFFFED Thread SP = PSP 14
Register values in
an interrupt
service routine

An interrupt
from the
user-mode
with the MSP
LR = 0xFFFFFFF9

SP = MSP

ISRs always
run on the
Handler mode
with the MSP

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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Interrupt: Stacking & Unstacking

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 Interrupt Number in PSR
• Valid exception numbers on ARMv7-M
▪ 1 to 511

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N Z C V Q IT[7:6] T Reserved GE[3:0] IT[5:0] 0 or Exception Number

IT[7:0]: If-Then bits

Thumb state flag GE[3:0]: Greater or equal flags (only available on Cortex-M4 and M7)

Stick saturation flag for SSAT and USAT

Overflow flag

Carry/Borrow flag

Zero flag

Negative or less than flag

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Enable an Interrupt/Exception
• Enable a system exception
▪ Some are always enabled (cannot be disabled)
▪ No centralized registers for enabling/disabling
▪ Each is controlled by its corresponding components, such as
SysTick module

• Enable a peripheral interrupt

▪ Centralized register arrays for enabling/disabling
▪ NVIC’s ISER 0~15 registers for enabling
– Interrupt Set Enable Register
▪ NVIC’s ICER 0~15 registers for disabling
– Interrupt Clear Enable Register

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Enabling Peripheral Interrupts

TIM7_IRQn = 44
NVIC->ISER[1] = 1 << 12; // Enable Timer 7 interrupt

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Disabling Peripheral Interrupts

TIM7_IRQn = 44
NVIC->ICER[1] = 1 << 12; // Diable Timer 7 interrupt
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Priority Management

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Interrupt/Exception Priority
• Inverse Relationship:
▪ Lower priority value means higher urgency.
– Priority of Interrupt A = 5,
– Priority of Interrupt B = 2,
– B has a higher priority/urgency than A.

• Fixed priority for Reset, HardFault, and NMI.

Exception IRQn Priority

Reset N/A -3 (the highest)
Non-maskable Interrupt (NMI) 14 -2 (2nd highest)
Hard Fault 13 -1

• Adjustable for all the other interrupts and exceptions

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Peripheral Interrupt Priority
• Interrupt priority is configured by Interrupt Priority
Register (IPR) 0~123
▪ 124 IPRs * 4 priority configuration per IPR = 496
(= Total # of peripheral interrupts supported on ARMv7-M)
• Each priority consists of two fields, including preempt
priority number and sub-priority number.
▪ Available bits in a priority byte are device-implementation defined.
▪ The preempt priority number defines the priority for preemption.
▪ The sub-priority number determines the order when multiple
interrupts are pending with the same preempt priority number.

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 Peripheral Interrupt Priority
• The lengths of the Preemption Priority-field and the Sub-
priority Number-field are configurable within valid priority bits.
▪ The position of LSB is adjusted.
• Why adjusting LSB?
▪ Easier porting!
▪ Programs implemented on many-bit priority-level device can run on
small-bit priority level device without inversion of priority.
▪ example: 2/5 bits priority fields → 2/3 bits priority fields
Adjusting LSB Adjusting MSB
0b10100010 0b01000110
PP: 2 → 2 PP: 2 → 2
SPN: 17 → 4 SPN: 17 → 1
0b10100010 0b01000110
priority reversal!
0b10001010 0b00010110
PP: 2 → 2 PP: 2 → 2
SPN: 5 → 1 SPN: 5 → 5 default setting
0b10001010 0b00010110
System Interrupt Priority
• 3 SHPRs (System Handler Priority Register) determine
priorities of system exceptions and interrupts,

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Exception-masking registers
• PRIMASK: Set current execution priority to 0
▪ All interrupts are disabled except for NMI, hard fault, and reset
MOV R0, #1
MSR PRIMASK, R0

• FAULTMASK: Set current execution priority to -1

▪ All interrupts are disabled except for NMI and reset
• BASEPRI: Disable all interrupts of the same or lower
priority level
▪ Example
– disabling interrupts whose priority levels are equal to or lower
than 0x60
MOV R0, #0x60
MSR BASEPRI, R0

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