Computer

Engineering
2DX4
Event Based Programming &
Interrupts

Week 7

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Course Organization

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 o Event vs. Procedural: Interrupt vs Polling
• Interrupt Concept
• ARM Cortex-M4 Nested Vectored Interrupt
Controller (NVIC)
• Triggering Interrupts
Lecture Objectives
o Inputs
o SysTick

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 Event vs.
Procedural:
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Make sure to include an image description by rightInterrupt vs
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Polling

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 Recall: Embedded Program Structure

• Embedded programming can be approached with a

common set of steps, regardless of application.
• Example items that would be configured for the uC
environment:
o Bus clock
o Interrupts enabled/disabled
o Enable major peripherals (ADC, DAC, SCI, etc.)

This is a procedural programming

paradigm that requires the
programmer to poll I/O resources.

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 Embedded Program Structure

• Example items that would be performed in the body of

the program:
o Output values to physical pins (e.g., LEDs, LCD
interface)
o Input values from physical pins (e.g., keypad,
switches)

Is this a polling
method or interrupt
driven? How do I tell?

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 Embedded Program Structure

• Since we have a loop, this simple program implements

polling.
• Polling means looping based upon a value we keep
checking (e.g., was a button pressed?).
• A polling method does not exclude the use of interrupts.

So if polling and interrupts

are not mutually exclusive –
how do I know?

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 Embedded Program Structure
• An interrupt driven program typically has a very different
structure.
• Often the main body of the program seems to be
missing. However, by looking at the environment set up
we can determine that interrupts have been enabled.
• All logic has been implemented as event driven and so it
is common to have an infinite loop when the processor is
waiting for an event (or even better to be in a low power
“wait” state).
• When an interrupt occurs, it is handled by an Interrupt
Service Routine (ISR). This will look like a function, but
An ISR looks
is invoked by interrupt, instead of the programmer like a function.
explicitly calling the function.
This is an event-based
programming paradigm that
allows the programmer to service
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What is an interrupt?

• A special event that requires the CPU to stop normal program execution and perform some service related to
the event.
• Examples of interrupts include I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0,
etc.

Classroom analogy:

Polling – Instructor asks each student if they understand a concept, then

teaches next concept.

Interrupt – Instructor continues to teach and student raises hand when they
need attention

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What’s Wrong With Procedural/Polling?

• Nothing is “wrong” with procedural programming or polling. However, it can present a challenge when timing
is critical in the embedded application.
• For example, when using ADC you must meet Nyquist restrictions.
o Polling can introduce I/O time delays that are variable, causing failed synchronization.
o Interrupts can be prioritized to ensure timing is met.
• Generally I/O is slower than software

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 Click the picture icon to insert a background picture.
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clicking on your image and selecting ‘Edit Alt Text…’
Concept
For an embedded system

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Interrupts
Technical description

• An interrupt is the automatic transfer of software execution in response to a hardware event that is
asynchronous with the current software execution. This occurrence is called a trigger or an event.
• The hardware event can either be a busy to ready transition in an external I/O device (like the UART
input/output) or an internal event (like bus fault, memory fault, or a periodic timer).
• When the hardware needs service, signified by a busy to ready state transition, it will request an interrupt by
setting its trigger flag.
• A thread is defined as the path of action of software as it executes. The execution of the interrupt service
routine (ISR) is called a background thread. This thread is created by the hardware interrupt request and is
killed when the interrupt service routine returns from interrupt
• A new thread is created for each interrupt request. It is important to consider each individual request as a
separate thread because (just like functions) local variables and registers used in the interrupt service routine
are unique and separate from one interrupt event to the next interrupt.
• In a multi-threaded system, we consider the threads as cooperating to perform an overall task.

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Interrupts (cont’d)
Technical description

• Enabling / Disabling Interrupts

o When deciding to use interrupts, we may arm (disarm) a device, which means to means to enable (shut off)
the source of interrupts.
o Each potential interrupting trigger/event has a separate arm bit.
o One arms (disarms) a trigger/event if one is (is not) interested in interrupts from this source.
o To enable (disable) means to allow interrupts at this time (postponing interrupts until a later time).
o On the ARM Cortex-M processor there is one interrupt enable bit for the entire interrupt system.
o We disable interrupts if it is currently not convenient to accept interrupts. In particular, to disable interrupts
we set the I bit in PRIMASK

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Interrupts (cont’d)
Technical description

• Event Queuing
o If a trigger flag is set, but the interrupts are disabled (I=1), the interrupt level is not high enough, or the flag
is disarmed, the request is not dismissed. Rather the request is queued, postponed until a later time, when
the system deems it convenient to handle the requests.
o We will pay special attention to these enable/disable software actions. In other words, once the trigger flag
is set, under most cases it remains set until the software clears it.
• Completing an Interrupt
o Clear the interrupt trigger/event flag. This is called an acknowledgement.
• ISR
o The software module that is executed when the hardware requests an interrupt.
o Except for the SysTick interrupt, the ISR must clear the trigger flag that caused the interrupt (acknowledge).

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What happens when an Interrupt is triggered?
This is a fundamental difference between and ISR and a normal function

• In a procedural program, when you invoke a function you

know the state of the machine and you have control of the
various state/variable you want to store prior to execution
of the function.
• In an even based program, you cannot control when an
ISR is called, thus there must be a mechanism by which
machine state can be stored.
• When an interrupt is triggered, the following items occur:
o Registers pushed on the software stack
o Program Counter is set to Vector Address
o IPSR is set to 18 (interrupt program status register)
(recall NVIC – see 18 refers to PortC)
o LR’s top 24-bits set to FFFFFFFF (indicating ISR)
o LR’s bottom 8 bits set to F9 (this example) indicating
return method using the main stack pointer (MSP)

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 Click the picture icon to insert a background picture.
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NVIC
ARM Cortex-M4 Nested
Vectored Interrupt Controller

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Interrupt Vector Table
What can generate an interrupt and how does the microcontroller know where to find the ISRs?

• Microcontrollers that support event based

programming with interrupts will typically have
a table to stores the address of the ISR.
• The table is organized by the resources that
can throw/generate interrupts.
• On the right is a table from your textbook
showing a portion of your microcontroller’s
Interrupt Vector Table.
• On the Cortex-M4 this is called the NVIC,
which stands for Nested Vectored Interrupt
Controller.
• Notice the ISR names

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Interrupt Vector Table (cont’d)
What can generate an interrupt and how does the microcontroller know where to find the ISRs?

• The ISR names correspond to the microcontroller

resources which can trigger an interrupt.
• We see here the the following resources are
interrupt enabled:
o SysTick
o GPIOPort(s)
o Various serial communications
o Timers (not shown)
o Etc.
• Remember this is a partial table, see you
textbook and/or the Reference Manual for the
complete list.

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mcmaster.ca |
 ARM Cortex-M Interrupts
NVIC_ST_CTRL_R, bit 1
❑ Arm bit (also called enable)
❖ Separate arm bit for each source
❖ Software initializes arm bit to 1 to allow interrupts
❑ Trigger flag Count flag is in NVIC_ST_CTRL_R, bit 16
❖ hardware sets trigger when it wishes to request an interrupt
❖ software clears the trigger to signify processing done
❑ Interrupt priority (0=max to 7=lowest) NVIC_PRI3_R, bits 31-29
❖ Higher priority interrupt can suspend a lower ISR
❖ Lower/equal priority interrupt will wait until higher is done
❑ Interrupt enable (I bit)
❖ Global interrupt enable bit, I, in PRIMASK register
PRIMASK, bit 0
❖ To enable (I=0), execute CPSIE I EnableInterrupts();
❖ To disable (I=1), execute CPSID I DisableInterrupts();

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NVIC Interrupt Enable Registers

❑ Enable interrupt
❖ A single enable bit for each device
❖ NVIC_EN0_R for IRQ numbers 0 to 31
❖ NVIC_EN1_R for IRQ numbers 32 to 47
❖ SysTick does not need this enable step

NVIC_EN0_R = 0x000000002; // IRQ 1

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7-23
 ARM Cortex-M Interrupts

❑ Interrupt priority (0=max to 7=lowest)

❖ Higher priority interrupt can suspend a lower ISR
❖ Lower/equal priority interrupt will wait until higher is done

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7-25
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Interrupts
- Inputs

- SysTick

- Periodic Timers

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SysTick Interrupt
SysTick can be configured to
generate periodic interrupts
• If configuring each individual I/O device
for interrupt handling is too much, then
a hybrid approach may be taken.
• On the left is a typical polling busy/wait
approach.
• On the right, we can instead use
SysTick to trigger a simple periodic
ISR that polls the next I/O resource.
• This has the advantage that
processing can occur between periodic
I/O check, instead of at the end of all
I/O polling. Also, if a specific I/O
needed to occur every 3xPeriod then
this would accomplish that objective.

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SysTick Interrupt

• The SysTick timer is a simple way to create periodic interrupts.

• A periodic interrupt is one that is requested on a fixed time basis.
• This interfacing technique is required for data acquisition and control systems, because software servicing
must be performed at accurate time intervals. 

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SysTick Interrupt

• SysTick has a 24-bit counter that decrements at the bus clock frequency.
• Let fBUS be the frequency of the bus clock, and let n be the value of the RELOAD register.
• The frequency of the periodic interrupt will be fBUS/(n+1).

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SysTick Interrupt

• First, we clear the ENABLE bit to turn off SysTick during initialization.

• Second, we set the RELOAD register.
• Third, we write any value to NVIC_ST_CURRENT_R to clear the counter.
• Lastly, we write the desired mode to the control register, NVIC_ST_CTRL_R. We must set CLK_SRC=1.

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SysTick Interrupt

• We set INTEN to enable interrupts.

• We establish the priority of the SysTick interrupts using the SysTick field in the NVIC_SYS_PRI3_R register.
• We need to set the ENABLE bit so the counter will run.
• When the CURRENT value counts down from 1 to 0, the COUNT flag is set. On the next clock,
the CURRENT is loaded with the RELOAD value.

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SysTick Interrupt

• In this way, the SysTick counter (CURRENT) is continuously decrementing.

• If the RELOAD value is n, then the SysTick counter operates at modulo n+1 (…n, n-1, n-2 … 1, 0, n, n-1, …).
• In other words, it rolls over every n+1 counts. Thus, the COUNT flag will be set every n+1 counts.

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SysTick Interrupt

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GPIO Interrupt

• Synchronizing software to hardware events requires the software to recognize when the hardware changes
states from busy to done.
• Many times the busy to done state transition is signified by a rising (or falling) edge on a status signal in the
hardware.

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GPIO Interrupt

• For these situations, we connect this status signal to an input of the microcontroller, and we use edge-
triggered interfacing to configure the interface to set a flag on the rising (or falling) edge of the input.
• Using edge-triggered interfacing allows the software to respond quickly to changes in the external world.

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GPIO Interrupt
As shown earlier, GPIO can trigger an interrupt. Triggers can be edge sensitive or level sensitive.
When configuring the port for GPIO, we can also set the Port Mode.

Micro

PC1

PC2

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Choose/configure the edge for triggering
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 Interrupt
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Events Required to Create An Interrupt

• Configuring an Interrupt
o Arm the I/O device
o Enable NVIC
o Enable Global interrupts
o Set interrupt level
o Write the ISR to handle the interrupt Trigger

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 Discuss:
SoftBank Group (Boston Dynamics) Do you think a system like this is
procedural or even-based?
Why?

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Agility Robotics (Cassie)

http://spectrum.ieee.org/automaton/robotics/industrial-robots/agility-robotics-
introduces-cassie-a-dynamic-and-talented-robot-delivery-ostrich

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Looking Forward

• Studio

o Communications

o Interrupt

• Lab W8

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