ECE419
ECE419
CO1 :: Recall the syntax and semantics of Verilog for digital circuit modeling
CO2 :: Explain the fundamental principles of digital VLSI design using Verilog
CO3 :: Apply verilog programming techniques to design and simulate digital circuits.
CO4 :: Analyze the results of static timing analysis to ensure timing closure in VLSI design
CO6 :: Create robust system verilog test environments to verify complex digital VLSI designs
Unit I
Digital design with verilog HDL : Introduction to verilog HDL, Digital VLSI design flow, Design
methodology, Module, Port, Simulation, Lexical conventions, Data types, System task
Unit II
Programming techniques in Verilog I : Dataflow Modelling, Gate Level Modelling, Verilog gate
primitive, Continuous assignment, Delay specification, Expression, Operator type, Port connecting
rule, Module instantiation
Unit III
Programming techniques in Verilog II : Behavioral modelling Branching statement, Multiway
Branching, Behavioral modelling, Structured procedures, Conditional statement
Unit IV
Programming techniques in verilog-III : Loop statement, Procedure assignment, Sequential and
parallel block, Timing control, Task and function
Unit V
Programming techniques in verilog-IV : Finite state machine, Switch level modelling, Switch level
modelling element, Timing check, Critical path in digital circuit
Unit VI
Timing analysis and verification methodology : Overview of timing analysis, Setup-hold time
calculation, Setup time violation, Hold time violation, Introduction to verification and system verilog,
Verification guideline, Object oriented programming concepts in system verilog, Assertions in system
verilog, Randomization in system verilog, Functional coverage
Text Books:
1. VERILOG HDL by SAMIR PALNITKAR, PEARSON
References:
1. VERILOG DIGITAL SYSTEM DESIGN by ZAINALABEDIN NAWABI, MCGRAW HILL
EDUCATION