S905 Datasheet Revision 1.1.

A53 GIC Bit Interrupt sources Description

170 VCPUMNTIRQ0
169 PMUIRQ1
168 PMUIRQ0
167 1'b0
166 1'b0
165 1'b0
164 1'b0
163 1'b0
162 ctiirq3
161 ctiirq2
160 ctiirq1
127 ctiirq0
126
125 1'b0 unused
124 uart3_slip_irq UART slip
123 uart2_irq UART 2
122 1'b0 unused
121 1'b0 unused
120 1'b0 unused
119 rdma_done_int RDMA
118 I2S_cbus_ddr_irq Audio I2S CBUS IRQ
117 1'b0 unused
116 vid1_wr_irq
115 vdin1_vsync_int
114 vdin1_hsync_int
113 vdin0_vsync_int
112 vdin0_hsync_int
111 spi2_int
110 spi_int
109 vid0_wr_irq
108 1'b0 unused
107 1'b0 unused
106 1'b0 unused
105 uart1_irq
104 1'b0 unused
103 sar_adc_irq SAR ADC
102 1'b0 unused
101 gpio_irq[7] GPIO Interrupt
100 gpio_irq[6] GPIO Interrupt
99 gpio_irq[5] GPIO Interrupt
98 gpio_irq[4] GPIO Interrupt
97 gpio_irq[3] GPIO Interrupt
96 gpio_irq[2] GPIO Interrupt
95 gpio_irq[1] GPIO Interrupt
94 gpio_irq[0] GPIO Interrupt
93
92 TimerI TimerI
91 TimerH TimerH

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A53 GIC Bit Interrupt sources Description

90 TimerG TimerG
89 TimerF TimerF
88 1'b0 unused
87 hdcp22_irq
86 hdmi_tx_interrupt
85 1'b0 unused
84 hdmi_cec_interrupt
83 1'b0 unused
82 demux_int_2
81 dmc_irq
80 dmc_sec_irq
79 ai_iec958_int IEC958 interrupt
78 iec958_ddr_irq IEC958 DDR interrupt
77 I2S_irq I2S DDR Interrupt
76 crc_done From AIU CRC done
75 deint_irq Reserved for Deinterlacer
74 dos_mbox_slow_irq[2] DOS Mailbox 2
73 dos_mbox_slow_irq[1] DOS Mailbox 1
72 dos_mbox_slow_irq[0] DOS Mailbox 0
71 1'b0 unused
70 1'b0 unused
69 1'b0 unused
68 m_i2c_3_irq I2C Master #3
67 1'b0 unused
66 smartcard_irq
65 ndma_irq Block Move
64 spdif_irq
63 nand_irq
62 viff_empty_int_cpu
61 parser_int_cpu
60
59 U2d_interrupt USB
58 U3h_interrupt USB
57 Timer D Timer D
56 bus_mon1_fast_irq
55 bus_mon0_fast_irq
54 uart0_irq
53 async_fifo2_flush_irq
52 async_fifo2_fill_irq
51 demux_int
50 encif_irq
49 m_i2c_0_irq
48 bt656_irq
47 async_fifo_flush_irq
46 async_fifo_fill_irq
45 bt656_2_rq bt656_B
44 1'b0 unused
43 1'b0 unused

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A53 GIC Bit Interrupt sources Description

42 eth_lip_intro_o
41 1'b0 unused
40 1'b0 unused
39 Timer B Timer B
38 Timer A Timer A
37 1'b0 unused
36 eth_gmac_int
35 audin_irq
34 Timer C Timer C
33 demux_int_1
32 eth_pmt_intr_o

24.3 Register Description

Each register’s final address = 0xC1100000 + offset * 4

GPIO Interrupt EDGE and Polarity: 0x2620

This register controls the polarity of the GPIO interrupts and whether or not the interrupts are level or edge triggered. There
are 8 GPIO interrupts. These 8 GPIO interrupts can be assigned to any one of up to 256 pins on the chip.

Bit(s) R/W Default Description

31-24 R 0 unused
23 GPIO_POLARITY_PATH_7: If a bitin this field is 1, then the GPIO signal for GPIO interrupt path 7 is inverted.
22 GPIO_POLARITY_PATH_6:
21 GPIO_POLARITY_PATH_5:
20 GPIO_POLARITY_PATH_4:
19 GPIO_POLARITY_PATH_3:
18 GPIO_POLARITY_PATH_2:
17 GPIO_POLARITY_PATH_1:
16 R/W 0 GPIO_POLARITY_PATH_0:
15-8 R 0 Unused
7 R/W GPIO_EDGE_SEL_PATH_7: If a bit is set to 1, then the GPIO interrupt for GPIO path 7 is configured to be an
edge generated interrupt. If the polarity (above) is 0, then the interrupt is generated on the rising edge. If
the polarity is 1, then the interrupt is generated on the falling edge of the GPIO. If a bit is this field is 0, then
the GPIO is a level interrupt.
6 R/W GPIO_EDGE_SEL_PATH_6
5 R/W GPIO_EDGE_SEL_PATH_5
4 R/W GPIO_EDGE_SEL_PATH_4
3 R/W GPIO_EDGE_SEL_PATH_3
2 R/W GPIO_EDGE_SEL_PATH_2
1 R/W GPIO_EDGE_SEL_PATH_1
0 R/W 0 GPIO_EDGE_SEL_PATH_0

GPIO 0 ~ 3 Pin Select: 0x2621

Each GPIO interrupt can select from any number of up to 256 GPIO pins on the chip. The Bits below control the pin selection
for GPIO interrupts 0 ~3.

Bit(s) R/W Default Description

31-24 R/W 0 GPIO_PIN_SEL3: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 3
23-16 R/W 0 GPIO_PIN_SEL2: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 2
15-8 R/W 0 GPIO_PIN_SEL1: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 1

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Bit(s) R/W Default Description

7-0 R/W 0 GPIO_PIN_SEL0: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 0

GPIO 4 ~ 7 Pin Select: 0x2622

Bit(s) R/W Default Description
31-24 R/W 0 GPIO_PIN_SEL7: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 7
23-16 R/W 0 GPIO_PIN_SEL6: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 6
15-8 R/W 0 GPIO_PIN_SEL5: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 5
7-0 R/W 0 GPIO_PIN_SEL4: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 4

GPIO Filter Select (interrupts 0~7): 0x2623

Bit(s) R/W Default Description
31 R/W 0 unused
30-28 R/W 0 FILTER_SEL7: (see FILTER_SEL0)
27 R/W 0 Unused
26-24 R/W 0 FILTER_SEL6: (see FILTER_SEL0)
23 R/W 0 Unused
22-20 R/W 0 FILTER_SEL5: (see FILTER_SEL0)
19 R/W 0 Unused
18-16 R/W 0 FILTER_SEL4: (see FILTER_SEL0)
15 R/W 0 Unused
14-12 R/W 0 FILTER_SEL3: (see FILTER_SEL0)
11 R/W 0 Unused
10-8 R/W 0 FILTER_SEL2: (see FILTER_SEL0)
7 R/W 0 Unused
6-4 R/W 0 FILTER_SEL1: (see FILTER_SEL0)
3 R/W 0 unused
2-0 R/W 0 FILTER_SEL0: This value sets the filter selection for GPIO interrupt 0. A value of 0 = no filtering. A value of 7
corresponds to 7 x 3 x (111nS) of filtering.

25. DIRECT MEMORY ACCESS CONTROLLER (DMAC)

25.1 Overview
The DMA controller is an engine connected to the DDR controller for the purposes of moving data to/from DDR memory. The
DMA controller supports 4 independent threads. Each thread is driven by DMA table descriptors placed in DDR memory. Each
DMA descriptor consists of 8 entries that describe the source/destination location as well as the stride and burst. Inline
processing is also supported to allow data from DDR to be processed using an AES, Triple-DES, CRC, or SHA module before
being placed back into DDR memory.

25.2 Descriptor Table

Below is the descriptor Table.

Table III.25.1 Descriptor Table
Entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
( 01=system, 10=DMA engine,

Source Hold

Thread Slice Count

Dest Hold
Owner ID

NO Break
00=no woner)

Dmatab (0 = use default slice)

IRQ

0 INLINE Type
Pre Endian Number of 256-byte blocks to
allocate to this thread

1 SP: Source Pointer (AHB address)

2 DP: Destination Pointer (AHB address) (0xFFFFFFFF = send data to the parser)
3 Byte transfer count
4 Source Skip Source Burst Count
5 Destination Skip Destination Burst Count

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6-AES

Reset IV
Encrypt
CTR IN
CTR Endian Mode Type OUT Endian
Limit Endian

6-TDES

restart
6-CRC

nowrite
restart
CRC Count

6-SHA

Last blk
IN
Mode
Endian

6-OTHERS

Post Endian

25.3 Register Description

The following registers’ final address = 0xda832000 + offset*4

SEC_BLKMV_GEN_REG0 0x24
Bit(s) R/W Default Description
31-20 R/W ‘h0 ddr_secure_id
19-18 R/W ‘h0 ddr_non_sec_val
17-16 R/W ‘h0 ddr_sec_val1
15-14 R/W ‘h0 ddr_sec_val0
13-12 R/W ‘h0 sec_read_sel
11-8 R/W ‘hF non_sec_mask: 1 = a thread is non-secure
7-4 R/W ‘h0 sec_ddr_sec_id_en: Even though a thread is secure, we may not want it to use the DDR secure ID (JIC)
3-0 R/W ‘h0 ddr_thread_id[5:2]: 2-bit below used for security

SEC_BLKMV_AES_REG0 0x00
Bit(s) R/W Default Description
31 R - aes_key_valid: read-back signal of aes_key_valid
30 R/W ‘h0 Reserved
29-28 R/W ‘h0 aes_pio_ctr_limit: pio mode CTR limit: Counter set up of counter mode (CTR): 00 = 128-bit Counter in CTR mode, 01 =
32 bit counter, 10 = 64-bit counter. 11 = 128-bit counter
27-24 R/W ‘h0 aes_pio_ctr_endian: pio mode CTR endian: Endian set up of counter mode (CTR)
23-20 R/W ‘hF Reserved
19-18 R/W ‘h0 aes_pio_type: pio mode aes type: 00 = 128, 01 = 192, 10 = 256, 11 = reserved
17-16 R/W ‘h0 aes_pio_mode: pio mode aes mode: 00 = ECB mode, 01 = CBC mode, 10 = CTR mode, 11 = reserved
15-12 R/W ‘h0 aes_pio_out_endian: pio mode aes out endian: Endian control of the outgoing message
11-8 R/W ‘h0 aes_pio_in_endian: pio mode aes in endian: Endian control of the incoming message
7 R/W ‘h0 aes_pio_encrypt: pio mode aes encrypt sel: 0 = decrypt, 1 = encrypt
6 R/W ‘h0 aes_get_key_sim: Paused for simulation checking only
5-4 R/W ‘h0 aes_key_iv_thread:
3 R/W ‘h0 aes_use_sec_thread: used for woftware simulation/debug and PIO mode
2 R/W ‘h0 Reserved
1 R/W ‘h0 aes_pio_init_IV: (manual mode). Write with a 1 then a 0 to manually initialize the IV when running in PIO mode.
0 R/W ‘h0 aes_clk_en_jic: backup enable and also used when the CPU needs to load keys/IV values into the save/restore engine

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