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6.19.14 Host Control Capability Parameters (HCCPARAMS)

Offset: 0x1B000108 Identifies multiple mode control addressing
Access: Read-Only capability.
Reset Value: 0006h

Bit Name Description

31:16 RES Reserved. Must be set to 0.
15:8 EECP EHCI extended capabilities pointer (default = 0)
This optional field indicates the existence of a capabilities list.
7:4 IST Isochronous scheduling threshold; Indicates where software can reliably update the
isochronous schedule relative to the current position of the executing host controller.
bit [7] The value of the least significant three bits indicates the number of micro-frames a
= 0 host controller can hold a set of isochronous data structures (one or more) before
flushing the state
bit [7] Host software assumes the host controller may cache an isochronous data structure
= 1 for an entire frame
3 RES Reserved. Must be set to 0.
2 ASP Asynchronous schedule park capability (default = 1)
The feature can be disabled or enabled and set to a specific level by using the
asynchronous schedule park mode enable and asynchronous schedule park mode count
fields in the register “USB Command (USBCMD)” on page 239.
1 The host controller supports the park feature for high-speed queue heads in the
asynchronous schedule
1 PFL Programmable frame list flag
0 System software must use a frame list length of 1024 elements with this host
controller. The frame list size field in the register “USB Command (USBCMD)”
is read-only and must be set to zero.
1 System software can specify and use a smaller frame list and configure the host
controller via the frame list size field in the register “USB Command
(USBCMD)”. The frame list must always be aligned on a 4K-page boundary,
ensuring the frame list is always physically contiguous.
0 ADC 64-bit addressing capability; must be set to 0. 64-bit addressing capability is not supported.

6.19.15 Device Interface Version Number (DCIVERSION)

Offset: 0x1B000120
Access: Read-Only

Bit Name Description

31:16 RES Reserved. Must be set to 0.
15:0 DCIVERSION The device controller interface conforms to the two-byte BCD encoding of the
interface version number contained in this register.

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6.19.16 Device Control Capability Parameters (DCCPARAMS)

Offset: 0x1B000122
Access: Read-Only

Bit Name Description

31:9 RES Reserved. Must be set to 0.
8 HC Host capable; the controller can operate as an EHCI-compatible USB 2.0 host controller.
7 DC Device capable; when set to 1, this controller is capable of operating as a USB 2.0
device.
6:5 RES Reserved. Must be set to 0.
4:0 DEN Device endpoint number
Indicates the number of endpoints (0–16) built into the device controller. If this
controller is not device capable, this field is zero.

6.19.17 USB Command (USBCMD)

Offset: 0x1B000140
Access: See Field Descriptions
Reset Value: 00080B00h (host mode)
00080000h (device mode)

Bit Name Description

31:24 RES Reserved. Must be set to zero.
23:16 ITC RW Interrupt threshold control
System software uses this field to set the max. rate the host/device controller issues
interrupts at. ITC contains the maximum interrupt interval measured in micro-frames.
00h Immediate (no threshold)
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames
10h 16 micro-frames
20h 32 micro-frames
40h 64 micro-frames

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Bit Name Description

15 FS2 RW Frame list size
/RO Read/write if programmable frame list flag in the register “Host Control Structural
Parameters (HCSPARAMS)” on page 237 is set to one. Specifies the size of the frame
list that controls which bits in the register “USB Frame Index (FRINDEX)” on
page 246 to use for the frame list current index. This field is made up of bits [15, 3:2] of
this register.
000 1024 elements (4096 bytes) (default)
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
14 ATDT RW Add dTD tripwire (device mode only)
W Used as a semaphore to ensure the to proper addition of a new dTD to an active
(primed) endpoint’s linked list. This bit is set and cleared by software. This bit shall also
be cleared by hardware when is state machine is hazard region for which adding a dTD
to a primed endpoint may go unrecognized.
13 SUTW RW Setup tripwire (device mode only)
Used as a semaphore to ensure the 8-byte setup data payload is extracted from a QH by
the DCD without being corrupted. If the setup lockout mode is off, a hazard exists when
new setup data arrives while the DCD is copying the setup data payload from the QH
for a previous setup packet. This bit is set and cleared by software and cleared by
hardware when a hazard exists.
12 RES Reserved. Must be set to zero.
11 ASPE RW Asynchronous schedule park mode enable (optional)
/RO If the asynchronous park capability bit in the register “Host Control Structural
Parameters (HCSPARAMS)” is a one, this bit defaults to 1h and is R/W. Otherwise
the bit must be a zero and is RO. Software uses this bit to enable or disable park mode.
0 Park mode is disabled
1 Park mode is enabled
10 RES Reserved. Must be set to zero.
9 ASP1 RW Asynchronous schedule park mode count (optional)
/RO If the asynchronous park capability bit in the register “Host Control Structural
8 ASP0
Parameters (HCSPARAMS)” is a one, this field defaults to 3h and is R/W. Otherwise
it defaults to zero and is RO.
Contain a count of the number of successive transactions the host controller is allowed
to execute from a high-speed queue head on the asynchronous schedule before
continuing traversal of the asynchronous schedule. Valid values are 1h–3h. Software
should not write a zero to this bit when park mode is enabled.
7 RES Reserved. Must be set to zero.

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Bit Name Description

6 IAA RW Interrupt on asynchronous advance doorbell (host mode only)
Used as a doorbell by software to tell the host controller to issue an interrupt the next
time it advances asynchronous schedule. Software must write a 1 to this bit to ring the
doorbell. When the host controller has evicted all appropriate cached schedule states, it
sets the interrupt on the asynchronous advance status bit in the register “USB Status
(USBSTS)”. If the interrupt on synchronous advance enable bit in the register “USB
Interrupt Enable (USBINTR)” is set to one, the host controller asserts an interrupt at
the next interrupt threshold.
The host controller sets this bit to zero after setting the interrupt on the synchronous
advance status bit in the register “USB Status (USBSTS)” to one. Software should not
write a one to this bit if asynchronous schedule is inactive.
5 ASE RW Asynchronous schedule enable (host mode only)
0 Do not process the asynchronous schedule (default)
1 Use the register “Next Asynchronous List Address (ASYNCLISTADDR)”
to access the asynchronous schedule
4 PSE RW Periodic schedule enable (host mode only)
0 Do not process the periodic schedule (default)
1 Use the register “Frame List Base Address (PERIODICLISTBASE)” on
page 247 to access the asynchronous schedule
3 FS1 RW Frame list size
/RO See bit [15], “FS2”, for description.
2 FS0
1 RST RW Controller reset (RESET)
Software uses this bit to reset the controller. This bit is set to zero by the host/device
controller when the reset process is complete. Software cannot terminate the reset
process early by writing a zero to this register.
Host When this bit is enabled, the host controller resets internal pipelines, timers, etc.
to the initial values. Any transaction in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. SW should not set
this bit to 1 when HCHalted in the register “USB Status (USBSTS)” is set to 0.
Device When software writes a 1 to this bit, the device controller resets internal
pipelines, timers, etc. to the initial values. Writing a 1 to this bit when the device
is in the attached state is not recommended. To ensure the device is not in
attached state before initiating a device controller reset, primed endpoints must
be flushed and the run/stop bit [0] set to 0.
0 RS RW Run/Stop (1 = Run, 0 = stop (default))
Host When set to a 1, the host controller proceeds with the schedule and continues as
long as this bit is set to 1. When this bit is set to 0, the host controller completes
the current transaction on the USB then halts. The HCHalted bit in the register
“USB Status (USBSTS)” indicates when the host controller has completed the
transaction and stopped. Software should not write a one to this field unless the
host controller is stopped.
Device Writing a 1 to this bit causes the device controller to enable a pull-up on D+ and
initiates an attach event. This bit is not connected to pull-up enable, as the pull-
up becomes disabled on transitioning to high-speed mode. This bit to prevents
an attach event before the device controller is properly initialized. Writing a 0
causes a detach event.

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6.19.18 USB Status (USBSTS)

Offset: 0x1B000144 Indicates various states of the host/device
Access: See Field Descriptions controller and pending interrupts. This register
Reset Value: 0 does not indicate status resulting from a
transaction on the serial bus. Software clears
some bits in this register by writing a 1 to them.

Bit Name Description

31:26 RES Reserved. Must be set to zero.
25 TI RW General purpose timer interrupt 1
C Set when the counter in the register “General Purpose Timer 1 Control
(GPTIMER1CTRL)” on page 236 transitions to zero. Write-one-to-clear.
24 TI0 RW General purpose timer interrupt 0
C Set when the counter in the register “General Purpose Timer 0 Control
(GPTIMER0CTRL)” on page 235 transitions to zero. Write-one-to-clear.
23:20 RES Reserved. Must be set to zero.
19 UPI RW USB host periodic interrupt
C Set by the host controller when the cause of an interrupt is a completion of a USB
transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit
set and the TD was from the periodic schedule.
This bit is also set by the host controller when a short packet (the actual number of
bytes received was less than the expected number of bytes) is detected and the packet
is on the periodic schedule. Write-one-to-clear.
18 UAI RW USB host asynchronous interrupt
C Set by the host controller when the cause of an interrupt is a completion of a USB
transaction where the TD has an interrupt on complete (IOC) bit set AND the TD was
from the asynchronous schedule.
This bit is also set by the host controller when a short packet (the actual number of
bytes received was less than the expected number of bytes) is detected and the packet
is on the asynchronous schedule. Write-one-to-clear.
17 RES Reserved. Must be set to zero.
16 NAKI RO Set by hardware when for one endpoint, both the Tx/Rx endpoint NAK bit and the
corresponding Tx/Rx endpoint NAK enable bit are set. Automatically cleared by
hardware when the all enabled Tx/Rx endpoint NAK bits are cleared.
15 AS RO Reports the real status of the asynchronous schedule (host mode only)
The host controller is not required to immediately disable or enable the asynchronous
schedule when software transitions the asynchronous schedule enable bit in the
register “USB Command (USBCMD)” on page 239. When this bit and the
asynchronous schedule enable bit are the same value, the asynchronous schedule is
either enabled (1) or disabled (0 = Default).
14 PS RO Reports the real status of the periodic schedule (host mode only)
The host controller is not required to immediately disable or enable the periodic
schedule when software transitions the periodic schedule enable bit in the register
“USB Command (USBCMD)”. When this bit and the periodic schedule enable bit
are the same value, the periodic schedule is either enabled (1) or disabled (0 =
Default).
13 RCL RO Reclamation (host mode only)
Used to detect an empty asynchronous schedule.
12 HCH RO HCHaIted (host mode only)
This bit is a zero whenever the run/stop bit in the register “USB Command
(USBCMD)” is set to one. The host controller sets this bit to one (default setting) after
it has stopped executing because the run/stop bit is set to 0, either by software or by
the host controller hardware.

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Bit Name Description

11 RES Reserved. Must be set to zero.
10 ULPII RW ULPI interrupt
C Only present in designs where the configuration constant VUSB_HS_PHY_ULPI = 1.
9 RES Reserved. Must be set to zero.
8 SLI RW DCSuspend
C When a device controller enters a suspend state from an active state, this bit is set to 1.
Cleared by the device controller upon exiting from a suspend state. Write-one-to-
clear.
7 SRI RW Start-of-(micro-)frame (SOF) received
C When the device controller detects a SOF, this bit is set to 1. When a SOF is late, the
device controller automatically sets this bit to indicate that an SOF was expected, thus
this bit is set about every 1 ms in device FS mode and every 125 ms in HS mode, and
synchronized to the received SOF.
Because the device controller initializes to FS before connect, this bit is set at an
interval of 1 ms during the prelude to connect and chirp. Write-one-to-clear.
6 URI RW USB reset received (device controller only)
C When the device controller detects a USB Reset and enters the default state (0), this bit
is set to 1. Write-one-to-clear.
5 AAI RW Interrupt on asynchronous advance
C System software can force the host controller to issue an interrupt the next time the
host controller advances the asynchronous schedule by writing a 1 to the interrupt on
asynchronous advance doorbell bit in the register “USB Command (USBCMD)”.
Indicates the assertion of that interrupt source. Write-one-to-clear.
4 RES Reserved. Must be set to zero.
3 FRI RW Frame list rollover
C The host controller sets this bit to a 1 when the frame list index rolls over from its
maximum value to 0. The exact value at which the rollover occurs depends on frame
list size, e.g, if the size (as programmed in the frame list size field of the register “USB
Command (USBCMD)”) is 1024, the frame index register rolls over every time
FRINDEX [13] toggles. Similarly, if the size is 512, the host controller sets this bit to 1
every time FHINDEX [12] toggles. Write-one-to-clear.
2 PCI RW Port change detect
C
Host The host controller sets this bit to 1 when on any port, a connect status or a
port enable/disable change occurs, or the force port resume bit is set as the
result of a transition on the suspended port.
Device The device controller sets this bit to1 when the port controller enters full- or
high-speed operational state. When the port controller exits full- or high-
speed operation states due to reset or suspend events, the notification
mechanisms are the USB Reset Received bit and the DCSuspend bits
respectively. Write-one-to-clear.
1 UEI RW USB error interrupt
C When completion of a USB transaction results in an error condition, this bit along with
the USBINT bit is set by the host/device controller if the TD on which the error
interrupt occurred also had its interrupt on complete (IOC) bit set. Write-one-to-clear.
0 UI RW USB interrupt
C Set by the host/device controller when the cause of an interrupt is a completion of a
USB transaction where the TD has an interrupt on complete (IOC) bit set.
Also set by the host/device controller when a short packet (the actual number of bytes
received was less than the expected number of bytes) is detected. Write-one-to-clear.

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