STA

Uncertainty:

Uncertainty is nothing but the combination of skew, jitters and PD margins is called as
Uncertainty

At Placement stage

Setup uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + jitter (1% of clock
period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + Pd extra margin (10
to 15ps) for hold jitter won't be there, in hold uncertainty because they hold does not depend
up clock period

At Clock Tree Synthesis

Setup uncertainty:

Take uncertainty with the combination of jitter (1% of clock period) + Pd extra margin (50ps) for
setup

Hold Uncertainty:

Take uncertainty value-based on Pd extra margin (10 to 15ps) for setup jitter won't be there in
hold uncertainty because they hold does not depend up clock period

After propagating the clock skew will be Met so skew is 0

Duty cycle = Active pulse width / entire clock period

what is the duty cycle of a clock with the period of 10, and the waveform is {2 7}

Duty cycle = {falling edge -rising edge} / clock period

clock jitter:

from cycle to cycle clock period and duty cycle can change slightly due to clock generation
circuitry is called as jitter

Empty module: It has only inputs and outputs information, it doesn't have any logic inside the
module definition.

Unresolved references :Module definition is present but timing library is missing is called
unresolved references

Block_Box :Macros are block boxes ,there is no functional information but it has timing info

Boundary Optimization:

Propagation of constant across the boundary

Propagation of equal and opposite information across the hierarchy

propagation of unconnected Port information across hierarchy

Pushing of inverters across the hierarchy

Virtual clock

Virtual clock is a clock it is doesn't associated with any clock pin or Port of the design

it will be used to validate the input to output timing paths

It is reference to static timing analysis to validate the reg2out ,in2out paths or in2reg paths

Data Arrival Time:

Time taken by the signal to propagate from clock definition point to the D pin of the capturing
flop is called as data arrival time

DAT = Tlaunch + Tcq+Tcombo+net delays

Data required time:

Data required time is the time taken by the signal from clock definition point to the clock pin of
the capturing flop is called as the data required time

DRT = Tclk +Tcapture +clock logic Delay -Tsetup -Tuncrtainty+clock net delay for setup time
analysis

Transition: Time taken by the signal can change their state from 0 to 1 or 1 to 0 is called as the
Transition

Slew: The rate of change of transition is called as Slew

Skew: The clock path arrival difference between the two successive clocks is called as Skew
Cell Delay: Time taken by signal to propagate through the cell.Cell delay is based on input
transition and output load is called as cell delay. This delay is based on cell rise and cell fall
delay .It is difference b/w 50 % of input tansition to the 50% of output transition.

Clock Latency :Latency is the combination of both source latency and network latency

Clock Latency = source latency + Network latency

Source latency:Time taken by the signal to propagate from the clock source to clock definition
point

Network latency: Time is taken by the signal to propagate from clock definition point to
register clock pin

CROSSTALK:-

Cross talk:

Cross talk is nothing but ,switching in one net can interfere neighbouring net due to the cross
coupling capacitance between that , this is called as cross talk

switching signal is Aggressor

Non switching signal is victim

Effects of Cross talk

Cross talk leads to timing violations

Functional failure

How cross talk will impact on the timing

case 1

If the signal is switching in same direction , victim transition becomes fast resulting data to
arrival early which leads to hold violations

This scenario is good for setup and bad for hold

case 2

if the signal is switching in opposite directions , victims transition becomes slows down ,which
increasing the delay and leads to setup violation
This scenario is good for hold and bad for setup

case 3

If cross talk in clock path the above cases are opposite

Note

Same Direction means :-

Aggressor and victim signal state are changing from 0 to 1

Opposite Directions means :-

Aggressor is switching from 0 to 1 and victim is switching from 1 to 0

Conditions for above 3 cases are , when Switching window will match then only timing
violations will come otherwise noise will come

On What factor cross talk depends:-

Amount of cross_couple capacitance

Slew rate of signal transition

Switching Direction

Cross_Talk reduction techniques:-

 Apply NDR rules (Double spacing)

 Upsize the victim net driver

 Downsize the victim net driver

 Shielding the victim net by Vss

 Jumping to the higher metal layer

 Use buffer at the middle of the victim nets

Scan chain Reordering

 The scan chain reordering is performed at Placement

 scan chain can reduce the wire length and congestion

 scan chain can performed based on their physical location of the flops

Benefits with the Scan chain reordering:

 Lesser the length will reduce the resistance and capacitance

 Lower values of R and C will improve the timing

 It will reduce the congestion

Path based analysis Vs Graph based analysis

In GBA mode the tool consider both the worst slew and worst arrival in a path during the
analysis

In PBA mode the tool consider the path by path

for setup analysis ,in GBA it will consider worst values among all the four values (observe the
below picture), For PBA it will consider path by path and timing arc by timing arc

For hold analysis, in GBA it will consider best value (less value) among all the four values

Conclusion is GBA is more pessimistic than PBA

PBA with AOCV is the Best Timing

mindelay _GBa <= mindelay PBA

max_delay GBA >= max_delay in PBA

For fixes of the Electro migration violations ,will increase the width of the metal layers

If will increase the metal width of that net ,the net resistance capacitance will decrease it leads
to fastened the data

Due to that that, the delay of the metal layer will decrease

Due to lesser values of the R and C the transition of that metal layer may increase it leads to
hold time violations

This timing violations are based on the life time of the chip

Electro_migration:

Electro migration is nothing but , the current in a metal wire is more than the current carrying
capability of that metal wire is called Electro migration

Electro migration can lead to opens or shorts due to metal ion displacement caused by the flow
of electrons

Electro migration will come in both Power ans Signal nets

Power Em is more crucial than signal em because the current direction in the power net is uni
direction but in signal both the direction that's why less electromigration in signal nets
compared to power nets

Electro migration Fixing techniques

Increasing the Metal width will to fix the electromigration ,which means if you increase the
metal width the current carrying capability of that metal wire will increase , means the current
density will reduce

current density = current / area

Area =width x thickness

sigma = current /W*T

current density and width is inversely proportional

Metal jumping Top metal layers also a one of the technique because Top metal layer width is
high compared to lower metal layers

Non Default rules double width will help to fix the Em violations

Layer Promotion

Use Buffer to decrease the wirelength

IR Drop:-

IR drop will occur due to the internal resistance, capacitance factors of the net . instance or cell
may not get the sufficient voltage to drive the cell is called IR Drop

Due to IR Drop cell may not work properly because the cell didn't get the sufficient supply
voltage

Due to this DROP the output of the cell may take lot of time to store the output of the that
instance or cell it leads fail the timing

How It will impact on the timing:

Due to that IR drop , cell output may take lot of time it leads to setup time violation

Reasons:

Consider two flops are connected in cascade

Assume 1st Flop is launching flop and second flop is Capturing Flop

Due to the internal resistance and cap values the data can go slow in data path which means it
may take time

When data path is slower than the clock path it leads to Setup time violation

IR drop will help to Hold time Violations

If IR drop is more in the clock path it may get both setup and hold violation

Types of IR Drop:-

Static IR:- It occurs because of leakage current

Vstatic = Iavg*R(wire)

Dynamic IR:- Due to switching activity of transistor then it increases the current requirement
during switching

Techniques to Reduce IR Drops:-

Cell padding or Partial blockages

Multiple straps & Vias

Downsize the cell

Insert Dcap cells where there is more IR drop

We Can also use HVT cells

Clock gating to reduce dynamic power

Physical DRC's

 Minimum width and spacing for metal

 Minimum width and spacing for via

 End of line spacing

 Via Enclose

 Parallel length spacing

 Minimum area

 Misaligned net Spacing

 Non sufficient Metal overlap

 Shorts violations

 Less than min edge Length

 Different net via cut spacing

 Special notch spacing

Order of Fixing the timing violations

Cross talk Noise

Bottleneck analysis

Fan-out

capacitance

transition

hold time violation

setup time violations

Report_annotated_delay
Annotated delay means To set cell/net delay.

To set a cell delay, specify the delay from a cell input to an output of the same cell.

To set a net delay, you specify the delay from a cell output to a cell input.

In a design that uses SDF-annotated delays on all arcs or almost all arcs, such as 95% or more

Annotated delay Means :RC values are applied properly

Non -Annotated Delay means: RC values are not applied properly

For any arcs that are not annotated, Sign-off Tool estimates the delay and output slew using
the best available input slew.

For a block of arcs that are not annotated, Tool propagates the worst slew throughout the
block.

Low power cells

Clock gating cells

Power Gating

Level shifters

Retention registers

Switch cells

Clock gating cells

Clock gating can be inserted without changing the function of the logic

Add clock gating in clock path to prevent the clock cycles

clock gating cells are used to reduce the dynamic power

Power gating cells

Which is used to shutoff the Power supply to the particular region

Power gates are use to reduce the leakage Power

Header switch and Footer Switch

Header switch will connect between VDD and PMOS

Footer Switch will connect between NMOS and VSS

When SLEEP = 0 transistor will work normally (SLEEP 0 and 1 is based on power control
management)

When SLEEP =1 transistor will turn off

SLEEP transistors are used to control Power to the selected blocks

Disadvantages: To turn on the PMOS it may take long time it causes more IR drop compare to
NMOS

More number of transistor at time to turn ,it means more current is required to turn at that
time drop may come

Level Shifters

Level shifter's are classified into two types

High_to_low Level shifter

Low_to_High Level shifter

High to low Level shifter is used The signal going from the high voltage domain to low voltage
domain the gate of the transistor may damage in the receiving domain ,or cause signal EM
that's why we use the High to low Level shifter

Low to high level shifter is used when ,the potential difference between the two voltage
domain is greater than the subtraction of ground bounce % in VDDh from threshold voltage ,
low voltage signal is driving the high voltage domain ,may cause crow bar currents to avoid we
use this Level Shifter

VDDH-VDDL > Vth-{%of ground bounce of VDDH}

One of the fundamental reason is that example 1Vsignal is driving the 1.5V gate will turn on
both NMOS and CMOS it may cause crowbar current

To meet certain requirements ,signal rise or fall time degradation between the driving cell in
one domain and the receiving into another domain it may cause Timing Violations

When the signal is going from 1V voltage domain to 1.5V voltage domain are vise verse we use
Level Shiters

Normally we can put the level shifter in three places like in transmitter domain or in receiver
domain or between the Domains

Basically Level shifters are placed in the destination Domain

Retention Registers (Shadow Register)

while doing any job in the device , when power supply of the device is turn off the state of the
info is lost, to resume the state of the info when its Power up
The block must have its state restore from external source build up its state from the reset
condition

we can keep inside the always on logic

It will placed in placement stage

Height of the retention flop is double of the standard cell row (For 45nm 1.71 is the row height
)

Flop height is equals to 2*row height

Switch cells:

Switch cells are used to Power up / down for the rails to the particular block we use switch cells

which are placed under the stripes

Switch cell has two Power inputs and one output

External power input, PSO for signal, PSO_out , VDD, VSS

Inputs are control input and power supply

Output is power output (input voltage is equal to output voltage)

Which are placed in ring fashion or column fashion or daisy chain format

Which are placed in daisy chain format to switch on the rails

More number of switch cells are required to turn on the rails ,at a time more logic need to turn
on , so if we provide less it cause IR drop issue

Got placed in Power plan stage

retention flops ,Always_on_cells, level shifters and isolation cells are placed at placement stage

Sanity checks for STA:

Linking Checks:

We need to check., is there any missing modules or missing pins in a library. this is done by link
command.

Constraint checks:

In constraint checks we need to check the SDC, i.e. if there are any no-clock, no-input delay, or
unconstrained endpoints. this can be done by the check_timing command.

Parasitic checks:
In parasitic check we need to check the not annotated nets

Max transition violations

Upsize the cell.

Insert a buffer when the net is dominant.

Buffer can be replaced with inverter pair.

Move the cells nearer.

Vt swapping from HVT cells to LVT cells

Metal width increases

Metal jogging from lower to higher metals

Max cap/Fanout

Upsize the cell

Load splitting.

Cloning

Swapping