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Fixes at STA - Aravind Bandi

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82 views31 pages

Fixes at STA - Aravind Bandi

Uploaded by

Vivek jha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Fixes in STA

- Aravind Bandi
Setup Violations
Method 1: Reduce the number of buffers on the path

This will reduce the cell delay. The number of cells is reduced, but this
reduction is not simply a geometric reduction. The degree of reduction
should be less than "the number of removed buffers ✖ the original cell
delay"; because when the net wire becomes longer, the current
attenuation from one end of the net to the other end of the net is more
serious, and the charging speed of the device is slowed down.
However, the net delay will increase, the total length of the net wire will
increase, the RC parameters will increase, and the RC curve will be longer.

CMD: eco_delete_reapeter -net/pin


Method 2: Use a pair of inverters to replace the buffer
•  We know that the structure of the buffer is basically equivalent to two
• inverters. Using a pair of inverters to replace the buffer can reduce the
• total delay on the path. Compared to using only one buffer, a pair of
inverters will reduce the
• transition time by two times, so this will reduce the RC delay. The cell
delay
• of a buffer is approximately equal to the cell delay of a pair of inverters,
but the net delay is reduced, so the total delay is reduced.

• CMD: eco_add_repeater -pins $l -relative_distance_to_sink 0.1 -cells


BUF_X2
Method 3: Swap VT
• It means changing the VT of the cell, that is, replacing the HVT with
• SVT/RVT or LVT. Under the same conditions, the gate threshold voltage of
the low VT cell is
• lower, so the slew of the cell itself is smaller; under the same conditions,
the gate conduction current of the low VT cell is larger, so the charging
• speed of the subsequent net wire is faster. Therefore, low VT cells are
equivalent to reducing the total delay from
• both the cell delay and net delay perspectives. However, the static current
of Low VT cells is larger and the static power
• consumption is also larger.
• CMD: eco_update_cell -cell_name -upsize/downzize
Method 4: Increase drive strength (size-up cell)
• Generally speaking, cells with larger drivers have higher speeds, but
for
• some cell types, larger cells may be slower. However, this will also
make the power higher and the area larger.
Method 5: insert buffer
• Inserting a buffer will reduce the transition time, which will reduce
the net
• delay. If the reduction in total net delay is greater than the increase in
cell
• delay, then the total delay will be reduced. However, this will also
result in an increase in power and area.
CMD: eco_add_repeater -pins $l -relative_distance_to_sink 0.1 -cells
BUF_X2
Method 7: Adjust the cell location in the layout
•  The essence is to reduce net delay.
Method 8: Adjust clock skew
• It is to borrow the setup margin from the next level through skew
adjustment.
Method 11: Repair crosstalk
• In addition to adding shielding and NDR rules, another way to fix
crosstalk is to remove or move the various routing lines around the
violation point further away.

CMD: report_noise -crosstalk


report_delay_calculation
Hold Violation techniques
Below are the steps to fix hold violations:
• Gate sizing
• Improving the hold time constraint of launch flip-flop
• Increase the clock-q delay of launch flip-flop
• Adding buffers/delay cells in the data path
• Vt swapping
• Dummy loads
• Skewing
• Reduce operating voltage
Hold Violations
Method 1: add delay
You can use buffers, inverter pairs, and delay cells to fix hold violation.
Since the start point and end point of the hold violation path may
correspond to other setup violation paths (or the setup slack is tight),
you need to be extra careful when adding delay. In addition, generally
do not add delay to the common path of two timing paths.
Method 21: size-down cell
Try to go to the cell near the size end-point as much as possible to
minimize the impact on other paths.

• In addition, you can also repair hold by repairing crosstalk and manual
routing
Min Period
• Minimum period of the clock input of a lib can be checked in Synopsys
Primetime tool. Imagine a scenario where a design A, is having a clock
named clk and the design is characterised with the cik's period as a
value say 2 ns, ie 500 MHz. Suppose we are reading the .lib for this
design A, at the Top level for Static Timing Analysis, and the period
defined for the top level clock, which is connected to A's clk is 1 ns ie,
1GHz. Definitely, the design A is not going to function properly. To find
out such discrepancies we can check for the min_period violations.
For this the min_period con- straint for the clk should be specified
inside the .lib of A.
Min Period
• The minimum period constraint can be added in the library as below

• pin (CP) {
• direction: input;
• capacitance: 1.2;
• min_period: 2; /* This is the minimum period contraint which is given inside the .lib */

• This tells that the clock, which is reaching at the CP pin, should be having a minimum period
of 2 ns. If it is not, then it will be shown as violated by how much slack, in the
report_constraint- min_period-verbose report. This will be as well, a part in,
report_constraint -all_violators report too.
• The command report_analysis_coverage also covers min_period checks. It can be checked as
below
• report_analysis_coverage-check_type min_period
Min Period
• What needs to be done when min_period violations are seen?

• These violations should be checked and analysed at the initial phase


of the design cycle itself. First we need to analyse whether that
particular clock is expected to reach at that design instance.
Sometimes multiple clocks can reach the same pin due to some
missing case analysis. Also confirm whether the particular pin is
consumed as a clock itself inside the .lib design. After the analysis, if it
turns out to be a valid min_period violation, we need to inform the
top level architecture/RTL team and the design.lib owners, about the
frequency discrepancy and get it fixed from them.
Crosstalk
• Switching of the signal in one net can interfere neighbouring net due
to cross coupling capacitance.This affect is known as cross talk.
fixes of cross talk:
Double spacing=>more spacing=>less capacitance=>less cross talk
Multiple vias=>less resistance=>less RC delay
Shielding=> constant cross coupling capacitance =>known value of
crosstalk
Buffer insertion=>boost the victim strength
Increasing the Drive strength of victim net
Decrease the Drive strength of aggressor net
Net Improvement

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