EE207: Digital Systems I, Semester I 2003/2004

CHAPTER 3 -ii: Combinational Logic Design

Design Procedure, Encoders/Decoders (Sections 3.4 3.6)

Overview
Design Procedure Code Converters Binary Decoders

Binary Encoders Priority Encoders

Expansion Circuit implementation

Combinational Circuit Design

Design of a combinational circuit is the development of a circuit from a description of its function.
Starts with a problem specification and produces a logic diagram or set of boolean equations that represent the circuit.

Design Procedure
5. 1. 2.

3.

4.

ts Det and outputs and assign variables to them. erm Derive the truth table that defines the ine required relationship between inputs and outputs. the Obtain and simplify the Boolean function (Kreq maps, algebraic manipulation, CAD tools, ). Consider any design constraints (area, delay, uire power, available libraries, etc). d Draw the logic diagram. num Verify the correctness of the design. ber of inpu

Design Example
Design a combinational circuit with 4 inputs that generates a 1 when the # of 1s equals the # of 0s. Use only 2-input NOR gates

More Examples - Code Converters

Code Converters transform/convert information from one code to another:

BCD-to-Excess-3 Code Converter

Useful in some cases for digital arithmetic

BCD-to-Seven-Segment Converter

Used to display numeric info on 7 segment displays

BCD-to-Excess-3 Code Converter

Design a circuit that converts a binarycoded-decimal (BCD) codeword to its corresponding excess-3 codeword. corresponding excess-3 codeword (n+3)2 Excess-3 code: Given a decimal digit n, its

Example: n=5 n+3=8 1000excess-3 n=0 n+3=3 0011excess-3 We need 4 input variables (A,B,C,D) and 4 output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D).

BCD-to-Excess-3 Converter (cont.)

The truth table relating the input and output variables is shown below Note that the outputs for inputs 1010 through 1111 aredon't cares (n shown here).

Maps for BCD-to-Excess-3 Code Converter

The K-maps for are constructed using the don't care terms

BCD-to-Excess-3 Converter (cont.

Another Code Converter Example: BCD-to-Seven-Segment Converter

Seven-segment display:
7 LEDs (light emitting diodes), each one controlled by an input a 1 means on, 0 means off b g

Set a, b, c, d, g to 1

Set e, f to 0

Display digit 3?

BCD-to-Seven-Segment Converter

Input is a 4-bit BCD code 4 inputs (w, x, y, z). Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. a
f b

11110 e c I np (a=b=c=d=e=f=1, g=0) ut : 0 0 0 0B

CD

O ut Example: pu t: 11

BCD-to-Seven-Segment (cont.) Truth Table

Digit 0 1 2 3 wxyz 0000 0001 0010 0011 abcdefg 1111110 0110000 1101101 1111001 Digit 8 9 wxyz 1000 1001 1010 1011 abcdefg 1111111 111X011 XXXXXXX XXXXXXX

4 5 6

0100 0101 0110

0110011 1011011 X011111

1100 1101 1110

XXXXXXX XXXXXXX XXXXXXX

0111

11100X0

1111

XXXXXXX

??

Decoders
A combinational circuit that converts binary information from n coded inputs to a maximum 2n decoded outputs n-to- 2n decoder

n-to-m decoder, m = 2n

Examples: BCD-to-7-segment decoder, where n=4 and m=7

ecoders (cont.)

to-4 Decoder

to-4 Active Low Decoder

daatdata

3-to-8 Decoder

adderssaddress

3-to-8 Decoder (cont.)

Three inputs, A0, A1, A2, are decoded into eight outputs, D0 through D7 Each output Di represents one of the minterms of the 3 input variables. Di = 1 when the binary number A2A1A0 = i Shorthand: Di = mi The output variables are mutually exclusive;

ex 1 at any time, ac and the other seven are 0. tly on e ou tp ut ha s th e val ue

Implementing Boolean functions using decoders

A onal circuit can be constructed using decoders and OR gates! Why? n Here is an example: y Implement a full adder circuit with a decoder and two OR gates. c Recall full adder equations, and let X, Y, and Z o be the inputs: m Since there are 3 inputs and a total of 8 bi minterms, we need a 3-to-8 decoder. n a ti
S(X,Y,Z) = X+Y+Z = m(1,2,4,7) C (X,Y,Z) = m(3, 5, 6, 7).

Implementing a Binary Adder Using a Decoder

S(X,Y,Z) = Sm(1,2,4,7) C(X,Y,Z) = Sm(3,5,6,7)

Decoder Expansions
Larger decoders can be constructed using a number of smaller ones. -> HIERARCHICAL design! Example: A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable signals to the four 4-

to-16 decoders).

3-to-8 decoder using two 2-to-4 decoders

4-input tree decoder

Encoders
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1.

Encoders (cont.)

Encoder Example
Example:

8-to-3 binary encoder (octal-to-binary)

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

Encoder Example (cont.)

Simple Encoder Design Issues

There are two ambiguities associated with the design of a simple encoder:
1.

Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111. An output with all 0's can be generated when all

2.

the inputs are 0's,or when D0 is equal to 1.

Priority Encoders
Solves the ambiguities mentioned above. Multiple asserted inputs are allowed; one has priority over all others. Separate indication of no asserted inputs.

Example: 4-to-2 Priority Encoder Truth Table

4-to-2 Priority Encoder (cont.)

The operation of the priority encoder is such that: If two or more inputs are equal to 1 at the same time, the input in the highestnumbered position will take precedence. A valid output indicator, designated by

V, more is inputs are equal to 1. V = D3 + D2 + D1 + se D0 by inspection. t to 1 on ly w he n on e or

Example: 4-to-2 Priority Encoder K-Maps

Example: 4-to-2 Priority Encoder Logic Diagram

8-to-3 Priority Encoder

A Matrix of switches = Keypad

C0 C1 C2 C3

7 1 4 0 2 5

8 A 3 6

9 B F E D C
R0 R1 R2 R3

Keypad Decoder IC - Encoder

COL. 4-bit

1 4 7

2 5 8

3 6 9

F E D
ROW 4-bit

4-bit Binary (encoded

Priority Interrupt Encoder Schematic

Interrupting Devices
Device A

Interrupt Encoder

Microprocessor

Device B

Req(1:0)

Device C

Device D IntRq

Priority Encoding - Interrupt Requests

Interrupting Device A 0 0 B 0 0 C 0 0 D 0 1 Req (1:0) IntRq 00 00 0 1

0 0 0

0 0 1

1 1 0

0 1 0

01 01 10

1 1 1

Exercise: Complete this table?