Decoder

Decoder
• 2-to-4,
• 3-to-8,
• …
• n-to-2n E A B C O0 O1 O2 O3 O4 O5 O6 O7

0 X X X 0 0 0 0 0 0 0 0
O0 ABC
O1 ABC 1 0 0 0 1 0 0 0 0 0 0 0
A S2
O2 ABC 1 0 0 1 0 1 0 0 0 0 0 0
B S1 3:8 O3 ABC
1 0 1 0 0 0 1 0 0 0 0 0
dec O4 ABC
C S0
O5 ABC 1 0 1 1 0 0 0 1 0 0 0 0

O6 ABC 1 1 0 0 0 0 0 0 1 0 0 0
O7 ABC 1 1 0 1 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
Enb

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 Decoder

E?

3
 Design Using Decoder
• Applications:
 Implementing General Logic
 Any combinational circuit can be constructed using decoders
and OR gates!
• Example: 0
1
F1 = A' B C' D + A' B' C D + A B C D 2
F2 = A B C' D' + A B C 3
A S3
F3 = (A' + B' + C' + D') 4
5
S2
B 4:16
6
7
S1 dec
C 8
9
S0 10
D
11
12
13
14
15

Enb

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 Design Using Decoder
• Applications:
 Implementing General Logic
 Any combinational circuit can be constructed using decoders
and OR gates!
• Example: 0 A‘B’C’D’
1 A ‘B’C’D
F1
F1 = A' B C' D + A' B' C D + A B C D 2 A‘B’CD’
F2 = A B C' D' + A B C 3 A‘B’CD
A S3
F3 = (A' + B' + C' + D') 4 A‘BC’D’
5 A‘BC’D
S2
B 4:16
6 A‘BCD’
7 A‘ BCD
S1 dec
C 8 A B’C’D’ F2
9 A B’C’D
S0 10 A B’CD’
D
11 A B’CD
12 A B C’D’
13 A B C’D
14 A B C D’ F3
15 AB C D

Enb

5
 Active Low
• Decoder with
 Active Low Enable
 Active Low Outputs

G A B Y0 Y1 Y2 Y3
1 X X 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

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74x139 dual 2-to-4 decoder

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74x138 3-8 Decoder

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74x138 3-8 Decoder

9
 Using 3-State Buffers
 Can use 3-state buffers to share a single line for
several devices.
Decoder guarantees
that no two buffers are
on simultaneously.

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 Decoders
 Can build a decoder by smaller decoders

O0
A
0 S2 O1
O2
1 B S1 O3
2
3:8 O4
S0 dec
3 O5
A S3 4 O6
5 Enb O7
S2
B 4:16
6
7
S1 dec C
C 8
9 O0
S0 10
D S2 O1
11 O2
12 S1 O3
3:8 O4
13 S0 dec
O5
14
15 D O6
Enb O7

Enb

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Decoders

12
 Decoders
 Can build a decoder by smaller decoders

O0
A
0 B S2 O1
O2
1 B C S1 O3
2
3:8 O4
D S0 dec
3 O5
A S3 4 O6
5 Enb O7
S2
B 4:16
6
7
S1 dec C
C 8
9 O0
S0 10
D B S2 O1
11 O2
12 C S1 O3
3:8 O4
13 D S0 dec
O5
14
15 D O6
Enb O7

Enb

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 Decoders
 How to build a 5-32 decoder by
using 4-16 and 2-4 decoders?

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 Decoders
• Decoder: a more general term
 Our focus was on “binary decoders”

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 7-Segment Decoder

• Seven-segment display:
7 LEDs (light emitting diodes), each one
controlled by an input a
1 means “on”, 0 means “off”
f b
Display digit “3”? g
Set a, b, c, d, g to 1
Set e, f to 0 e c

d
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7-Segment Decoder

C0

C5 C1
C6

C4 C2
C3

C C C C C C C
0 1 2 3 4 5 6

BCD-to-7-segment
control signal
decoder

A B C D
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 7-Segment Decoder
• 7-Segment Decoder:
Input is a 4-bit BCD code  4 inputs (A, B, C,
D).
Output is a 7-bit code (a,b,c,d,e,f,g) that
allows for the decimal equivalent to be
displayed.
a
• Example:
Input: 0000BCD f g b
Output: 1111110 e c
(a=b=c=d=e=f=1, g=0)
d
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 BCD-to-7Segment Truth Table

Digit ABCD abcdefg Digit ABCD abcdefg

0 0000 1111110 8 1000 1111111
9 1001 111X011
1 0001 0110000
1010 XXXXXXX
2 0010 1101101
1011 XXXXXXX
3 0011 1111001
1100 XXXXXXX
4 0100 0110011
1101 XXXXXXX
5 0101 1011011 1110 XXXXXXX
6 0110 X011111 1111 XXXXXXX
7 0111 11100X0

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 AB
A
AB
K-maps A
AB
A

CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10

00 1 0 X 1 00 1 1 X 1 00 1 1 X 1

01 0 1 X 1 01 1 0 X 1 01 1 1 X 1
D D D
11 1 1 X X 11 1 1 X X 11 1 1 X X
C C C
10 1 1 X X 10 1 0 X X 10 0 1 X X

B B B
K-map for a K-map for b K-map for c
A A A A
AB AB AB AB
00 01 11 10 00 01 11 10 00 01 11 10 CD 00 01 11 10
CD CD CD
00 1 0 X 1 00 1 0 X 1 00 1 1 X 1 00 0 1 X 1

01 0 1 X 0 01 0 0 X 0 01 0 1 X 1 01 0 1 X 1
D D D D
11 1 0 X X 11 0 0 X X 11 0 0 X X 11 1 0 X X
C C C C
10 1 1 X X 10 1 1 X X 10 0 1 X X 10 1 1 X X

B B B B

K-map for d K-map for e K-map for f K-map for g

a = A + B D + C + B' D' d = B' D' + C D' + B C' D + B' C

b = A + C' D' + C D + B' e = B' D' + C D
c = A + B + C' + D f = A + C' D' + B D' + B C'
g = A + C D' + B C' + B' C
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Encoder
 Encoder
• Encoder:
 Inverse operation of a decoder
 Has 2n input lines and n output lines.
 The output lines generate the binary
equivalent of the input line whose value is 1.

I0
4-2 z1
I1
Binary
I2
Encoder z2
I3

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 Encoder

O0 I0
A S2 O1 I1 Z2 A
O2 I2
B S1 3:8 O3 I3 Z1 B
8:3
C decoder O4 I4 encoder
S0 Z0 C
O5 I5
O6 I6
O7 I7

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 Encoder Circuit Design
• Example:
 8-3 Binary Encoder

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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Encoder Circuit
With Enable

With Acknowledge
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 Application

The number of inputs: large

 fewer lines
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 Encoder Design Issues
 Only one input can be active at any
given time.
 If two inputs are active simultaneously,
the output produces an undefined
combination
 (for example, if D3 and D6 are 1 simultaneously,
the output of the encoder will be 111.

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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 Priority Encoder
 Multiple asserted inputs are allowed;
one has priority over all others.

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K-Maps

29
Circuit

30
8-3 Priority Encoder

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 Datasheets

 http://users.otenet.gr/~athsam/database.htm
 Some sample datasheets in the course site.

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