Ch3

DECF Instruction: DECF fileReg, d //Decrement the value in a file register by 1.

( fileReg: The file register

d = 0: Store the result in WREG,d = 1: Store the result back in the file register
(fileReg).)

DECFSZ Instruction: DECFSZ fileReg, d // Decrement the value in a file

register by 1, and skip the next instruction if the result is zero.)
·
 se
Test 1

:
D) when MOVWF 40H is executed

Test2

Q6)

Which phase(s) of an instruction cycle

The write cycle occurs during the execution phase of the What is the data memory location
instruction cycle.
accessing?
• During the execution phase, the instruction MOVWF Full Address = (BSR × 0x100) + 0x3F
0x3F, Banked writes the contents of the WREG Full Address = (02H × 0x100) + 0x3F =
(20H) into the specified memory location (0x3F in the
selected bank). 0x23F
• The timing diagram in Figure 1 represents the address
signals (A0-A11), the write enable signal, and the data
signals (D0-D7) during this phase as the data is transferred
to memory. What is the content of the data bus? (2 marks)
The content of the data bus (D0-D7) is the value stored in WREG,
which is 20H (as given in the question).
During the write operation, the value 20H is transferred from the
WREG to the destination memory location (0x23F).

D) what is the status after executing the

following two instructions:
MOVLW 0x8F
ADDLW 0x23

Address of R0:300H
what are the roles of the address of the first location in this user stack:302H
hardward stack in PIC18.Roles: What are the address modes of the instruction MOVEE RO,
Storing return addresses, PREINCO? Direct Addressing mode and Indirect addressing mode
automatic management, and Show the contents of FSRO Show the contents
interrupt handling. when "MOVLW OxFF" is of hardware stack
executing. 303H and stack pointer
Show the contents of when "MOVLW
hardware stack and stack OxOF" is
pointer when "MOVLW executing. Stack
OxFF" is pointer =2
executing.stack pointer = 1 stack[0002AH,0001
stack[00018H,empty] 8H,empty]

=
b) to propagate the possible carry to high
order addresses/ make possible
correction on the high order address

db D'0', D'1', D'8', D'27', D'64', D'125', D'216'

b)Based on Figure Q3, design a decoding circuit for the

address range 8000H to FFFFH. Assume that we use
Active High for decoding.
(3 marks)

c)Suppose that we only have memory chips with 16K

bytes capacity. How many memory chips are required to
implement the address range for 8000H to FFFFH?
(2 marks)

-2*(1/8+1/16)
 ANS
ORG 0x008
BTFSC INTCON0, INT0IF
B1)Do not know the receiver is ready/busy or not
Do not know the receiver gets the data or not
MAIN:
B2)ADD CLRF TRISD before BSF INTCON, INT10E
BSF TRISB,1 Change MOVFF PORTC, 00H to MOVFF PORTC, PORTD
SETF TRISC
BCF INTCON,INT10E
BCF INTCON,INT10F
BCF INTCON2,INTEDG0
BSF INTCON, GIE

A) 1MC= 1us, (7+3)x200 =2,000us or 2ms

b) call the delay function 100 times with a loop
MOVLW d'100'
MOVWF REGA
Here Call Delay
DECF REGA,F
BNZ Here
8-bit unsigned number representation 1. Write a program to add three packed BCD Write a program to add 7F9AH
determine the decimal value of the 8-bit pattern 0001 1101 in each representation: Show a simple code to (a) load value 11H into 1. Write a program to add three numbers (in locations 0-2) and save the to BC48H, and save the result
locations 0-5, and (b) add them together and place numbers (in locations 0-2) and
(a) 8-bit unsigned number representation save the result in file registers. result in file registers. starting at 40H.
the result in WREG as the values are added. Use
= 16 + 8 + 0 + 2 + 1 = 29 EQU to assign the names R0-R5 to locations 0-5.
(b) 8-bit 2’s complement representation H_byte EQU 0x20 H_byte EQU 0x20 BYTE_L EQU 0x40
29 R0 EQU 0 L_byte EQU 0x20 L_byte EQU 0x20 BYTE_H EQU 0x41
(c) BCD (Binary-Coded Decimal) code R1 EQU 1 BYTE_U EQU 0x42
13>9 R2 EQU 2 MOVLW 0 MOVLW 0 MOVLW 0x9A
Not valid BCD code R3 EQU 3 MOVWF H_byte MOVWF H_byte MOVWF BYTE_L
Given a 8 bit pattern 1001 1001, what is the decimal value R4 EQU 4 MOVF 0, W
MOVF 0, W MOVLW 0x7F
(a) 8-bit unsigned number representation R5 EQU 5 ADDWF 1, W
BNC N_1
ADDWF 1, W MOVWF BYTE_H
= 128 + 0 + 0 + 16 + 8 + 0 + 0 + 1 MOVLW 11H
MOVWF R0 INCF H_BYTE, F DAW MOVLW 0
= 153 N_1 BNC N_1 MOVWF BYTE_U
MOVWF R1
(a) 8 bit 2’s complement representation MOVWF R2 ADDWF 2, W INCF H_BYTE, F MOVLW 0x48
Binary: 1001 1001 MOVWF R3 BNC N_2 N_1 ADDWF BYTE_L,F
Step 1: Invert the bits → 0110 0110 MOVWF R4 INCF H_BYTE, F ADDWF 2, W MOVLW 0xBC
Step 2: Add 1 → 0110 0110 + 1 = 0110 0111 MOVWF R5 N_2 DAW ADDWFC BYTE_H,F
= 64 + 32 + 0 + 0 + 4 + 2 + 1 = 103 MOVLW 0H MOVWF L_BYTE BNC N_2 MOVLW 0x00
make it negative due to the MSB: -103 ADDWF R0, W INCF H_BYTE, F ADDWFC BYTE_U,F
(a) BCD code ADDWF R1, W N_2
99 ADDWF R2, W
MOVWF L_BYTE
ADDWF R3, W
Given two decimal numbers, A=-127 and B=-64,
ADDWF R4, W Write a program to add BCD 7795 to BCD Write a program to subtract 7F9A
a)Convert A and B into the 8-bit 2’s complement system format. ADDWF R5, W 9548 and save the result starting at 40H. from BC48H and save the result
Absolute value of A: 127
Binary (7 bits): 0111 1111
starting at 40H.
BYTE_L EQU 0x40
Invert the bits: 1000 0000 BYTE_H EQU 0x41
Add 1: 1000 0000 + 1 = 1000 0001 BYTE_U EQU 0x42 BYTE_L EQU 0x40
Absolute value of B: 64 MOVLW 0x95 BYTE_H EQU 0x41
Binary (7 bits): 0100 0000 MOVWF BYTE_L
Invert the bits: 1011 1111 MOVLW 0x48
MOVLW 0x77
Add 1: 1011 1111 + 1 = 1100 0000 MOVWF BYTE_H
MOVWF BYTE_L
(b) Perform A + B in the 8-bit 2’s complement system format MOVLW 0 MOVLW 0xBC
1000 0001 + 1100 0000->0100 0001=65(Result, ignoring carry beyond 8 bits) MOVWF BYTE_U MOVWF BYTE_H
expected -127 +(-64) =-191 overflow MOVLW 0x48
Add the following hex values. MOVLW 0x9A
ADDWF BYTE_L,W
(a) 2CH + 3FH 17. Find the time delay for the delay subroutine shown below if the system has PIC18
DAW SUBWF BYTE_L,F
Hex-> dec with a frequency of 4MHz
Find the time delay for the delay subroutine shown MOVWF BYTE_L MOVLW 0x7F
2 x 16 + 12 = 44
3 x 16 + 15 =63 Delay MOVLW d’200’ below if the system has PIC18 with a frequency of MOVLW 0x95 SUBWFB BYTE_H,F
MOVWF REGA 4MHz ADDWFC BYTE_H,W
44+63 =107 DAW Show how to perform 77x34 in the PIC18
BACK MOVLW d’100’
107/16=6 remainder 11 MOVWF REGB MOVLW d’200’ MOVWF BYTE_H
11 in hex is B. HERE NOP MOVWF REGA
MOVLW 0x0 MOVLW D'77'
result;6B(hex) DECF REGB, F BACK MOVLW d’100’ MULLW D'34'
MOVWF REGB
ADDWFC BYTE_U,W
(b) F34H + 5D6H BNZ HERE DAW ; The result will be in double register PRODH-
15 x 16^2 + 3 x 16^1 + 4 x 16^0 =3,892 DECF REGA, F HERE NOP PRODL
NOP MOVWF BYTE_U
5 x 16^2 + 13 x 16^1 + 6 x 16^0 =1494 BNZ BACK
Return DECF REGB, F
3892+1494=5386 Show how to perform 77/3 in the PIC18 Also learn
MC = 1µs BNZ HERE
5386/16^2 =21 remainder 10 DECF REGA, F
10/16 = 10 remainder A Roughly MOVF ARG1, W ;
HERE loop lasts (1+1+2)*100 – 1 = 399 instruction cycles. BNZ BACK NUM EQU 0x19
result: 150A(hex) MYQ EQU 0x20 MULWF ARG2 ; ARG1 * ARG2 ->
Overall delay = [399*200 + (1+1+1+2)*200-1+1+1+2 ] * 1µs
Regarding the data bus and address bus, which is unidirectional and which is Instruction cycle = 250 ns; ; PRODH:PRODL
REM EQU 0x21
bidirectional? Data bus is bidirectional, address is unidirectional. HERE loop lasts (1+1+1+2)*100 – 1 = 499
DENUM EQU D'3' How do you detect the OV flag in the PIC18? How do you
(9) Which register of the CPU holds the address of the instruction to be fetched? PC (Program Counter)instruction cycles.
10) Which section of the CPU is responsible for performing addition? ALU CLRF MYQ detect the C flags?
(11) List the three bus types present in every CPU. Address, control and data Write a program to get 8 bit data from MOVLW D'77'
PORTD and send it to PORTB and BOV and BNOV instructions - BC and BNC instructions
(12) Which register of the CPU holds the data for Arithmetic and Logic operations? Accumulator MOVWF NUM
PORT C. MOVLW DENUM Write a program to find the number of zeros in an
State the three main parts of a digital computer.
8-bit data item.
State the three main parts of a digital computer.CPU, memory, IO device AGAIN
Instruction Fetch: SETF TRISD ;Define PORTD as INCF MYQ,F
input MYREG EQU 0x20 ;Contains data
1) The CPU places the content of the program counter on the address bus in order to fetch an instruction SUBWF NUM,F
CLRF TRISB ;Define PORTB as COUNTER EQU 0x21
from memory, BC AGAIN
output RESULT EQU 0x22
2) The program counter is incremented so as to be ready to fetch the next instruction, DECF MYQ,F CLRF RESULT
3) After the data in the data bus is ready, the CPU places it (the instruction) in the instruction register ready CLRF TRISC ;Define PORTC as ADDWF NUM,F
output MOVLW 8
for decoding,
MOVFF PORTD, PORTB MOVFF NUM,REM MOVWF COUNTER
Instruction Decode:
MOVFF PORTD, PORTC AGAIN RRCF MYREG,F
The instruction decoder decodes the instruction to identify: Write a program to find the position of the first BC NEXT
i) the operation to be carried out, “1” in an 8-bit data item. The data is
Write a program to toggle bit 2 of INCF RESULT, F
ii) the address of the source operands and the results, PORTB and bit 5 of PORTB scanned form D0-D7. Give the result for NEXT DECF COUNTER,F
Instruction Execution: continuously without disturbing the 68H. BNZ AGAIN
1) Additional memory accesses may be conducted to obtain all the operands needed (if any), rest of the bits.
2) The specified operation will be performed, BCF TRISB, 2 ;Define PB2 as output MYREG EQU 0x20 Find the time delay for the following code shown
3) The results are placed according to the destination address so determined. Again, additional BCF TRISB, 5 ;Define PB5 as output COUNTER EQU 0x21 below if the system has PIC18 with a frequency of
memory access may be required (if any), BACK BTG PORTB, 2 POSITION EQU 0x22 4MHz
A programmer puts the first instruction at address 100H. What happens when the microcontroller is powered BTG PORTB, 5 CLRF POSITION MOVLW d’100’
BRA BACK MOVLW 8 MOVWF REGB
up?
MOVWF COUNTER HERE NOP
Ans:PC=0, CPU fetch the first instruction.and then executes it . Write a program to get the MOVLW 68H
1. Show the lowest and highest values (in hex) that the PIC18 program counter can take. status of RC3 and put it on DECF REGB, F
MOVWF MYREG
Ans:1F FFFFH RC4. AGAIN BNZ HERE
1. The design of PIC18 follows ____________ architecture. What are the properties of this architecture? BSF TRISC, 3 ;Define PC3 as RRCF MYREG,F (b) Write a subroutine that can generate a
Ans: Harvard Architecture. Program memory and Data Memory have their individual data and address buses. input BC OVER programmable delay. The input parameter is
BCF TRISC, 4 ;Define PC4 as passed by a fixed location. Describe how to use this
1. What are the widths of the address bus and data bus of PIC18 program memory? How many memory INCF POSITION, F
output DECF COUNTER,F routine.
locations can be addressed by the program memory address bus? BACK BTFSS PORTB, 3
Ans: Program memory (21 bit address bus and 16 bit data bus) BNZ AGAIN (a)
BRA BIT_L OVER
2. What are the widths of the address bus and data bus of PIC18 data memory? How many memory BSF PORTB, 4 (1+1+2)*100 – 1 + 1 +1 = 401 instruction cycles.
locations can be addressed by the data memory address bus?
Ans: Data memory (12 address bus and 8 bit data bus)
BRA BACK
BIT_L BCF PORTB, 4
1. Which of the following are (b)
3. Most instructions allocate only 8 bits to address the data memory, whereas the width of the address bus BRA BACK invalid uses of immediate delay NOP
of PIC18 data memory is more than 8 bits. How can these instructions uniquely specify where DECF local_var, F
address model? BNZ delay
operands and destination of an arithmetic/logic operation are located in the memory?Ans: Bank Write a program to add the
(a) MOVLW 0x24 (b) Return
unpacked BCD digits stored In main,
Which of the following is (are illegal?(a) MOVLW 500
in locations 0-5. Store the MOVLW MYREG, 0x30, local_var EQU 0
(b) MOVLW 50 (c) MOVLW 00 result in location 6. MOVLW 0x60 :
(d) MOVLW 255H (e) MOVLW 25H (f) MOVLW F5H Ans: b. MOVLW takes only one :
movlw constant
(g) MOVLW mybyte, 50H
MOVLW D’0’ operand which is an immediate movwf local_var
Ans (a), (d), (f) and (g)
8. Which of the following is (are illegal)? value. call delay
(a) ADDLW 500
ADDWF 0h, W 1. Identify the addressing model for each of the :
The delay is
(b) MOVLW 50 (c) MOVLW 00 DAW following:
(1+1+2)*input– 1 + 2 + 2 ms
(d) ADDLW 255H (e) MOVLW 0x12 (f) MOVLW 0F5H (a) MOVWF PORTB (b) MOVLW 0x50 (c)
(g) ADDWL 25H
ADDWF 1h, W MOVWF MYREG Write a program to copy FFH into RAM locations 50H to 6FH.
Ans (a) and (g) DAW (d) MOLW 0 (e) MOVFF MYREG, RAM_ADDR EQU 50H
YOUREG COUNT_REG EQU 0x20
Show a simple code to load value 15H into location 7, and then add to WREG five times and place the resultADDWF 2h, W (f) MOVWF YOUREG COUNT_VAL EQU 1FH
in WREG as the values are added. WREG should be zero before the addition starts. DAW a) Direct b) Immediate c) Direct d) Immediate e) MOVLW COUNT_VAL
MOVLW 15H Direct f) Direct MOVWF COUNT_REG
MOVWF 7H ADDWF 3h, W . Write a program to read the following message from LFSR 0,RAM_ADDR
MOVLW 0F MOVLW 0xFF
ADDWF 7H, W
DAW ROM and place
starting at 50:
it in data RAM
AGAIN MOVWF INDF0
ADDWF 7H, W ADDWF 4h, W ORG 0X600 INCF FSR0L,F
ADDWF 7H, W mydata: “1-800-999-9999”,0 DECF COUNT_REG,F
ADDWF 7H, W DAW Ans: BNZ AGAIN
ADDWF 7H, W ADDWF 5h, W RAM_ADDR EQU 50H Write a program to find y=x2+3x+5, where x
ORG 0000 is between 0 and 9.
What is the difference between MOVWF and MOVF instruction?
MOVWF copies the contents of WREG to a location in the file register. MOVF copies the contents of a DAW
MOVLW 0x00
MOVWF TBLPTRL
retlw 0000
location in the file register to WREG. MOVWF 6h MOVLW 0x6 SETF TRISB
MOVWF TBLPTRH CLRF TRISC
What is the difference between MOVFF and MOVWF? LFSR 0,RAM_ADDR NEXT MOVF PORTB, W
MOVWF copies the contents of WREG to a location in the file register. MOVFF copies the contents of a NEXT TBLRD*+ ANDLW 0x0F
location in the file register to another file register. MOVF TABLAT, W
CALL Y_TABLE
MOVWF is a two-byte instruction. MOVFF is four-byte instruction. BZ EXIT
MOVWF POSTINC0 MOVWF PORTC
1. Identify the addressing model for each of the following: BRA NEXT BRA NEXT
(a) MOVWF PORTB (b) MOVLW 0x50 (c) MOVWF MYREG EXIT BRA EXIT ;------- Y_TABLE SUBROUTINE
;----------MESSAGE Y_TABLE
(d) MOLW 0 (e) MOVFF MYREG, YOUREG ORG 0x600
(f) MOVWF YOUREG DB "1-800-999-9999",0
MULLW 0x2
a) Direct b) Immediate c) Direct d) Immediate e) Direct f) Direct END MOVF PRODL, W
ADDWF PCL,F
retlw D'5'
retlw D'8'
…
retlw D'85'
retlw D'104'
In a PIC18 system, the addresses of the status register & data
Assume that the AN0 and AN1 pins of a PIC18 running with a 4 MHz crystal oscillator are connected to a potentiometers. The voltage range of the potentiometer is
register of an input device are E00H & E01H, in data from 0V to 5V. The reference external sources Vref+=5V and Vref-=0 are used.
memory space, respectively. When bit 0 of the status
register is 1, the data to be input by CPU is ready. Both Write a program to measure the voltages applied to the AN0 and AN1 pins, convert them, and retrieved the conversion result and place it in RAM location 0-3.
status & data registers are 8-bits long. Write the instruction Let the minimum value of TAD = 1.6 ms and the minimum value of TACQ = 10 ms
sequences using to check the status register continuously
and input the data when data is ready. ADCON1= 0011 1011 = 0x3B

Main ORG 0x0000 TAD must be at least 1.6us. For fOSC = 4MHz or TOSC = 0.25us, the minimum possible TAD that can be chosen is 8TOSC or 2us. => fOSC/8 =>001
MOVLB 0xE0
TACQ must be at least 10µs. TAD = 2us. TACQ = 6 TAD =>011
MOVLW 0x01
Again CPFSEQ 0x00, 1 ADCON2=10 011 001 = 0x99
bra Again start
MOVF 0x01, w, 1 movlw 0x3B ; useAN2 and AN3 as reference voltages
movwf ADCON1 ; configure channel AN0-3 as analoginput
End movlw 0x99 ; select FOSC/8 as conversion clock,
movwf ADCON2 ; 6 TAD for acquisition time,
;right-justified
Assume fOSC = 4MHz, write a few instructions to configure PIC18F4520
ADC with the following requirements: movlw 0x01 ; select channel AN0 and enable A/D
movwf ADC converts the analog signal fed into Channel AN3. movwf ADCON0
b. Set AN0 to AN3 as analog inputs, other A/D port pins for digital I/O. bsf ADCON0,GO,A ; start A/D conversion
wait_con0
c. ADC result is left justified.
btfsc ADCON0,DONE,A ; wait until conversion is done
d. Select VDD and VSS as reference voltages. bra wait_con0
e. Select the minimum possible TAD movff ADRESH, 1 ; save conversion result
f. Select the minimum possible TACQ movff ADRESL, 0 ; "
g. Turn on ADC module
Do not start ADC yet movlw 0x05 ; select channel AN1 and enable A/D
TAD must be at least 0.7us and TACQ must be at least 1.4µs. movwf ADCON0
bsf ADCON0,GO,A ; start A/D conversion
Ans: TAD must be at least 0.7us. For fOSC = 4MHz or TOSC = 0.25us, wait_con1
the minimum possible TAD that can be chosen is 4TOSC or btfsc ADCON0,DONE,A ; wait until conversion is done
bra wait_con1
1us.
movff ADRESH, 3 ; save conversion result
TACQ must be at least 1.4µs. TAD = 1µs. TACQ >= 2 TAD movff ADRESL, 2 ; "

movlw b’00001101’ end

movwf ADCON0
movlw b’00001011’
movwf ADCON1
movlw b’00001100’
movwf ADCON2

Given two decimal numbers A = 39 and B = 87;

Convert A and B into 8-bit 2’s complement numbers and show the calculation of A-B.

A = 39 (decimal):
Convert to binary:

39(dec)= 00100111(Bin)
B = 87(decimal):
Convert to binary:
87 = 01010111

Step2:Negate B for subtraction

01010111->invert->10101000
Add 1 to inverted bits: -B = 10101001(2’s complment)

Perform A-B same as A + (-B):

00100111 + 10101001
= 1101 0000
the result indicate the result is negative
now convert to decimal
11010000->0010 1111(invert)
00101111+1 =00110000(plus1)
00110000 = 48 since the result is negative
A-B = -48

Given two decimal numbers A = 39 and B = 87;

Convert A and B into packed BCD codes and show the calculation of A + B;
39 -> 0011 1001(Packed BCD)
87-> 1000 0111(P BCD)

0011 1001 + 10000111

= 1100 0000
since 1100 is invalid in BCD, 0110 + 0110 = 0010 0000/01100010