4-Channel High Current LED Driver with

Adaptable Power Control

Data Sheet ADP8140
FEATURES TYPICAL APPLICATION CIRCUITS
Highly integrated feature set for a high brightness LED
driver solution with minimal external components VCC
4 current sink channels with an adjustable current from
125 μA to 500 mA
NTC
Analog and pulse-width modulation (PWM) dimming inputs
Analog and PWM LED current outputs
2% (maximum) matching between LED channels
5% (maximum) LED current accuracy
Operates from VIN of 3 V to 30 V; higher voltages easily ADP8140
accomplished with an external Zener diode VIN MIN

Operates with LED anode supply voltages up to 100 V dc REG VT

MODE DIM
Feedback output controls external power source for optimal
ENABLE EN SINK1
efficiency and safety FAULT FAULT SINK2
Multiple ADP8140 IC operation in parallel to control one FB_OUT SINK3
power supply COMP SINK4

Integrated error amplifier for secondary side control of ISET VO_SNS

EXPOSED PAD
isolated power supplies

10935-001
Easy connection of a temperature thermistor or light sensor
Provides robust protection of the entire system Figure 1. ADP8140 Used with Shunt Regulator
Power supply overvoltage protection
LED overtemperature protection
AGND VCC BST
LED short-circuit protection
FB VIN
LED open-circuit protection ADP2441 BUCK
REGULATOR
IC overtemperature protection COMP SW

Shorted ISET protection

EN PGND
Open ISET and EN protection
PGOOD FREQ SS
Standby mode for low current consumption
Fault indicator output ADP8140 VIN
Small, thermally enhanced, LFCSP package (4 mm × 4 mm)
VIN MIN
REG VT
APPLICATIONS
MODE DIM
High brightness LED lighting EN SINK1
Large format LED backlighting FAULT SINK2
FB_OUT SINK3
COMP SINK4
ISET VO_SNS 10935-039

EXPOSED PAD

Figure 2. ADP8140 Used with Buck

GENERAL DESCRIPTION
The ADP8140 provides high current control of up to four LED circuits, overvoltages, and LED open circuits. Multiple
drivers. Each driver can sink up to 500 mA. The sink current is ADP8140 ICs are easily connected in parallel to drive additional
programmed for all four drivers with one external resistor. LED strings or higher current LEDs. The ADP8140 is available
The device features a feedback output that controls an external in a small, thermally enhanced, lead frame chip scale package
power supply for optimal efficiency. The ADP8140 also protects (LFCSP).
the LEDs, power supply, and itself against thermal events, short
Rev. B Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADP8140 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 MODE Pin Operation................................................................ 13
Applications ....................................................................................... 1 Power Control Modes ................................................................ 13
Typical Application Circuits............................................................ 1 Dimming the LED Current ....................................................... 14
General Description ......................................................................... 1 Reducing the LED Current with the DIM Pin ....................... 15
Revision History ............................................................................... 2 Dimming LEDs with the VT Pin ............................................. 15
Specifications..................................................................................... 3 Fault Protections ......................................................................... 15
Absolute Maximum Ratings............................................................ 6 LED Open-Circuit and Short-Circuit Protection .................. 16
Maximum Temperature Ranges ................................................. 6 Die Temperature Protection ..................................................... 17
Thermal Resistance ...................................................................... 6 Using Multiple ADP8140 ICs ................................................... 17
ESD Caution .................................................................................. 6 Operating the ADP8140 from Higher Input Voltages .......... 18
Pin Configuration and Function Descriptions ............................. 7 Effect of LED VF Mismatch ....................................................... 18
Typical Performance Characteristics ............................................. 8 Managing the Power Dissipation of the ADP8140 ................ 19
Theory of Operation ...................................................................... 11 Layout Guidelines....................................................................... 19
Start-Up Sequence ...................................................................... 11 Ordering Options ....................................................................... 19
Current Sinks .............................................................................. 12 Outline Dimensions ....................................................................... 23
Power Control Operation .......................................................... 12 Ordering Guide .......................................................................... 23

REVISION HISTORY
9/2020—Rev. A to Rev. B
Changes to Figure 36 ...................................................................... 22

9/2018—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23

2/2015—Revision 0: Initial Version

Rev. B | Page 2 of 23
Data Sheet ADP8140

SPECIFICATIONS
VIN = 12 V, EN = DIM = VT = 3.0 V, MIN = MODE = 0 V. Typical values are at TJ = 25°C and are not guaranteed. Minimum and
maximum limits are guaranteed from TJ = −40°C to +125°C, unless otherwise noted.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Input Voltage
Operating Range VIN 3.0 30.0 V
Undervoltage Lockout VUVLO 2.85 2.95 V
Quiescent Current
During Standby IQ(STBY) EN = 0 V, VIN = 3.3 V to 30 V 200 μA
During Operation IQ(ACTIVE) EN = 3 V, VIN = 3.3 V to 30 V, RSET = 71.5 kΩ 4.1 4.5 mA
REG Output
Output Voltage VREG1 VIN = 3.3 V to 30 V, IREG = 1 mA 2.85 3.0 3.15 V
VREG2 VIN = 3 V, IREG = 1 mA 2.85 2.95 V
Source Current IREGMAX VIN = 3.3 V to 30 V 15 mA
Load Regulation VIN = 3.3 V to 30 V, IREG = 0.1 mA to 15 mA 0.75 mV/mA
FEEDBACK OUTPUT
FB_OUT Error Amplifier (EA) VEA(450) 430 450 476 mV
Accuracy
VEA(350) 324 350 380 mV
FB_OUT NMOS Pull-Down IFB_PD SINKx = 0 V, FB_OUT = 3 V 12.0 15.0 18.0 mA
Current
FB_OUT Stage Gain GFB Force 1.2 V and 1.3 V on COMP, measure FB_OUT 12500 17000 22000 μmho
current (FB_OUT = 12 V)
FB_OUT Fault Current IFB_FC Fault activated, FB_OUT = 30 V 0.04 1 μA
Amplifier Transconductance COMPGM 30 60 120 μmho
Amplifier Transconductance
Output
Source COMPSOURCE COMP pin output source current 110 μA
Sink COMPSINK COMP pin output sink current 1.5 mA
Resistance COMPRO 20 MΩ
Low Gain EA GBUFF Gain in buffer mode (MODE = 30.1 kΩ to GND) 3.6 3.9 4.2
Low Gain Bandwidth MODE = 30.1 kΩ to GND 100 kHz
ISET
Accuracy ILED_500 RSET = 5.11 kΩ, SINKx = 600 mV 475 500 525 mA
ILED_350 RSET = 7.32 kΩ, SINKx = 600 mV 332.5 350 367.5 mA
ILED_100 RSET = 25.5 kΩ, SINKx = 600 mV 95 100 105 mA
ILED_35 RSET = 71.5 kΩ, SINKx = 600 mV 33.0 35 37.5 mA
Shorted Current ISET = GND 500 570 620 mA
Open Current ISET = open 15 17 mA
CURRENT SINKS
Current Sink Headroom Voltage VHR_500 RSET = 5.11 kΩ, ILED = 95% × ILED_500 320 430 mV
at Maximum Current
VHR_350 RSET = 7.32 kΩ, ILED = 95% × ILED_350 210 324 mV
Current at 350 mV IHR_350 Maximum guaranteed current using the 350 mV 350 mA
reference option
Sink Matching Matching = (ISINK_MAX − ISINK_MIN)/(ISINK_MAX + ISINK_MIN) × 100
At 500 mA Current IMATCH500 0.2 2 %
At 350 mA Current IMATCH350 0.25 2 %
At 100 mA Current IMATCH100 0.25 2 %
At 35 mA Current IMATCH35 0.3 2 %

Rev. B | Page 3 of 23
ADP8140 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SINKx Leakage Current ISINK(LKG) SINKx pin = 4 V 8 12 μA
Channel Clamp Threshold
Low VCH_CLMP_LOW Threshold on SINKx to trigger VCH_CLMP_LOW, MIN pin = 7.4 7.75 8.1 V
GND
High VCH_CLMP_HIGH Threshold on SINKx to trigger VCH_CLMP_HIGH 14.5 15.1 15.7 V
Channel Clamp Current
Low ICLMP_LOW Channel pull-down current when SINKx > 315 350 385 mA
CHCLMP_LOW, RSET = 7.32 kΩ
High ICLMP_HIGH Channel pull-down current when SINKx > 430 510 600 mA
CHCLMP_HIGH
Channel Clamp Hysteresis VCH_CLMP_HYS Hysteresis after either channel clamp is triggered 1.2 V
Lowest SINKx Current Output current for DIM = 0 V and RSET = 10 kΩ (see 125 μA
Figure 15)
INPUT CONTROLS
Input Threshold (Low) VIL 0.6 V
Input Threshold (High) VIH 1.1 V
EN Input Resistance REN EN = 1.2 V 400 kΩ
MODE Pin Pull-Up Current IM 15 20 24 μA
MODE Threshold 1, 30.1 kΩ VM1 Threshold for increasing mode voltage to enter dc 0.35 0.4 0.45 V
buffer operation
MODE Threshold 2, 52.3 kΩ VM2 Threshold for increasing mode voltage to enter 0.75 0.8 0.85 V
PWM buffer operation
MODE Threshold 3 VM3 Threshold for increasing mode voltage to enter 1.25 1.3 1.35 V
PWM EA operation
LED SCALING CONTROLS
DIM and VT Limit Voltage VTLIMIT VT (and DIM if MODE = GND) voltage to produce 1.9 2.0 2.1 V
100% output current
Dimming Accuracy ILED_DIM1 ILED_DIM1/ILED_100, VT = 1 V, MIN = 0 V, RSET = 25.5 kΩ 48 50 52 %
ILED_DIM2 ILED_DIM2/ILED_100, DIM = 0.2 V, MODE = GND, RSET = 9.4 10 10.4 %
25.5 kΩ
ILED_DIM3 ILED_DIM3/ILED_100, DIM = 50%,140 Hz, MODE = REG, 48 50 52 %
RSET = 25.5 kΩ
VT Pull-Up Current Source 0.6 1 μA
DIM Pin Frequency Range MODE = REG 0.14 40 kHz
MIN Comparator Hysteresis VMIN_HYS 55 mV
MIN Pin PWM Mode VMIN_PWM Voltage on MIN pin at which VT changes from 2.2 2.3 2.4 V
Threshold scaling LED current to pulsing LED current
PWM Delay and Rise/Fall Time Delay from VT low to high (or high to low) to LED 20 μs
current low to high (or high to low), MIN = REG
THERMAL FOLDBACK
(INTERNAL)
Thermal Foldback Threshold TFBTHRES 135 °C
Thermal Shutdown Threshold TSDTHRES 150 °C
Thermal Shutdown Hysteresis TSDHYS 20 °C
FAULT DETECTION
FAULT Threshold
A
E

A VFAULT_TH Threshold for FAULT comparator

A
E

A 1.14 1.2 1.26 V

FAULT Hysteresis
A
E

A VFAULT_HYS Hysteresis for FAULT comparator

A
E

A 100 mV
FAULT Filter
A
E

A tFAULT VO_SNS and FAULT shutdown noise filter

A
E

A 10 μs
FAULT Pull-Down Resistance
A
E

A FAULTPD
A
E

A Fault activated 7 15 20 Ω
VO_SNS
Threshold VVO_SNS_TH Threshold for VO_SNS comparator 1.176 1.2 1.224 V
Hysteresis VVO_SNS_HYS Hysteresis for VO_SNS comparator 50 mV
Leakage Current IVO_SNS 50 nA
Open SINKx Fault Threshold VSFD_OPEN SINKx pin voltage threshold to remove a sink from 80 mV
the feedback loop after a VOUT_OVP fault
Rev. B | Page 4 of 23
Data Sheet ADP8140
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Channel Overvoltage VCH_OVP Threshold on SINKx to trigger CH_OVP fault 5.3 5.7 6.1 V
Threshold
Channel Overvoltage VCH_OVP_HYS Hysteresis after VCH_OVP is triggered 1.2 V
Hysteresis
Short SINKx Fault Threshold VSFD_SHORT SINKx pin voltage threshold to remove a sink from 525 mV
the feedback loop after a CH_OVP fault

Rev. B | Page 5 of 23
ADP8140 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. MAXIMUM TEMPERATURE RANGES
Parameter Rating The maximum operating junction temperature (TJ(MAX))
VIN, FB_OUT to GND −0.3 V to +31 V supersedes the maximum operating ambient temperature
SINKx to GND −0.3 V to +21 V (TA(MAX)). Therefore, in situations where the ADP8140 is
MODE, COMP, REG, MIN, DIM, VT, ISET to −0.3 V to +3.6 V exposed to poor thermal resistance and a high power dissipa-
GND tion (PD), the maximum ambient temperature may need to be
EN, FAULT, VO_SNS to GND
A
E

A −0.3 V to +6.0 V derated. In these cases, the ambient temperature maximum can
Operating Ambient Temperature Range –40°C to +105°C1 be calculated with the following equation:
Operating Junction Temperature Range –40°C to +125°C TA(MAX) = TJ(MAX) − (θJA × PD(MAX))
Maximum Junction Temperature 150°C
Storage Temperature Range –45°C to +150°C THERMAL RESISTANCE
Soldering Conditions JEDEC J-STD-020 θJA (junction to air) is specified for the worst-case conditions,
ESD (Electrostatic Discharge) that is, a device soldered in a circuit board for surface-mount
Human Body Model (HBM) ±1.5 kV packages. The θJA, θJB (junction to board), and θJC (junction to
Charged Device Model (CDM) ±500 V case) are determined according to JESD51-9 on a 4-layer
1
printed circuit board (PCB) with natural convection cooling.
The maximum operating junction temperature (TJ(MAX)) supersedes the
maximum operating ambient temperature (TA(MAX)). See the Maximum The LFCSP exposed pad must be soldered to GND.
Temperature Ranges section for more information.
Table 3. Thermal Resistance
Stresses at or above those listed under Absolute Maximum
Package Type θJA θJB θJC Unit
Ratings may cause permanent damage to the product. This is a
16-Lead LFCSP 33.2 12.4 2.4 °C/W
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational ESD CAUTION
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all voltages are
referenced to GND.

Rev. B | Page 6 of 23
Data Sheet ADP8140

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1 INDICATOR
(LASER MARKING)

VIN 1 16 MIN
REG 2 15 VT
MODE 3 14 DIM
EN 4
ADP8140 13 SINK1
EXPOSED PAD
FAULT 5 (GND) 12 SINK2
FB_OUT 6 11 SINK3
COMP 7 10 SINK4

10935-003
ISET 8 9 VO_SNS

TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD OF THE LFCSP TO GROUND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 VIN Supply Voltage Input (3.0 V to 30 V).
2 REG Regulated 3.0 V (Typical) Source. Connect a 1.0 μF (or greater) capacitor from REG to ground.
3 MODE Operation Mode. If MODE is connected to ground, the device is placed in dc EA operation. If MODE is connected to
REG, the device is placed in PWM EA operation. If MODE is connected via a 30.1 kΩ resistor to ground, the device is
placed in dc low gain buffer operation. If MODE is connected via a 52.3 kΩ resistor to ground, the device is placed
in PWM low gain buffer operation. The MODE pin is read only once at power-up (when VIN exceeds 3 V). Any
changes to the MODE pin after applying power are ignored. See the MODE Pin Operation section for more
information.
4 EN Enable Input. Pull high (above VIH(MIN)) to enable the device. EN is internally pulled low with a 400 kΩ (typical)
resistor.
5 FAULT
A
E

Fault Output. This pin must be connected to an external pull-up resistor. If using multiple ADP8140 ICs in parallel,
all FAULT pins must be connected together.
A
E

6 FB_OUT Feedback Output. The FB_OUT pin is a control signal for the external power stage. The action of this pin depends
on the MODE setting.
7 COMP Compensation Pin for EA. The COMP pin is a control signal for the external power stage. COMP is a dual function
pin. The action of this pin depends on the MODE setting.
8 ISET Output Current Setting. Connect a resistor to ground to set the output current. If left floating, the current sinks are
set to 15 mA.
9 VO_SNS Overvoltage Protection Sensing Input. Connect the VO_SNS pin through a resistor divider to the top of the LED
strings, or connect it to ground to disable overvoltage sensing.
10 SINK4 Current Sink for LED Channel 4.
11 SINK3 Current Sink for LED Channel 3.
12 SINK2 Current Sink for LED Channel 2.
13 SINK1 Current Sink for LED Channel 1.
14 DIM Dim Input. The DIM pin scales the LED current from the PWM signal or dc voltage. The action of this pin depends
on the MODE setting.
15 VT Voltage Threshold. VT is a dual function pin. If MIN < 2.2 V at startup, VT is an analog current reduction pin. A
voltage on VT scales the LED current. If MIN is connected to REG at startup, a PWM signal applied to VT pulses the
LED current.
16 MIN Minimum Voltage Threshold. If MIN < 2.2 V at startup, the MIN voltage sets the minimum voltage threshold for the
VT pin. VT voltages below the MIN voltage shuts down the power stage. If MIN is connected to REG at startup, a
PWM signal applied to VT pulses the LED current.
EPAD (GND) Exposed Pad (Ground). Connect the exposed pad of the LFCSP to ground.

Rev. B | Page 7 of 23
ADP8140 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12 V, EN = DIM = VT = 3.0 V, MIN = MODE = 0 V, VSINKx = 450 mV, TA = 25°C, unless otherwise noted.
4.5

4.0 500 –40°C

+25°C
–40°C +125°C
3.5
+25°C 400
3.0 +85°C
+125°C

ISINK (mA)
2.5 300
IQ (mA)

2.0
200
1.5

1.0
100
0.5
10935-004

0 0

10935-007
0 5 10 15 20 25 30 35 0.01 0.1 1
VIN (V) VSINK (V)

Figure 4. Typical Operating Current vs. VIN, EN = 3 V, RSET = 71.5 kΩ Figure 7. Typical Sink Current vs. Sink Voltage, RSET = 5.11 kΩ

400
4.9
–40°C
+25°C 350 –40°C
+25°C
4.7 +85°C
+85°C
+125°C 300 +125°C
4.5
250
ISINK (mA)
IQ (mA)

4.3
200

4.1
150

3.9
100

3.7 50
10935-005

3.5

10935-008
0
5 10 20 40 0.01 0.1 1
RSET (kΩ) VSINK (V)

Figure 5. Typical Operating Current vs. RSET Figure 8. Typical Sink Current vs. Sink Voltage, RSET = 7.32 kΩ

300 120

–40°C
250 100 +25°C
+85°C
+125°C

200 80
IQ (STBY) (µA)

ISINK (mA)

150 60

100 40

IQ –40°C
IQ +25°C
50 20
IQ +85°C
IQ +125°C

0
10935-009

0
10935-006

0 5 10 15 20 25 30 0.01 0.1 1
VIN (V) VSINK (V)

Figure 6. Typical Standby Current vs. VIN, EN = 0 V Figure 9. Typical Sink Current vs. Sink Voltage, RSET = 25.5 kΩ

Rev. B | Page 8 of 23
Data Sheet ADP8140
1.0 3.20
–40°C
+25°C
–40°C 3.15
+85°C
+25°C
0.8 +125°C
+125°C
3.10
ISINK MATCHING (%)

3.05
0.6

VREG (V)
3.00

0.4 2.95

2.90
0.2
2.85

10935-013
0 2.80

10935-010
0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 30
VSINK (V) VIN (V)

Figure 10. Typical Sink Current Matching vs. Sink Voltage, RSET = 5.11 kΩ Figure 13. REG Voltage vs. Input Voltage

1.0 500
–40°C
450
–40°C +25°C
+25°C 400 +85°C
0.8
+85°C +125°C
+125°C 350
ISINK MATCHING (%)

0.6 300
ISINK (mA)
250

0.4 200

150

0.2 100

10935-014
50

0 0
10935-011

0.3 0.5 0.7 0.9 5 15 25 35 45 55 65 75

VSINK (V) RSET (kΩ)

Figure 11. Typical Sink Current Matching vs. Sink Voltage, RSET = 7.32 kΩ Figure 14. Sink Current vs. RSET (DIM = 3 V)

1.0 300
–40°C
+25°C
+85°C 250
0.8
+125°C
ISINK MATCHING (%)

200
0.6
ISINK (uA)

150

0.4
100
–40°C
0.2 +25°C
50
+85°C
10935-012

+125°C
0
10935-015

0
0.15 0.35 0.55 0.75 0.95 5 10 20 40 80
VSINK (V) RSET (kΩ)

Figure 12. Typical Sink Current Matching vs. Sink Voltage, RSET = 25.5 kΩ Figure 15. Sink Current vs. RSET (DIM = 0 V)

Rev. B | Page 9 of 23
ADP8140 Data Sheet
100

–40°C VT
+25°C
OF FULL-SCALE CURRENT (%)

80 +85°C
+125°C
ISINK AS A PERCENT

1
60

ISINK
40

20
4

10935-018
0

10935-016
0 0.5 1.0 1.5 2.0 2.5 3.0 CH1 1V CH4 100mA 1.0ms
DIM OR VT VOLTAGE (V)

Figure 16. Typical Sink Current vs. DIM or VT Voltage (MODE = 0, MIN = 0 V) Figure 18. Typical Sink Current Waveforms with PWM on VT Pin (MIN = 3 V)

100

90 EN
–40°C
+25°C
80 1
AVERAGE ISINK AS A PERCENT

+85°C
+125°C FAULT
70
OF MAX CURRENT (%)

2
60

50

40 COMP

3
30
ISINK
20
4
10935-017

10

10935-019
0
CH1 2V CH2 2V CH3 1V CH4 200mA 2.00ms
0 10 20 30 40 50 60 70 80 90 100
VT DUTY CYCLE (%)

Figure 17. Typical Average Sink Current vs. VT Duty Cycle Figure 19. Start-Up Sequence (See Figure 1 Setup)
(MIN = 3 V, VT Frequency = 120 Hz)

Rev. B | Page 10 of 23
Data Sheet ADP8140

THEORY OF OPERATION
The ADP8140 provides high current control of up to four LED needed. In this operation, with EN low, the ADP8140 consumes
channels. Each driver can sink up to 500 mA. One external no more than 200 μA (typical). A 400 kΩ (typical) resistor from
resistor programs the sink current for all four channels. The EN to GND ensures that the ADP8140 is shut down in the
device features a feedback output that controls an external event of an open connection on the EN pin.
power supply for optimal efficiency. The ADP8140 also protects When EN also goes high, the power stage starts up and the
the LEDs, power supply, and itself against thermal events, short current sinks are enabled. There is an approximate 8 ms delay
circuits, and LED open circuits. Multiple ADP8140 ICs are after EN goes high. When the sinks are enabled, the FAULT pin A
E

easily connected in parallel to drive additional LED strings or

is released and the COMP and FB_OUT pins begin their
higher current LEDs.
normal regulation. When EN goes low, the SINKx pins are left
START-UP SEQUENCE on for another 100 μs to discharge any voltage from the power
To start the ADP8140, VIN must be applied in excess of the stage output. The device then enters low current consumption
UVLO threshold and the EN pin must be high. However, even operation.
with EN low, the REG pin produces a constant 3.0 V (typical)
on its output. REG can be used as a low current supply, as

VOUT

REG SINK1 SINK2 SINK3 SINK4 COMP

FB_OUT
VT VEA(REF)
SCALE
MIN MIN
NTC AND
MIN MAX
ID1 MAX

MIN
IM 5.7V
ID2
MODE
DIM SINK SHUTDOWN
CONTROL CONTROL
DIM
ID3
REDUCE CURRENT
WHEN DIE TEMP CH_OVP
> 135°C ID4
DIE TEMP 8V/15V
SENSE
ISET SINKx < 550mV? NOISE
IF SO, REMOVE FILTER
SINK EN FROM FB LOOP
10 µs
EN
RESET
ALL FAULTS
400kΩ

UVLO REG
VIN 3.0V TO 30V
ISET SHORT 1.2V
CIN
TSD
VREG_OK FAULT

VT < MIN
REG 3.0V
VOUT
SINKx < 75mV?
VO_SNS IF SO, REMOVE
NOISE FILTER FROM FB LOOP GND
VOUT_OVP (EXPOSED PAD)
6V 10 µs
1.2V
10935-022

16-LEAD EXPOSED PAD THERMALLY ENHANCED PACKAGE

Figure 20. Detailed Block Diagram

Rev. B | Page 11 of 23
ADP8140 Data Sheet

VIN VUVLO
UVLO

3.0V
REG

EN VREG OK AND UVLO OK AND EN HIGH

SHUTDOWN SHUTDOWN

SINK_EN ~8ms 100µs

(INTERNAL)

DETERMINE MODE STATE

MODE_STATE
DETERMINE (ONE OF 4 STATES) UNTIL REG OR VIN POWERS DOWN
(INTERNAL)

FAULT
(EXT RESISTOR
PULL-UP)

COMP
(EA CONFIG)

FB_OUT
(EA CONFIG)

10935-023
COMP
(BUFFER CONFIG)

Figure 21. Start-Up Timing and Signals

CURRENT SINKS per sink to 570 mA (typical) and shuts down the power stage
(FAULT goes low and FB_OUT and COMP are disabled).
E

The ADP8140 contains four internal current sinks. Each A A

current sink is capable of delivering 125 μA to 500 mA. To Each current sink has a maximum rated voltage of 20 V.
ensure accurate regulation, the voltage on the current sinks However, the maximum output voltage driving all the current
must be greater than the maximum headroom voltage given in sinks, through the LEDs, is allowed to exceed 20 V. The LEDs
Table 1. For additional information on the headroom voltage, drop enough voltage so that the SINKx voltage remains close to
see Figure 7 to Figure 9. All current sinks have their maximum the FB_OUT EA accuracy value, VEA(REF) (where REF is the
current set by the external resistor, RSET. To determine the value reference voltage). Because the ADP8140 controls the power
of RSET, use Equation 1. A graph of sink current vs. RSET is shown stage, the voltage is not present when off or during a fault.
in Figure 14. Therefore, the ADP8140 can be safely used in conjunction with
2560 power supplies that produce over 100 V for their output.
RSET (kΩ)  (1)
I SINK (mA) POWER CONTROL OPERATION
Multiple sinks can be combined together for higher currents per The ADP8140 controls a power stage with its COMP and
LED string. For example, two sinks can be shorted together to FB_OUT pins. The power stage allows the IC to optimize the
drive two strings of LEDs, each at up to 1 A, or four sinks efficiency and protection of the LEDs. The ADP8140 operates
combined to drive one string of LEDs at up to 2.0 A. in two power control modes: error amplifier and low gain
buffer. The MODE pin is used to select the power control mode.
A resistor must always be connected to the ISET pin. However,
in the event that ISET is accidentally left open, the ADP8140
defaults to a typical current of 15 mA (typical) per sink. If ISET
is accidentally shorted to GND, the ADP8140 limits the current

Rev. B | Page 12 of 23
Data Sheet ADP8140
MODE PIN OPERATION The FB_OUT pin outputs a current, which indicates power
The MODE pin is used to program one of four possible modes control. A higher FB_OUT sink current indicates that more
of operation. The condition of the MODE pin affects the DIM power is required to the LEDs. A lower FB_OUT sink current
pin input (see the Reducing the LED Current with the DIM Pin indicates that less power is required for the LEDs. This
section) and the power control mode (see Power Control Modes operation makes the FB_OUT ideal for any power control
section). The MODE pin state is read at power-up only, when application that does not normally have an error amplifier. The
VIN crosses the UVLO threshold. After this point, the MODE two primary applications for this are as follows:
pin voltage is 0 V. The MODE status cannot change after power-up.  Controlling an optocoupler on the secondary side of an
isolated power supply
Table 5. Modes of Operation Programmed by the MODE Pin
 Controlling a PMOS transistor to regulate power in a fixed
MODE Connection DIM Pin Mode Power Control output voltage supply.
GND Analog voltage Error amplifier
30.1 kΩ to GND Analog voltage Low gain buffer Depending on the power stage used, an RC network must be
52.3 kΩ to GND PWM signal Low gain buffer connected to the COMP pin. The COMP pin connects to the
REG PWM signal Error amplifier output of the FB_OUT transconductance amplifier. To select
the COMP resistor and capacitor values, a free simulation tool,
POWER CONTROL MODES ADIsimPE, is available at: www.analog.com/ADIsimPE.
Error Amplifier Power Control
Using this tool, and the included ADP8140 circuit model, the
In the error amplifier power control mode, the ADP8140 loop control and stability can be easily simulated and adjusted
applies the minimum voltage of the four current sinks to the for different setups.
inverting input of an internal error amplifier. The output of this
error amplifier connects to the FB_OUT inverting buffer.

SINK1 SINK2 SINK3 SINK4 COMP

FB_OUT
VEA(REF)
MIN MIN
AND
MAX
ID1 MAX

ID2 5.7V

SINK SHUTDOWN
CONTROL
ID3

CH_OVP
ID4
8V/15V
10935-024

SINK_EN

Figure 22. Error Amplifier Power Control

Rev. B | Page 13 of 23
ADP8140 Data Sheet
Low Gain Buffer Power Control Set the value of R1 to be small enough so that the internal
In the low gain buffer power control mode, the ADP8140 250 kΩ pull-down resistance on the COMP pin does not affect
multiplies the minimum voltage of the four current sinks by the total resistance. For example, if R1 = 10 kΩ, VHR = 325 mV,
GBUFF (3.9 typical; see Table 1) and outputs it to the COMP pin. and FB_REF = 600 mV, then
This mode allows the ADP8140 to easily control nearly any 3.9  0.325 
switched mode power supply (SMPS) control IC, such as a buck R2  10 kΩ    1  11.1 kΩ
 0.6 
regulator or boost controller. Common examples are shown in
Figure 32 to Figure 36. Next, select R3 to set the maximum voltage applied to the SMPS
FB input.
In this mode, the COMP pin is connected to the feedback (FB)
input of an SMPS controller. The FB_OUT pin can be left VREG  R1
R3   R1  R2
floating or connected to GND. Do not tie it to COMP or any FBMAX
other pin. Connect the FAULT pin to the EN signal of the SMPS
E

A A

where FBMAX is the maximum voltage desired on the SMPS FB

IC. This connection ensures that the power delivery immediately input. Therefore, if FBMAX = 720 mV,
shuts down in the event of a fault.
3 V  10 kΩ
The values of R1, R2, and R3 program the minimum headroom R3   10 kΩ  11.1 k  20.6 kΩ
voltage on the SINKx pins and set the maximum voltage that
0.720
the SMPS FB input receives. A spreadsheet is available at Ensure that FBMAX is sufficiently higher than the maximum
www.analog.com/ADP8140 to assist in these calculations. FB_REF operating point. Some extra margin is beneficial.
Otherwise, to find the values start with the following equation: DIMMING THE LED CURRENT
 3.9  VHR  The ADP8140 offers multiple methods of dimming. The
R2  R1    1
 FB _ REF  dimming input can be either an analog voltage or a PWM
signal. The LED output current can be either scaled (dc
where:
dimming) or pulsed on and off in response to the PWM input
FB_REF is the internal error amplifier reference voltage of the
signal. The two dimming pins, DIM and VT, provides different
SMPS IC. This is typically 600 mV or 1.2 V. However, it does
functions, but both pins can be used for dimming simultaneously,
vary for different ICs; therefore, consult the data sheet of that IC.
which provides enormous flexibility in controlling the LED
VHR is the minimum headroom voltage that the ADP8140
current.
current sinks need (see Figure 7 to Figure 9). This value varies
based on the maximum sink current that is programmed on the
ISET pin.

VREG
SINK1 SINK2 SINK3 SINK4
R3 600mV
R2
COMP FB
MIN MIN 250kΩ
AND 4× R1
MAX
ID1

OPEN-DRAIN
BUFFER
ID2
SINK BUCK OR BOOST IC
CONTROL
ID3

ID4
10935-025

8V/15V
ADP8140

Figure 23. Low Gain Buffer Power Control

Rev. B | Page 14 of 23
Data Sheet ADP8140
REDUCING THE LED CURRENT WITH THE DIM PIN current goes to the value dictated by the ISET and DIM pins.
The DIM pin scales the output current when either an analog If the PWM input is low, the current becomes the minimum
voltage or a PWM signal is applied to it. The response of the current as defined in Figure 15. This small current allows the
ADP8140 to the DIM pin depends on the condition of the LEDs to be slightly biased and minimizes the voltage difference
MODE pin. between the off and on states, which greatly reduces the
response time of the power delivery loop.
If the MODE pin is connected to GND or a 30.1 kΩ resistor at
startup, the DIM pin functions as an analog voltage input. As In this mode, the 7.75 V SINKx clamp is disabled. When the
such, a DIM voltage of 2 V or greater does not impact the output clamp is disabled, the voltages on the SINKx pins rise as high as
current. A DIM voltage of 0 V reduces the output current to as 15.1 V (typical) during the LED off time.
low as 125 μA (see Figure 15). Any DIM voltage between 0 V If MIN < 2.2 V, the voltage on the VT pin linearly scales the
and 2 V linearly scales the output current. LED current. VT voltages greater than 2 V (typical) produce
100% of the programmed ISET current. When VT is less than
2 V, the output current is reduced 1% per 20 mV. If the voltage
on the VT pin is below the voltage on the MIN pin, the power
MODE supply to the LEDs is disabled. If the VT pin voltage rises above
MODE = GND ANALOG CONTROL
the MIN threshold, plus some hysteresis, the power supply is
100%
reenabled. If both the VT pin and the DIM pin are used for
OUTPUT(%)
analog dimming, the pin that gives the lower LED current is
DIM 2V
DIM (V) SCALE
used to set the LED current.
10935-026

To implement thermal protection of the LEDs, the VT pin is

connected to an external negative temperature coefficient
Figure 24. Reducing the Output Current by Applying an Analog Voltage to
the DIM Pin (NTC) resistor. This NTC resistor is typically placed on the LED
heat sink. Selecting the value of the NTC and the resistor in the
If MODE is connected to REG or to a 52.3 kΩ resistor at
network shapes the slope of the VT voltage in response to the
startup, a PWM duty cycle applied to the DIM pin is internally
LED temperature. A resistor divider on the MIN pin sets the
filtered and used to scale the output currents. Set the DIM pin
level at which the power stage (FB_OUT and COMP) are
frequency between 140 Hz and 40 kHz. A lower frequency
disabled.
PWM signal gives the ADP8140 more information about the
applied duty cycle and leads to better resolution of the duty
cycle, which translates into smaller LED current step sizes on VREG

the current sink digital-to-analog converters (DACs). VT

NTC 100%
OUTPUT(%)
VREG
MIN 2V
MODE MIN
MODE = VREG SCALE PWM VT (V)

10935-028
SCALE
100%
OUTPUT(%)
Figure 26. Using an External NTC to Implement LED Thermal Protection
DIM 100%
DIM DUTY CYCLE (%) SCALE FAULT PROTECTIONS
10935-027

To ensure the safety of the LEDs, the ADP8140 IC, and the
Figure 25. Reducing the Average Output Current by Pulse Width Modulating power source, the ADP8140 includes a comprehensive array of
the Current Sinks with the DIM Pin
detection and protection features.
When DIM = 0 V, or 0% duty cycle, the minimum output current
 Power supply overvoltage protection
is a function of the programmed RSET value. This minimum
 LED overtemperature protection
value varies between 125 μA and 250 μA, depending on the RSET
 LED short-circuit protection
value. The typical value as a function of RSET is shown in Figure 15
of the Typical Performance Characteristics section.  LED open-circuit protection
 IC overtemperature protection
DIMMING LEDS WITH THE VT PIN  Shorted ISET protection
The VT pin has two modes of operation, depending on the  Open ISET and EN protection
configuration of the MIN pin.
These features are summarized in the flowchart shown in
If MIN is connected to REG at startup, a PWM input to the VT Figure 27.
pin pulses the LED current sinks. If the PWM input is high, the

Rev. B | Page 15 of 23
ADP8140 Data Sheet
DIE TEMP PROTECTION

FAULT DETECTION NO SCALE ILED DIE TEMP

DOWN > 150°C
SHUTDOWN YES
FAULT>1.2V
TURN POWER (10µs NOISE
STAGE OFF FILTER)
(LEAVE ALL YES
YES NO
SINKS ON) EN = LOW
NO SET
EN = HIGH FAULT
YES FAULT>1.1V DIE TEMP LOW
(10µs NOISE NO > 135°C
FILTER)
DIE TEMP
> 130°C
VT PROTECTION NO
ACTIVE YES

YES VT < MIN

(10µs NOISE NO
SET NO YES
FILTER)
VO_SNS > 1.2V VOUT OVP
FAULT
LOW (10µs NOISE
NO FILTER)
YES
ANY SINK YES
VT < MIN+ < 75mV?
VMIN (HYS) NO MAX(CHx)
NO > 5.5V? REMOVE
YES SINKx FROM
YES NO NO MIN CIRCUIT
MAX(CHx) NO
> 7.5V? YES ANY
ACTIVE CHx VO_SNS
< 550mV? < 1.15V
RSET NO
YES YES
ISET < 4.5kΩ SET
PROTECTION MAX(CHx) REMOVE FAULT
SET ALL SINKS TO < 4.5V SINKx FROM LOW
FULL ISET CURRENT MIN CIRCUIT
YES
SET
FAULT YES MAX(CHx) CHANNEL
LOW > 15V SET OVERVOLTAGE
FAULT PROTECTION
MAX(CHx) YES LOW
< 13.8V?

SET ALL SINKS

TO 500mA
CHANNEL
SET
CLAMPS
FAULT
LOW

10935-029
Figure 27. Fault Flowchart

LED OPEN-CIRCUIT AND SHORT-CIRCUIT 1.15 V (typical), the FB_OUT function resumes its normal
PROTECTION operation and FAULT goes high.
E

A A

An LED open-circuit fault can result from a bad solder Alternatively, the output voltage may not rise high enough to
connection or damaged LED. An open LED string results in the trigger the VO_SNS pin, but it may rise high enough to cause
current sink headroom falling to a very low level. The feedback one of the SINKx pins to exceed 5.7 V (typical), or a shorted
loop naturally interprets this as a request for more power. This LED may cause the SINKx pins to exceed this level. To prevent
can quickly lead to a case where the output voltage is too high. excessive power dissipation and damage to the IC, when a
However, on the ADP8140, any abnormally high output voltage SINKx pin rises above 5.7 V (typical), a channel overvoltage
is detected by the VO_SNS pin and the SINKx pins. fault (CH_OVP) is declared. During a CH_OVP fault, any sinks
The VO_SNS pin senses the output voltage of the power supply with a voltage less than 525 mV (typical) are removed from the
through an external resistor divider. VO_SNS is then compared FB_OUT path. Then the FB_OUT pull-down NMOS is
to an internal threshold (1.2 V typical). If the output voltage released, causing the power stage to shut down. The LED
rises such that the voltage of the VO_SNS pin is greater than current sinks are left enabled during this event. When the
1.2 V, an output overvoltage fault (VOUT_OVP) is declared. SINKx voltage drops to 4.5 V (typical), the FB_OUT function
During a VOUT_OVP fault, any sinks with a voltage less than resumes its normal operation.
80 mV (typical) are removed from the FB_OUT path. Then the Continued output overvoltage operation degrades efficiency
FB_OUT pull-down NMOS is released and FAULT goes low, A
E

A
and can affect the lifetime of passive components. Therefore,
causing the power stage to shut down. The LED current sinks when an overvoltage condition is detected (either VOUT_OVP
are left enabled during this event. When VO_SNS drops to or CH_OVP), then any open LED current sinks are identified
and removed from the feedback loop. But the sinks are always
Rev. B | Page 16 of 23
Data Sheet ADP8140
left enabled, so that they can regulate the current if the open- shuts down the power stage with COMP, FB_OUT, and FAULT. A
E

circuit or short-circuit LED condition is removed. Bringing EN When the temperature drops below 130°C (typical), the
or VIN low and then high again restores all sinks to the ADP8140 restarts the power stage. If the fault or high power
feedback loop. dissipation persists, the sequence repeats.
VO_SNS can also be used to monitor the input voltage. When USING MULTIPLE ADP8140 ICS
connected to the input voltage through a resistor divider, the
Multiple ADP8140 ICs can be combined in parallel to control
ADP8140 shuts down and disables any power stages if the
the same supply. This combination is advantageous to control
supply input voltage rises too high. This shutdown can help to
more than four strings of LEDs or to drive higher currents. For
protect the LEDs and power stage.
example, using two ADP8140 ICs, four LED strings can be
DIE TEMPERATURE PROTECTION driven at 1 A each, or two strings can be driven at 2 A each.
Significant voltage mismatch between LED strings can create When using multiple ADP8140 ICs in parallel to control one
high power dissipation within the ADP8140. If this increase in power supply, all of the FAULT and EN pins must be connected
A
E

power dissipation causes the die temperature on the ADP8140 together. If any FAULT pin goes low, all ADP8140 ICs respond
A
E

to rise above 135°C (typical), the IC automatically begins to to the event. Most applications will work best if the dimming
reduce the output current on all four sinks. If the die tempera- signals are also connected amongst the ADP8140 ICs, though it
ture continues to rise and exceeds 150°C (typical), the ADP8140 is not required.

COUT
PGND PGND PGND PGND PGND SW

PGND SW

SW SW

BST GND
VIN ADP2384
PVIN VREG

PVIN FB

PVIN COMP

PVIN EN PGOOD RT SYNC SS

RT

ADP8140 ADP8140
VIN VIN MIN VIN VIN MIN
REG VT REG VT
MODE DIM DIM MODE DIM DIM
EN SINK1 EN SINK1
FAULT SINK2 FAULT SINK2
FB_OUT SINK3 FB_OUT SINK3
COMP SINK4 COMP SINK4
ISET VO_SNS ISET VO_SNS
EXPOSED PAD EXPOSED PAD
10935-030

FAULT
ENABLE

Figure 28. Multiple ADP8140 ICs Powered from One Supply (Low Gain Buffer Control Shown)

Rev. B | Page 17 of 23
ADP8140 Data Sheet
OPERATING THE ADP8140 FROM HIGHER INPUT EFFECT OF LED VF MISMATCH
VOLTAGES The ADP8140 always controls the FB_OUT pin to regulate the
The ADP8140 is capable of operating from an input voltage output voltage to provide the minimum amount of headroom
(VIN) range of 3.0 V to 30 V. However, higher voltages can be voltage required for the current sinks. One of the current sinks
used to power the ADP8140 when an appropriate current is regulated to VEA(REF). Typically, VEA(REF) is either 350 mV or
limiting circuit is used. 450 mV (see VEA(350) and VEA(450) in Table 1). The voltage seen on
It is sometimes sufficient to limit the voltage on the VIN pin by the other three SINKx pins varies based on the distribution of
placing a Zener diode on VIN and limiting the current with a the LED forward voltage, VF. For a given lot of LEDs, the VF and
resistor from the input voltage to the VIN pin. This method can the change in VF with temperature is relatively consistent. Given
be used if standby power dissipation is not an issue. a VF distribution, the maximum voltage that appears on any of
the SINKx pins can be statistically calculated. For example,
Alternatively, if the supply voltage range is small, an additional consider a mean VF of 3.5 V and a normal distribution with a
Zener diode between the supply and the VIN pin shifts the standard deviation of 70 mV. A statistical analysis of such a
voltage at the VIN pin below 30 V. This method adds minimal distribution reveals the maximum voltage that may appear on
power dissipation in both standby and active modes. any of the SINKx pins, as shown in Figure 30). Note that in
However, a more robust voltage limiter uses a Zener diode, an Figure 30, the maximum value is defined as the average plus six
NPN transistor, and two resistors. This simple circuit, shown in standard deviations (σ) of the distribution.
Figure 29, gives the required operating IQ during normal 3.5
AVERAGE
operation but also reduces the standby current when the MAX
3.0
ADP8140 is disabled.
VCC
2.5
SINKx VOLTAGE (V)

RZ RLIM
2.0
IB
VIN
1.5
VZ
10935-031

CIN
ADP8140 1.0

Figure 29. VIN Current Limiting Circuit for High Input Voltages
0.5

10935-032
Select VZ to give a voltage well below the 30 V absolute
maximum of the VIN pin. With this circuit, the VIN pin voltage 0
0 5 10 15 20 25 30
is regulated to about VZ − 0.7 V. Select the resistor, RZ, to limit NUMBER OF LEDs PER STRING
the current when the ADP8140 is disabled yet still provide Figure 30. Voltage on SINKx Pins Given a Normal Distribution of VF, Standard
enough current to reverse bias the Zener diode and drive the Deviation = 70 mV
NPN transistor when the ADP8140 is active. The current
The SINKx voltage found on each pin determines the power
through RZ is given by
that the ADP8140 package must dissipate. Specifically, the
 V  VZ  ADP8140 power dissipation can be represented as follows:
I RZ   CC 

 RZ  PDISS = (VSINK1 + VSINK2 + VSINK3 + VSINK4) × ILED (2)

A value of 100 μA at the minimum expected VCC is generally A statistical analysis based on the VF distribution of the LED
sufficient. Even at maximum VCC, this value only contributes a can be performed to predict the total power dissipation within
few milliwatts of power dissipation during standby. the ADP8140. For the same distribution used in Equation 2 and
an LED current of 350 mA, Figure 31 gives the average and
RLIM limits the maximum current during transients. A value of a
maximum power dissipations. Note that in Figure 31, the
few hundred ohms is sufficient. When the ADP8140 is active,
maximum value is defined as the average plus six standard
the additional worst case power dissipation from this limit
deviations of the distribution.
circuitry is given by
ΔPDISS(ACTIVE) = (VCC(MAX) – VZ(MIN) + 0.7 V) × IQ =
(48 V − 24 V + 0.7 V) × 3 mA = 74 mW

Rev. B | Page 18 of 23
Data Sheet ADP8140
3.0
AVERAGE
 The ADP8140 is designed for easy layout with single sided
MAX metal core substrates. If FR4 substrate is used, thermal vias
2.5
must be used between the LFCSP exposed pad and a large
ground trace on the opposite side of the board.
SINKx VOLTAGE (V)

2.0
 Place the REG capacitor close to the IC. The location of the
VIN capacitor is not as important.
1.5
 Place the COMP capacitor(s) and resistor as close to the IC
as possible.
1.0
 Place the VO_SNS resistors (if used) close to the IC.
0.5
 If applying an analog dimming voltage to the DIM or VT
pins, placing a bypass capacitor near these pins reduces the

10935-033
0
noise on these dimming signals.
0 5 10 15 20 25 30
NUMBER OF LEDs PER STRING ORDERING OPTIONS
Figure 31. Total Power Dissipation (All Four Strings) for a Normal The ADP8140 is available in two options. The difference
Distribution of VF, Standard Deviation = 70 mV, ILED = 350 mA
between the options is the VEA(REF) voltage and the number of
MANAGING THE POWER DISSIPATION OF THE sinks that control the COMP and FB_OUT voltage.
ADP8140 See Figure 33 to Figure 36 for examples of the ADP8140 used in
With the predicted power dissipation known, the next step is to various configurations: with a PMOS regulation stage, as a
determine if the ADP8140 package is able to dissipate that secondary side controller, with a boost or buck power stage, or
power adequately. Use the following to calculate the maximum with one power stage.
power that the ADP8140 is able to dissipate: ADP8140ACPZ-1-R7
PDISS(MAX) = (TJ − TBOARD)/θJB The ADP8140ACPZ-1-R7 has VEA(REF) at 350 mV. Therefore, if
= (135 − 105)/12.4 = 2.4 W using the device with the PMOS power stage or as a secondary
where: side controller, each current sink can supply up to 350 mA of
TJ =135°C, the maximum ADP8140 junction temperature LED current at 350 mV of headroom voltage. However, if using
(before entering thermal foldback). the device to control an SMPS IC, each current sink can supply
TBOARD = 105°C, the maximum board temperature. up to 500 mA of LED current.
θJB = 12.4°C/W (see Table 3). The minimum voltage for all four of the current sinks is used to
Assume that 100% of the power dissipates through the exposed control the power regulation (COMP and FB_OUT).
pad to the board. ADP8140ACPZ-2-R7
The ability of the ADP8140 package to dissipate heat varies if The ADP8140ACPZ-2-R7 has VEA(REF) at 450 mV. Therefore, all
the operating conditions are not consistent with the θJB four of the sinks can be driven to 500 mA in any configuration.
conditions given in Table 3. Additionally, it is imperative to
Only the minimum voltage from SINK1, SINK2, and SINK3 is
follow the layout guidelines given in the Layout Guidelines
used to control the FB_OUT and COMP pins. Therefore, this is
section.
the preferred device model if only three LED strings are used in
LAYOUT GUIDELINES a system. SINK4 can be left floating or connected to GND. Note
For optimum performance, follow these layout guidelines: that SINK4 is still enabled; if it is connected to an LED string, it
regulates its current to be the same as the other sinks. Therefore,
 The exposed pad of the ADP8140 must be properly SINK4 can be combined with another SINKx pin (for example
connected to a heat sink. Solder the exposed pad to the to drive two strings at 1 A each).
PCB and connect it to a large plane of ground metal with
an array of thermal vias.

Rev. B | Page 19 of 23
ADP8140 Data Sheet

VCC

NTC

ADP8140
VIN MIN
REG VT
MODE DIM
ENABLE EN SINK1
FAULT FAULT SINK2
FB_OUT SINK3
COMP SINK4
ISET VO_SNS
EXPOSED PAD

10935-034
Figure 32. ADP8140 with a PMOS Regulation Stage

D1
VCC COUT

DRV M1
POWER FACTOR
CORRECTION/ CS
FLYBACK
CONTROLLER RCS NTC

FB
RN
GND

ADP8140
VIN MIN
REG VT
VZS
MODE DIM
ROPTO EN SINK1
FAULT SINK2
AC INPUT FB_OUT SINK3
VOLTAGE
COMP SINK4
ISET VO_SNS
RO2
RO1
10935-035

CIN CREG CC RSET EXPOSED PAD

Figure 33. ADP8140 Secondary Side Control Design Example

Rev. B | Page 20 of 23
Data Sheet ADP8140

VIN

AGND VCC BST

FB VIN

COMP ADP2441 SW

EN PGND
NTC
PGOOD FREQ SS/TRK

ADP8140
VIN MIN
REG VT
MODE DIM DIM
EN SINK1
nFAULT FAULT SINK2
ENABLE FB_OUT SINK3
COMP SINK4
ISET VO_SNS

10935-036
EXPOSED PAD

Figure 34. ADP8140 with a Buck Power Stage

ADP8140
5V 6 VIN SW 5 VIN MIN
REG VT
ADP1612
MODE DIM DIM
3 EN
EN EN SINK1
FB 2 FAULT SINK2
7 FREQ
FB_OUT SINK3
COMP SINK4
8 SS COMP 1
ISET VO_SNS

GND EXPOSED PAD

10935-037
4

Figure 35. ADP8140 with a Boost Power Stage

Rev. B | Page 21 of 23
ADP8140 Data Sheet

COUT
PGND PGND PGND PGND PGND SW

PGND SW

SW SW

BST GND
VIN ADP2384
PVIN VREG

PVIN FB

PVIN COMP

PVIN EN PGOOD RT SYNC SS

RT

ADP8140 ADP8140
VIN VIN MIN VIN VIN MIN
REG VT REG VT
MODE DIM DIM MODE DIM DIM
EN SINK1 EN SINK1
FAULT SINK2 FAULT SINK2
FB_OUT SINK3 FB_OUT SINK3
COMP SINK4 COMP SINK4
ISET VO_SNS ISET VO_SNS
EXPOSED PAD EXPOSED PAD

10935-038
nFAULT
ENABLE

Figure 36. Multiple ADP8140 ICs with One Power Stage

Rev. B | Page 22 of 23
Data Sheet ADP8140

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)

4.10 3.40
4.00 SQ 3.30
3.90 3.20 0.40 BSC
9 16

2.80
PIN 1 INDEX EXPOSED 2.70
AREA PAD
2.60
0.50
0.40
0.30 8 1
0.20 MIN
TOP VIEW BOTTOM VIE W
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)

0.80
0.75 SIDE VIEW
0.05 MAX FOR PROPER CONNECTION OF
0.70 THE EXPOSED PAD, REFER TO
0.02 NOM
THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
SEATING 0.25 0.08 SECTION OF THIS DATA SHEET.
PLANE 0.20 0.203 REF

06-19-2018-B
0.15
PKG-003927

COMPLIANT TO JEDEC STANDARDS MO-229-WGGE.

Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-29)
Dimensions shown in millimeters

ORDERING GUIDE
Model1, 2, 3 VEA(REF) (mV) Temperature Range Package Description Package Option
ADP8140ACPZ-1-R7 350 −40°C to +125°C 16-Lead LFCSP, 7” Tape and Reel CP-16-29
ADP8140ACPZ-2-R7 450 −40°C to +125°C 16-Lead LFCSP, 7” Tape and Reel CP-16-29
ADP8140EB-EVALZ ADP8140 PMOS Evaluation Board
ADP8140CP-EVALZ ADP8140EB-EVALZ with the LEDs and Heat Sink
1
Z = RoHS Compliant Part.
2
ADP8140ACPZ-1-R7: SINK4 function is normal.
3
ADP8140ACPZ-2-R7: SINK4 regulates current but does not control FB_OUT and COMP.

©2015–2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10935-9/20(B)

Rev. B | Page 23 of 23
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Analog Devices Inc.:

ADP8140ACPZ-2-R7 ADP8140ACPZ-1-R7 ADP8140CP-EVALZ ADP8140EB-EVALZ