Unit-4

Digital Integrated Circuit Design: An overview, CMOS logic gate

circuits basic structure, CMOS realization of inverters, AND, OR,
NAND and NOR gates.

Latches and Flip flops: The latch, CMOS implementation of SR flip-

flops, a simpler CMOS implementation of the clocked SR flip-flop,
CMOS implementation of J-K flip flops, D flip- flop circuits.
 Integrated Circuits
An Integrated Circuit(IC) or monolithic integrated circuits is a set of
electronics circuit on one small plate (Chip) of semiconductor materials.
or
A circuit in which all or some of the circuit elements are inseparable
associated and electrically interconnected, so that it is considered for the
purpose of construction are called as integrated circuit. An IC consists of
interconnected transistors, capacitors, resistors, diodes etc. These
components are interconnected with an external connecting terminals
contained in a small package.

Classification of ICs (Integrated Circuits)

Below is the classification of different types of ICs basis on their chip size.
 SSI: Small scale integration. 3 – 30 gates per chip.

 MSI: Medium scale integration. 30 – 300 gates per chip.

 LSI: Large scale integration. 300 – 3,000 gates per chip.
 VLSI: Very large scale integration. More than 3,000 gates per chip or
20,000-1,00,000 transistor/chip
 ULSI: Ultra Large Scale Integration. 106-107 transistor/chip
 GSI: Giant-Scale Integration. > 107 transistor/chip

Types of ICs (Integrated Circuits)

Based on the method or techniques used in manufacturing them, types of
ICs can be divided into three classes:
1. Thin and thick film ICs
2. Monolithic ICs
3. Hybrid or multichip ICs
Below is the simple explanation of different types of ICs as mentioned above.
1. Thin and Thick ICs:
In thin or thick film ICs, passive components such as resistors, capacitors are
integrated but the diodes and transistors are connected as separate
components to form a single and a complete circuit. Thin and thick ICs that
are produced commercially are merely the combination of integrated and
discrete (separate) components.
Thick and thin ICs have similar characteristics, similar appearance except the
method of film deposition. Method of deposition of films distinguished Thin
ICs from Thick ICs.

Thin film ICs are made by depositing films of a conducting material on a glass
surface or on a ceramic base. By varying the thickness of the films deposited
on the materials having different resistivity, Passive electronic components
like resistors and capacitors can be manufactured.
In Thick film ICs, silk printing technique is used to create the desired pattern
of the circuit on a ceramic substrate. Thick-film ICs are sometimes referred to
as printed thin-film.
The screens are actually made of fine stainless steel wire mesh and the links
(connections) are pastes having conductive, resistive or dielectric properties.
The circuits are fired in a furnace at a high temperature so as to fuse the films
to the substrate after printing.
2. Monolithic ICs
In monolithic ICs, the discrete components, the active and the passive and
also the interconnections between then are formed on a silicon chip. The
word monolithic is actually derived from two Greek words “mono” meaning
one or single and Lithos meaning stone. Thus monolithic circuit is a circuit
that is built into a single crystal.
Monolithic ICs are the most common types ICs in use today. Its cost of
production is cheap and is reliable. Commercially manufactured ICs are used
as amplifiers, voltage regulators, in AM receivers, and in computer circuits.
However, despite all these advantages and vast fields of application of
monolithic ICs, it has limitations. The insulation between the components of
monolithic ICs is poor. It also have low power rating, fabrication of insulators
is not that possible and so many other factors.
3. Hybrid or Multi chip ICs
As the name implies, “Multi”, more than one individual chips are
interconnected. The active components that are contained in this kind of ICs
are diffused transistors or diodes. The passive components are the diffused
resistors or capacitors on a single chip.

These components are connected by metallised patterns. Hybrid ICs are

widely used for high power-amplifier applications from 5W to more than
50W. Its performance is better than that of monolithic ICs.
 Digital Integrated Circuits

These types of ICs work on the basic digital system i.e. two defined level
which is 0’s and 1’s (in other words, Low and High or ON and OFF
respectively). Microprocessor and Micro controller is the example of Digital
ICs which contains of millions of flip flops and logic gates.
Analog Integrated Circuits
Analog ICs work by processing continuous signals i.e. analog signal. OP-AMP
(Operational Amplifier), NE 555 Timers and Sensors are the example of
Analog ICs. These types of ICs are used for amplification, filtering,
modulation, demodulation etc.
Mixed Signal ICs
Mixed Signal Integrated Circuit is a kind of ICs where both Digital and Analog
ICs are combine on a single chip.
Advantages and Applications of ICs
ICs have advantages over those that are made by interconnecting discrete
components some of which are its small size.
 It is a thousand times smaller than the discrete circuits.
 It is an all in one (components and the interconnections are on a single
silicon chip).
 It has little weight and Its cost of production is also low.
 It is reliable because there are no soldered joints.
 ICs consume little energy and can easily be replaced when the need arises.
 It can be operated at a very high temperature.
 Different types of ICs are widely applied in our electrical devices such as
high power amplifiers, voltage regulators, TV receivers and computers etc.
Limitation for different types of ICs
Despite the advantages that ICs provide us with, it have limitations some of
which are:
 Limited power rating
 It operates at low voltage
 It produces noise during operation
 Its components such as resistors and capacitors are voltage dependent
 It is delicate i.e it cannot withstand rough handling etc.
 Digital Integrated Circuit Design

The classification of Digital Integrated Circuit technologies and logic families

are as:

Complementary
CMOS

Pseudo
Pseudo-NMOS

CMOS

Pass-Transistor
Transistor Logic

Dyanimic Logic

Didgital IC
Technologies and TTL
Logic-circuit families
Bipolor

ECL

BiCMOS

GaAs

Member of each family are made with same having a similar circuit structure
and exhibit the same basic feature. Each logic families offer a unique set of
advantage and disadvantages.
In the conventional style of designing system, one selects an appropriate
logic family (e.g. TTL, ECL, and CMOS) and attempts to implement as much of
the system as possible using circuit modules that belong to this family. In this
way interconnection between the various packages is relatively straight
forward. One e the other hand, package from more than one family are used, it
is required to design suitable interconnection circuits.
The selection of logic family is based on:
 Logic flexibility
 Speed of Operation
 Availability of complex function
 Noise Immunity
 Operating temperature
 Power dissipation
 Cost

Logic-Circuit Characterization

The following parameter is usually used to characterize the operation and

performance of the logic-circuit family:
1. Noise Margins
2. Propagation Delay
3. Power Dissipation
4. Delay-Power Product
5. Fan-In and Fan-out
1. Noise Margins (NM):
The statics operation of logic-circuits family is characterised by the voltage
transfer characteristic (VTC) of basic inverter.
Noise margin is the amount of noise that a circuit can withstand. The ability
of gate to tolerate fluctuations of the voltage levels. The robustness of a
logic-circuit
circuit family is determined by its ability to reject noise. The Noise
Margin is the maximum voltage
voltage amplitude of extraneous signal that can be
algebraically added to the noise-free
noise worst-case
case input level without causing
the output voltage to deviate from the allowable logic voltage level.
2. Propagation Delay (PD):
The dynamic operation of logic-circuits
logic ts family is characterised by the
propagation delay of basic inverter.

Propagation delay is the length of time taken for a signal to reach its
destination.
or
The
he time required for the output of a digital circuit to change states after a
change at one or more of its inputs. The speed of a digital circuit is specified
in terms of the propagation delay time. The delay times are measured
between the 50 percent voltage levels of input and output waveforms. There
are two delay times,
tpHL: when the output goes from the HIGH state to the LOW state
tpLH: when the output making a transition from the LOW state to the HIGH
state.
The
he propagation delay time of the logic gate is taken as the average of these
two delay times.

= ( − )
 3. Power Dissipation:
The power dissipation is defined a power needed by the logic circuit. There
are two types of power dissipation in logic gate.
a. Static
b. Dynamic
Static power refers to the power that the gate dissipates in absence of
switching action. Dynamic power on the other hand occurs only when the
gate is switched. An inverter operated from power supply VDD driving a load
capacitor C, dissipate dynamic power PD.
=
4. Delay-Power Product
The delay power product is a figure of merit correlated with the energy
efficiency of the logic gate. Also known as switching erengy, it is a product of
power consumption time the input-output delay.
= .
5. Fan-In and Fan-out:
Fan-in (input load factor) is the number of input signals that can be
connected to a gate without causing it to operate outside its intended
operating range. expressed in terms of standard inputs or units loads (ULs).

Fan-out (output load factor) is the maximum number of inputs that can be
driven by a logic gate. A fanout of 10 means that 10 unit loads can be driven
by the gate while still maintaining the output voltage within specifications
for logic levels 0 and 1.
 CMOS Logic Gate Circuits

Complimentary Symmetry Metal-Oxide Semiconductor, COSMOS or CMOS is

a predominant technology for manufacturing integrated circuits. This
dominance of CMOS Technology in the fabrication of Integrated Circuits or
ICs will continue for decades to come.
The name complementary in CMOS refers to the fact that both NMOS and
PMOS Transistors are used in the same design. The basic gate employs both P
and N MOSFETS.
Basic Structure
The CMOS logic gate consists of two networks:
a. Pull Down Network(PDN)
b. Pull Up Network(PUN)
The structure of CMOS is as:

The PDN is constructed using NMOS transistor and PUN is constructed PMOS
transistor. CMOS logic is arranged in such a way that only one of the pull-up
or pull-down networks is ON while the other is OFF with the help of a single
input.
 CMOS Inverter

The simplest of the logic gates is the Inverter. It is an essential part of digital
design and understanding the operation and properties of an Inverter will
make it significantly easier to study NAND Gates, Adders, Multiplexers and
even Microprocessors. Following is the circuit of a CMOS Inverter Gate along
with its symbols.

Operation: When the input is LOW both gate are at grou ground potential, it
means gate voltage
ge relative to PMOS are at -VDD and at 0V relative to the
source of NMOS. The result is that the PMOS is turn ON and NMOS is turned
OFF. Under this condition, there is a LOW impedance path from VDD to the
output and a very HIGH impedance from output to ground. Therefore the
output voltage
age approches the HIGH level i.e. VDD under normal loading
condition.
When the input is HIGH both gate are at VDD potential, and the situration
reversed it means gate volatge relative to PMOS are at 0V and at VDD relative
to the source of NMOS. The result is that the PMOS is turn OFF and NMOS is
turned ON. Under this condition, there is a HIGH impedance path from VDD to
the output and a very LOW impedance path from output to ground.
Therefore the output voltage approches the LOW level i.e. 0 volt under
normal loading condition.
The truth table of CMOS inverter are as:-
as:
Input MOS Transistor Output
S. No.
M1 M2 =
1 0 ON OFF 1
2 1 OFF ON 0
From above truth table, in either state, one MOS transistor is ON while other
is OFF. Because one transistor is always OFF, the DC power dissipation is
extremely low of order 10nW. The major power drain occurs when the
CMOS circuit change state.

Advantage of CMOS:
 Low power dissipation
 Excellent Noise Immunity
 High package density
 Wide range of supply voltage
This advantage makes it a strong contender for a popular standard for digital
circuit design.
 Realization of Two input NOR Gate

Two inputs CMOS NOR does gate contain two NMOS connected in parallel in
pull down network and two NMOS connected in series in pull up network.

Operation:
When all the input are LOW, both of PMOS are ON and both NMOS are OFF.
Under this condition, there is a LOW impedance path from VDD to the output
and a very HIGH impedance from output to ground. Therefore the output
voltage approches the HIGH level i.e. VDD under normal loading condition.
If any input is HIGH, the associated PMOS transistor is OFF and the
corresponding NMOS transistor turn ON. Under this condition, there is a
HIGH impedance path from VDD to the output and a very LOW impedance
path from output to ground. Therefore the output voltage approches the
LOW level i.e. 0 volt under normal loading
l condition.
The truth table of CMOS inverter are as:-
as:

Input Status of MOS Transistor Output

S. No.
MAN MBN MAP MBN = +
1 0 0 OFF OFF ON ON 1
2 0 1 OFF ON ON OFF 0
3 1 0 ON OFF OFF ON 0
4 1 1 ON ON OFF OFF 0
 Realization of Two input NAND Gate

Two input CMOS NAND does gate contain two NMOS connected in series in
pull down network and two PMOS connected in parallel in pull up network.

Operation:
When all the input are HIGH,
HIGH both of NMOS
MOS are ON and both PMOS are OFF.
Under this condition, there is a HIGH impedance path from VDD to the output
and a very LOW impedance path from output to ground. Therefore the
output voltage approches the LOW level i.e. 0 volt under normal loading
condition.
If any input is LOW, the associated PMOS PMOS transistor is ON and the
corresponding NMOS transistor turn OFF. Under this condition, there is a
LOW impedance path from VDD to the output and a very HIGH impedance
from output to ground. Therefore the output voltage approches the HIGH
level i.e. VDD under
der normal loading condition.
The truth table of CMOS inverter are as:-
as:

Input Status of MOS Transistor Output

S. No.
MAN MBN MAP MBN = .
1 0 0 OFF OFF ON ON 1
2 0 1 OFF ON ON OFF 1
3 1 0 ON OFF OFF ON 1
4 1 1 ON ON OFF OFF 0
 Realization of Two input OR Gate

Two input CMOS OR gate contain two NMOS connected in parallel in pull
down network and two NMOS connected
connected in series in pull up network and
then inverter is connected having one NMOS in pull down network and one
PMOS in pull up network as:-
as:

Operation:
When all the inputs are LOW, both of PMOS are ON and both NMOS are OFF.
Under this condition, there is a LOW impedance path from VDD to the input of
inverter, which make PMOS transistor (M1) OFF and NMOS transistor (M2)
ON. Hence a very LOW impedance created from output to ground. Therefore
the output voltage approches the LOW level i.e. 0Volt under normal loading
condition.
If any input is HIGH, the associated PMOS transistor is OFF and the
corresponding NMOS transistor turn ON. Under this condition, there is a
LOW impedance path from 0 Volt to input of inverter, which make PMOS
transistor (M1) ON and NMOS transistor (M2) OFF. Hence a very LOW
impedance created from output to VDD ground. Therefore
erefore the output voltage
approches the HIGH level i.e. VDD volt under normal loading condition.
The truth table of CMOS inverter are as:-
as:
S. Input Status of MOS Transistor Output1 Output2
No. MAN MBN MAP MBN M1 M2 = + = +
1 0 0 OFF OFF ON ON OFF ON 1 0
2 0 1 OFF ON ON OFF ON OFF 0 1
3 1 0 ON OFF OFF ON ON OFF 0 1
4 1 1 ON ON OFF OFF ON OFF 0 1
 Realization of Two input AND Gate

Two input CMOS AND gate contain two NMOS MOS connected in series in pull
down network and two PMOS connected in parallel in pull up network and
then inverter is connected having one NMOS in pull down network and one
PMOS in pull up network as:-
as:

Operation:
When all the inputs are LOW, both of PMOS are ON and both NMOS are OFF.
Under this condition, there is a LOW impedance path from VDD to the input of
inverter, which make PMOS transistor (M1) OFF and NMOS transistor (M2)
ON. Hence a very LOW impedance created from output to ground.
round. Therefore
the output voltage approches the LOW level i.e. 0Volt under normal loading
condition.
If any input is HIGH, the associated PMOS transistor is OFF and the
corresponding NMOS transistor turn ON. Under this condition, there is a
LOW impedance path from 0 Volt to input of inverter, which make PMOS
transistor (M1) ON and NMOS transistor (M2) OFF. Hence a very LOW
impedance created from output to VDD ground. Therefore the output voltage
approches the HIGH level i.e. VDD volt under normal loading condition.
The truth table of CMOS inverter are as:-
as:
S. Input Status of MOS Transistor Output1 Output2
No. MAN MBN MAP MBN M1 M2 = + = +
1 0 0 OFF OFF ON ON OFF ON 1 0
2 0 1 OFF ON ON OFF ON OFF 0 1
3 1 0 ON OFF OFF ON ON OFF 0 1
4 1 1 ON ON OFF OFF ON OFF 0 1
 Realization of Complex Gate
There are a few more important gates
gate that are complex but find extensive
use in digital system. These are
1. AND-OR-INVERT(AOI)
INVERT(AOI)
2. OR-AND-INVERT(OAI)
INVERT(OAI)

1. AND-OR-INVERT (AOI)
Consider function
= +
In the fuction , and are two AND fuction and their sum is the OR
function and finally inverted. It means is implemented as an AND
AND-OR-
INVERT (AOI) gate.
 2. OR-AND-INVERT (OAI)
Consider function
= ( + ). ( + )
In the fuction , and are two OR fuction and their product is the AND
function and finally inverted. It means is implemented as an OR OR-AND-
INVERT (OAI) gate.
Ex- Realise two inputs CMOS Ex-OR
Ex Gate i. e. = . + .

In terms of AOI In terms of OAI

In order to design pull down network In order to design pull down network
first of all we calculate first of all we calculate
= . + . = . + .
= + . + = + . +
= ( + ). ( + ) = ( + ).
)( + )
= . + .
Ex- Realise two inputs CMOS Ex-NOR
Ex Gate i. e. = . + .
In order to design pull down network first of all we calculate
= . + .
= + .( + )
= ( + ). ( + )
= . + .
Ex- Sketch a CMOS logic gate that realizes function = . . + . .
= . . + . .
= . . + . .
= ( . . ). ( . . )
=( + + ). + +
=( + + ). ( + + )
= . + . + . + . + . + . + . + . + .
= . + . + . + . + . + .
Ex- = . . + . .
= . . + . .
= ( . . ). ( . . )
=( + + ). + +
=( + + ). ( + + )
= . + . + . + . + . + . + . + . + .
= . + . + . + . + . + .
= .( + ) + ( + ) + .( + )
Ex- = . . + . .
= . . + . .
= ( . . ). ( . . )
=( + + ). + +
=( + + ). ( + + )
Ex- Sketch a CMOS logic circuits that realizes half adder.
Solution:
Input Output
S. No.
Sum Carry
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1

= . + .
= . + .
= + . +
= ( + ).
)( + )

= .
= . = +
Ex- Design a CMOS circuit that realize the function of 3 input odd parity
checkers. Specially the output is to be high when the odd number (1 or 3) of
the inputs are high.
Solution:
Inputs Output
0 1 0 1
0 0 0 0
1 0 1 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
= . . + . . + . . + . .
So, for pull down network
= . . + . . + . . + . .
= ( . . ). . . . . . .( . . )
= + + . + + . + + .( + + )
= ( + + ). ( + + ). ( + + ). ( + + )
Ex- Design a CMOS circuit that realize the function of 3 input odd parity
checkers. Specially the output is to be high when the odd number (1 or 3) of
the inputs are high. Attain design with 10 transistor in each of pull up(PUN)
and pull down networks(PDN) (not
(no include inverters).
Solution:
Inputs Output
0 1 0 1
0 0 0 0
1 0 1 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
= . . + . . + . . + . .
So, for pull down network
= . . + . . + . . + . .
= ( . . ). . . . . . .( . . )
= + + . + + . + + .( + + )
= ( + + ). ( + + ). ( + + ). ( + + )
Ex- Design a CMOS circuit that realize the function of 3 input even parity
checkers. Specially the output is to be high when the even number (0 or 2) of
the inputs are high.
Solution:
Inputs Output
1 0 1 0
0 0 0 1
0 1 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
= . . + . . + . . + . .
So, for pull down network
= . . + . . + . . + . .
= ( . . ). . . . . . . . .
= + + . + + . + + . + +
= ( + + ). ( + + ). ( + + ). ( + + )
Ex- Design a CMOS circuit that realize the function of 3 input even parity
checkers. Specially the output is to be high when the even number (0 or 2) of
the inputs are high. Attain design with 10 transistor in each of pull up(PUN)
and pull down networks(PDN) (not include inverters).
Solution:
Inputs Output
1 0 1 0
0 0 0 1
0 1 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
= . . + . . + . . + . .
So, for pull down network
= . . + . . + . . + . .
= ( . . ). . . . . . . . .
= + + . + + . + + . + +
= ( + + ). ( + + ). ( + + ). ( + + )
Ex- Design a CMOS full adder circuit with input A, B,C and two output S, C0
such that S is high if 1 or 3 input is high and C0 is 1 if two or more inputs are 1.
Solution:
Inputs Output
S
0 1 0 1
0 0 0 0 0
1 0 1 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 C0
1 0 0 1 0 0 0 1 0
1 0 1 0 1 0 1 1 1
1 1 0 0 1
1 1 1 1 1

= . . + . . + . . + . .
= . + . + .
So, for pull down network
= . . + . . + . . + . .
= ( . . ). . . . . . .( . . )
= + + . + + . + + .( + + )
= ( + + ). ( + + ). ( + + ). ( + + )
= .( + . + .
= .( + ) + .
= + ( ). ( + )