Digital System Design

USING VERILOG
CDAC NOIDA
M.TECH ( VLSI DESIGN) FI RST SEMESTER
I SHA GUPTA
L ECTURE - 3

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Verilog Language
Verilog has a variety of constructs as part of it. All are aimed at providing a functionally tested
and a verified design description for the target FPGA or ASIC.

The language has a dual function – one fulfilling the need for a design description and the other
fulfilling the need for verifying the design for functionality and timing constraints like
propagation delay, critical path delay, slack, setup, and hold times.

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Hierarchical Modeling Concepts
The designer must use a "good" design methodology to do efficient Verilog HDL-based design.

There are two basic types of digital design methodologies:

A top-down design methodology and

A bottom-up design methodology.

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Top-Down Design Methodology
In a top-down design methodology, we define the top-level block and identify the sub-blocks
necessary to build the top-level block.
We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot
further be divided.

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Top-Down Design Methodology
In a bottom-up design methodology, we first identify the building blocks that are available to
us.
We build bigger cells, using these building blocks. These cells are then used for higher-level
blocks until we build the top-level block in the design.

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Design Approach
Typically, a combination of top-down and bottom-up flows is used.
Design architects define the specifications of the top-level block. Logic designers decide how
the design should be structured by breaking up the functionality into blocks and sub-blocks. At
the same time, circuit designers are designing optimized circuits for leaf-level cells. They build
higher-level cells by using these leaf cells.
The flow meets at an intermediate point where the switch-level circuit designers have created
a library of leaf cells by using switches, and the logic level designers have designed from top-
down until all modules are defined in terms of leaf cells.

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Module in Verilog
A module is the basic building block in Verilog.
Any Verilog program begins with a keyword – called a “module.”
A module is the name given to any system considering it as a black box with input and output
terminals as shown in Figure

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Module in Verilog
The terminals of the module are referred to as ‘ports’.
The ports attached to a module can be of three types:
Input ports
Output ports
Inout ports
A module provides the necessary functionality to the higher-level block through its port
interface (inputs and outputs).

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Module Declaration in Verilog
In Verilog, a module is declared by the keyword module.

A corresponding keyword endmodule must appear at the end of the module definition.

Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

Verilog takes the active statements appearing between the “module” statement and the
“endmodule” statement and interprets all of them together as forming the body of the module.
Whenever

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 Module Declaration Example
module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule

Specifically, the T-flipflop could be defined as a module as follows:

module T_FF (q, clock, reset);

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Levels of Design Abstraction
Internals of each module can be defined at four levels of abstraction, depending on the needs
of the design.
The module behaves identically with the external environment irrespective of the level of
abstraction at which the module is described.

Switch Level
Gate Level
Data Level
Behavioral Level

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Instances
A module provides a template from which you can create actual objects.
When a module is invoked, Verilog creates a unique object from the template. Each object has
its own name, variables, parameters, and I/O interface.
The process of creating objects from a module template is called instantiation, and the objects
are called instances.

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Instances Example

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Instantiation
As part of the instantiation declaration, the input and
output terminals are to be defined.
The convention followed is to stick to the same order as in
the module declaration.
Some modules may have a large number of ports. Sticking
to the order of the ports in an instantiation is likely to cause
(human) errors.
An alternative (and sometimes more convenient) form of
instantiation is also possible

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Module Important Points
In Verilog, it is illegal to nest modules. One module definition cannot contain another module
definition within the module and endmodule statements.
Instead, a module definition can incorporate copies of other modules by instantiating them.
Each module can be defined only once.
Module definitions are to be done independently. One module cannot be defined inside
another – they cannot be nested.
Any module can be instantiated inside another any number of times. Each instantiation has to
be done with a separate name assigned to it.

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Test Benches
Any digital circuit that has been designed and wired goes through a testing process before
being declared as ready for use.
Testing involves studying circuit behavior under simulated conditions for the following:
Check and ensure that all functions are carried out as desired.
Check and ensure that all the functional sequences are carried out as desired.
Check for the timing behavior:

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Test Benches
Simulated testing is a time-based Initial
activity. It is usually carried out in Begin
simulated time. a1 = 0;
a2 = 0;
With any simulation tool the #3 a1 = 1;
simulation progresses through equal #1 a1 = 0;
simulation time steps. The time step #2 a2 = 1;
can be 1 fs, 1 ps, 1 ns and so on. In the #4 a1 = 1;
text the default value is taken as 1 ns. #3 a2 = 0;
#1 a2 = 1;
end
and g1(b, a1, a2);
initial $monitor ( $time, “a1 = %b, a2 = %b, b = %b”’ a1, a2, b);
#100 $finish;

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Test Benches
The keyword initial is followed by a Initial
sequence of statements between the Begin
keywords begin and end. a1 = 0;
a2 = 0;
The “# 3” implies a time delay or wait #3 a1 = 1;
time of 3 time steps in simulation. #1 a1 = 0;
Thus the sequence implies the #2 a2 = 1;
following: #4 a1 = 1;
#3 a2 = 0;
At 0 simulation time the logic variables #1 a2 = 1;
a1 and a2 are assigned the logic level 0. end
and g1(b, a1, a2);
initial $monitor ( $time, “a1 = %b, a2 = %b, b = %b”’ a1, a2, b);
#100 $finish;

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Test Benches
With a delay of 3 ns a1 is reassigned Initial
the logic value of 1. Begin
a1 = 0;
With a further delay of 1 ns – that is, a2 = 0;
at the 4th ns - a1 is reverted to the logic #3 a1 = 1;
level 0. #1 a1 = 0;
Similarly at the 6th, 10th, 13th and #2 a2 = 1;
14th ns values of simulation time, #4 a1 = 1;
further changes are made to a1 and a2. #3 a2 = 0;
#1 a2 = 1;
Note that every time value specified end
here is an increment in simulation time. and g1(b, a1, a2);
initial $monitor ( $time, “a1 = %b, a2 = %b, b = %b”’ a1, a2, b);
#100 $finish;

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Test Benches
The values of a1 and a2 are not Initial
changed beyond the 14th ns. Begin
a1 = 0;
The statement initial # 100 $finish; a2 = 0;
implies that the simulation is to b #3 a1 = 1;
continued up to the 100th ns o #1 a1 = 0;
simulation time and then stopped. #2 a2 = 1;
The statement initial $monitor ( #4 a1 = 1;
$time, “a1 = %b, a2 = %b, b = %b”’ a1, #3 a2 = 0;
a2, b); monitors a1, a2, and a3 for #1 a2 = 1;
changes; whenever any of them end
changes, all of them are sampled and and g1(b, a1, a2);
the sampled values displayed. initial $monitor ( $time, “a1 = %b, a2 = %b, b = %b”’ a1, a2, b);
#100 $finish;

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Test Benches
Summarizing testing constitutes three activities:
Generation of the test signals – under the “initial” banner
Application of the test signal to the circuit under test – through instantiation
Observing selected signal values – through the $monitor statement

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