Agenda * Design Methodologies. * Port Connection rules. * Hierarchical Modeling examples. * Module Instantiation by Port Name. * Modules Instantiation by Port Order. Design Verification using Test benches.Design Methodology Top-Down + Define final(top) module. * Identify the sub module to be added. + Describe Sub module and establish connections. er ; Bottom-Up + Design the basic module (leaf cells). -Assemble (Instantiate) sub modules to describe top module. Tepeve black — ot} let} Let} Lew} Lat} Lot a on RK let [ ter) [a vet] Par] [ae cat} Lat} | cot | | cot a] La) Lat} LarModule Instances QModule + Serves as template for creating actual new objects * Once invoked Verilog creates a unique object from the template UModule Instantiation * The process of creating unique objects from a module template + The created objects are called module instances + Each object has its own name, variables, parameters and I/O InterfacesPort Connection Rules input output a —— reg or net net reg or net net . input ports should be of net data a ype (wire) and can be connected to net as well as register to the external world. * Output ports may be register or a net internally but should be connected to net to the external world. + Width Matching : It is illegal to connect an Internal and External items of different sizes while making Inter-module port connections.4 bit full adder: Hierarchical View 4 Bit Adder modules Top-down modules FA FA FA FA I t I J module2 cto ee! cro ct HA} OR HA HA] OR OR OR Gaoid XOR AND XOR AND XOR AND hd XOR AND XOR AND G4 XOR AND XOR AND HA XOR AND modulet Bottom-up1 bit full adder sum 1 fa (1 bit full adder) cout module fa (a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum= a b* cin; assign cout=(a & b) | (b &cin) |(a & cin); endmodule4 bit ripple carry adder AB] BIS] AR] BP] All] Bit] Alo] BiO ‘i -— . 3 5 a |; cour: gC tt 8 Eto g a Cin Tout 5Module Instantiation -By Port Name: Syntax Verilog! my_verilog (a Instance name Module name: >Module Name : Name of the module to be instantiated (DUT) >Instance Name: Specific name for this particular instantiation of DUT >a: Port of the module to be instantiated (sub module/DUT) >v_a : name of the corresponding port of top level block (Top level block/TB) >Port Connection list controls how this instantiation connects to the ports in the top level block >Same module can be instantiated multiple time, but each with unique name4 bit ripple carry adder: By Port order AGT BD] AB] BE] amy Boy Ao) BIO) seats sex} sexiay semo) module rca (A, B, CIN, SUM, COUT); input [3:0] A, B; input CIN; module fa (a, b, cin, sum, cout); output [3:0] SUM; output COUT; input a, b, cin; fa faO (A[O], B[0], CIN, SUM[O], C1); output sum, cout; assign sum= a% b% cin; assign cout=(a & b) | (b &cin) |(a & cin); endmoduleComponents of a Simulation * Once Design is completed it’ must be verified. * Two styles of stimulus applicationsTest Bench Example a) -DUV : AND2 Gate Description module and2_df (a , b, out); module test_file input a , b; output out; Data type declaration wire a,b, out; assign out=a & b; Tested block instantiation endmodule Test pattern generation Monitor output endmoduleTest Bench Example cy module test_file -Stimulus Description _ Data type declaration Tested block instantiation (Test pattern generation module and2_df_tb; reg A,B; wire OUT; endmodule and2_df duv (.a(A), .b(B), .out(OUT)); // Instantiation by port name initial begin Smonitor ( “Simtime=%g, A=%b, B=%b, OUT=%b", $time, A, B, OUT); ‘ endTest Bench Example ea) Stimulus Description module test_file Data type declaration Tested block instantiation Test pattern generation module and2_df_tb; reg A,B; wire OUT; Cacoieel and2_df duv (.a(A), .b(B), .out(OUT)); _// instantiation by port name initial begin $monitor ( "Simtime=%g, A=%b, B=%b, OUT=%b", Stime, A, B, OUT); end initial begin #5 A=0;B=0; #5 A=0;B=1;. #5 A=1;B=0; #5 A=1;B=1; endSummary * Design Methodologies. * Port Connection rules. Hierarchical Modeling examples. Port Instantiation by Port Name. Port Instantiation by Port Order. * Design Verification using Test benches.