Introduction to the

ARM® Cortex™-M Architecture

Delivering Cost-Sensitive High-Performance
32-Bit Devices

1
The ARM Cortex™ Family

x1-4
 ARM Cortex A Series - Applications CPUs
Cortex-A9
focused on the execution of complex OS and user
Cortex-A8 applications
Performance

Cortex-R4(F)  ARM Cortex R Series - Deeply embedded

processors focused on Real-time environments

Cortex-M3
SC300  ARM Cortex M Series - Microcontroller cores
focused on very cost sensitive, deterministic,
Cortex-M1 interrupt driven environments
Cortex-M0

2
 Introduction to the ARM® Cortex™-M Architecture

CORTEX-M3

3
 Introduction to Cortex-M3 Processor
 Cortex-M3 Architecture
 Harvard bus architecture
 3-stage pipeline with branch speculation
 Integrated bus matrix
 Configurable nested vectored interrupt
controller (NVIC)
 Advanced configurable debug and trace
components

 Optional components for specific market

requirements:
 Wake-up Interrupt Controller (WIC)*
 Memory Protection Unit (MPU)
 Embedded Trace Macrocell (ETM)
 Fault Robust Interface*

* Cortex-M3 Release 2

4
Cortex-M3 Processor Overview
Integrated Nested Vectored Central Core:
Wake-Up Interrupt Controller:
Interrupt Controller and 1.25 DMIPS/MHz
for Low Power Stand by
SYSTICK Timer 1 Cycle Multiply
Operation
Hardware Divide

Memory Protection Embedded Trace

Unit (MPU) Macrocell (ETM)
8-Region for Instruction
Trace

Instrumentation
Debug Access Trace Macrocell
Port: JTAG or (ITM ) for Data
Serial Wire Trace via Single
Wire Output

Data Watch Point

and Trace Unit (DWT) Flash Patch &
4x Data Watchpoints Breakpoint Unit
& 8x Hardware
Event Monitors Breakpoints

1x AHB-Lite Buses
2x AHB-Lite Buses
SYSTEM (SRAM & Fast Peripherals)
I_CODE (Instruction Code Bus)
1x APB Bus
D_CODE (Data / Coefficients Code Bus)
ARM Peripheral Bus (Internal & Slow Peripherals)

optional blocks, please consult your silicon manufacturers data sheet

5
ARM Cortex-M3 - Designed for Performance
Relative DMIPS/MHz
 High Performance 1,4
1,2
 High efficiency processor core – 1.25 DMIPS/MHz
1
 Advanced instructions for data manipulation 0,8
 Single Cycle Multiply 0,6
 Hardware Division 0,4
 Bit Field Manipulation 0,2

 Exceptional performance at low frequency 0

ARM7 (Thumb) ARM7 (ARM) Cortex-M3

 Excellent Code Density Relative Code Size

1,6
 Thumb-2 Instruction Set Architecture (ISA)
1,4
 Optimized applications for performance and code 1,2
size 1
 32-Bit code performance 0,8

 16-Bit code density 0,6

0,4
 No interworking required between code objects 0,2
0
ARM7 (Thumb) ARM7 (ARM) Cortex-M3

6
ARM Cortex-M3 - Designed for Low Power
 Cortex-M3 features architected support for sleep states
 Enables ultra low-power standby operation
 Critical for extended life battery based applications
 Includes very low gate count Wake-Up Interrupt Controller (WIC)

Power Management Unit  Sleep

 CPU can be clock gated
 NVIC remains sensitive to interrupts
Cortex-M3
Wake-up  Deep sleep
Deep  WIC remains sensitive to selected interrupts
Sleep
 Cortex-M3 inc. NVIC can be put into state
retention
WIC
NVIC
 WIC signals wake-up to PMU
 Cortex-M3 can be woken almost instantaneously
Wake-up  React to critical external events
sensitive
Interrupts
External interrupts

7
 ARM Cortex-M3 - Designed for Robustness
Cortex-M3 supports design of robust applications

 Processor Modes
 Separation of main and interrupt code
 Privilege Levels
 Separation of RTOS and user application
 NMI
 Inform processor of critical events
 SYSTICK
fRFMEA
 Protected system timer for pre-empting RTOS analysis


f
Fixed Memory Map R
D
 MPU* ARM
Cortex-
I
fRCPU_a
 Separation of user application tasks M3 rmcm3
 Fault Robust Observation Interface*
 IEC61508 standard SIL3 certification

CM3
*optional busses

8
Coresight™ Debug & Trace
 ARM CoreSight is a complete on-chip debug and real-time trace solution for
the entire system-on-chip (SoC)
 Configurable to adapt for market requirements
 Debug components can be configured or even
removed (check device manufacturer data sheet)

 Enhanced debugging modes and features

 Up to 8 (6 Instructions + 2 Literal) HW Breakpoints
 Debug Access Port (DAP) allows memory access
while processor is running
 Up to 4 Data Watch Points (DWT)
 Event Counters (DWT)

 Serial Wire Debug (SWD) Mode

 2 wire interface
 Offers extra functionality over JTAG using less I/O
 Serial Wire Viewer (SWV)
 Real-time trace with no extra trace hardware, pins or
silicon overhead
 Embedded Trace Macrocell
 Instruction Trace using 4-bit port

9
 Introduction to the ARM® Cortex™-M Architecture

CORTEX-M1

10
ARM Cortex-M1
 Soft processor for FPGA
 Upwards compatible with Cortex family on
ASIC/ASSP/MCU
 3 stage pipeline
 Delivers 0.8 DMIPS/MHz
 Capable of up to 200MHz

 Designed for synthesis on multiple FPGA

types, e.g:
 Actel ProASIC3, Actel Igloo and Actel Fusion
 Altera Cyclone-III, Altera Stratix-III
 Xilinx Spartan-3, Xilinx Virtex-5.

11
ARM Cortex-M1 Processor Features
 A 3-stage, 32-bit RISC processor
 Highly configurable to enable design trade-offs
 Retains the same programmers model for software simplicity

 Tightly Coupled Memories

 Internal FPGA block RAM used as single-cycle access memory
 ITCM, DTCM configurable from 0k to 1024kBytes

 Configurable debug
 JTAG or reduced pin-count SWD interface
 Full – 2 watchpoints, 4 breakpoints
 Small – 1 watchpoint, 2 breakpoints
 None – removable for cost reduction and security

12
ARM Cortex-M1 Processor Features (2)
 Integrated Interrupt Controller
 Fast interrupt response
 Configurable 1, 8, 16, 32
 Software programmed priority levels (1-4)
 Non-Maskable Interrupt

 Multiplier
 Fast option uses FPGA DSP blocks
 Small option uses adder to save area, can use DSP blocks
 Program function is the same with either - no need for software modifications

 AMBA AHB-lite 32-bit bus interface

 Connection to external memory and peripherals

 Big or Little Endian

 Synthesis time configurable

13
ARM Cortex-M1 Speed and Area
 Results below are to give a guideline for MHz and area
 The nature of FPGA implementation means results may change per system
 The results will also change as tools and FPGA evolve

 These are speed targeted synthesis run results

 For smallest configuration (0k TCM, no debug)
 Assuming fastest commercial speed grade

FPGA type Example Speed Area (LUTS)

65nm Altera Stratix III Xilinx Virtex-5 200 MHz 1900

90nm Altera Stratix II Xilinx Virtex-4 150 MHz 2300
65nm Altera Cyclone III 100 MHz 2900
90nm Altera Cyclone II Xilinx Spartan-3 80 MHz 2600
130nm Actel ProASIC3 Actel Fusion 70 MHz 4300 tiles

14
ARM Cortex-M1 Instruction Set
 Cortex-M1 implements an ISA based primarily on Thumb
 The high density 16-bit ISA introduced in ARM7TDMI
 Cortex-M1 includes a few Thumb-2 system instructions
 To allow operation in Thumb state only
 Enables binary upwards compatible with Cortex-M3

Thumb Thumb-2
User code, compiler generated OS & system
ADC ADD ADR AND ASR B NOP
BIC BL BX CMN CMP SEV WFE
EOR LDM LDR LDRB LDRH LDRSB WFI YIELD
LDRSH LSL LSR MOV MUL MVN DMB
NEG ORR POP PUSH ROR RSB DSB
SBC STM STR STRB STRH SUB ISB
SVC TST BKPT BLX CPS CPY MRS
REV REV16 REVSH SXTB SXTH UXTB MSR
UXTH
Cortex-M1 ISA
15
 Introduction to the ARM® Cortex™-M Architecture

CORTEX-M0

16
ARM Cortex-M0 Processor
 The smallest, lowest power ARM processor ever
 A third of the area of ARM7TDMI-S
 85 μW/MHz, 12K gates *

 Von-Neumann bus architecture

 3-stage pipeline
 Delivers 0.9 DMIPS/MHz

 Configurable nested vectored interrupt controller

(NVIC)
 Optional Wake-up Interrupt Controller (WIC)
 Configurable Debug

 Binary and tools upwards compatible with ARM

Cortex-M3 processor

* Implemented on 180ULL with ARM Physical IP

17
ARM Cortex-M0 Processor Features
 Cortex-M0 RTL is configurable
 Tune for your application
 Check device manufacturer data sheet
 Consistent programmer’s model
 Software compatibility
 All tools remain compatible
 Integrated Interrupt Controller (NVIC)
 1, 8, 16, 24 or 32 interrupts
 Multiplier options
 Fast or small (1 or 32 cycle)
 Optional OS extensions
 SYSTICK Timer
 PendSV (Pending System Call)
 Configurable debug
 4 or 2 breakpoints, 2 or 1 watchpoints
 JTAG or SWD interface

18
Energy Efficiency
 Cortex-M0 designed for excellent power efficiency
 Significantly less activity required to match 8/16-bit device performance
 Fast interrupt response minimizes time in active state

 Architected for ultra low power deep sleep

 Excellent static power results using ARM Physical IP Metro 180ULL libraries and PMK
 Easy integration to power management unit via Wake-up Interrupt Controller

ARM Cortex-M0 8-bit or 16-bit

EFFICIENT
ENERGY

ENERGY
Power

Power

COST
Time Time
Lower energy for an identical task

19
Architected Sleep States
 Cortex-M0 processor supports ultra low-power standby implementation
 Critical for extended life battery-based applications
 Includes very low gate count Wake-Up Interrupt Controller (WIC)

20
ARM Cortex-M0 Instruction Set
 Cortex-M0 implements an ISA based primarily on Thumb
 The high density 16-bit ISA introduced in ARM7TDMI
 Cortex-M0 includes a few Thumb-2 system instructions
 To allow operation in Thumb state only
 Enables binary upwards compatible with Cortex-M3

Thumb Thumb-2
User code, compiler generated OS & system
ADC ADD ADR AND ASR B NOP
BIC BL BX CMN CMP SEV WFE
EOR LDM LDR LDRB LDRH LDRSB WFI YIELD
LDRSH LSL LSR MOV MUL MVN DMB
NEG ORR POP PUSH ROR RSB DSB
SBC STM STR STRB STRH SUB ISB
SVC TST BKPT BLX CPS CPY MRS
REV REV16 REVSH SXTB SXTH UXTB MSR
UXTH
Cortex-M0 ISA
21
 Introduction to the ARM® Cortex™-M Architecture

CORTEX-M - ARCHITECTURE

22
ARM Cortex-M - Designed for Ease of Use

C
 Virtually everything can be written in C/C++

 No need for assembler in top level interrupt handlers

 Easy to use atomic bit twiddling

 Fast, fully deterministic ISR entry with hardware stacking

on interrupt entry

 Simpler programmer’s model with state manipulation

handled in hardware

 Memory Map, NMI and SYSTICK defined and integrated

enabling better code reuse
 Eases portability of applications and RTOS

23
ARM Cortex-M Processors
 Cortex-M family optimised for deeply embedded
 Microcontroller and low-power applications

24
Processor Mode

 Handler Mode
 Used to handle exceptions. The processor returns to Thread mode when it has
finished exception processing.
 Thread Mode
 Used to execute application software. The processor enters Thread mode when it
comes out of reset.

 In Thread mode, the CONTROL register controls whether software execution is

privileged or unprivileged, see CONTROL register. In Handler mode, software
execution is always privileged.
 RTX is using processor modes

25
 Privilege Levels

 Unprivileged
The software:
 has limited access to the MSR and MRS instructions, and cannot use the CPS
instruction
 cannot access the system timer, NVIC, or system control block
 might have restricted access to memory or peripherals.
 Unprivileged software executes at the unprivileged level

 Privileged
 The software can use all the instructions and has access to all resources.

Not available in Cortex-M0 / Cortex-M1

26
Register File
Thread/Handler Thread  All registers are 32-bit wide
R0
R1
 13 general purpose registers
R2  R0 - R7 are accessible by any instruction
R3  R8 - R12 are accessible to a few 16-bit instructions
R4 and to all 32-bit instructions
R5
R6  3 registers with special meaning/usage
R7  R13 - Stack Pointer (SP)
R8
R9  2 banked copies - Main and Process
R10  R14 - Link Register (LR)
R11
R12
 R15 - Program Counter (PC)
R13 (MSP) R13 (PSP)  Special-purpose registers
R14 (LR)
PC
 PSR
PSR  PRIMASK
 FAULTMASK
PRIMASK
FAULTMASK*
 BASEPRI
BASEPRI*  CONTROL
CONTROL
*Not available in Cortex-M0 / Cortex-M1

27
Program Status Registers
 PSR - Program Status Register combines
 APSR - Application Program Status Register
 Negative, Zero, Carry, OVerflow, Q-Sticky Saturation Flag
 IPSR - Interrupt Program Status Register
 ICI/IT – Interrupt Continuable Instruction, IF-THEN instruction status
 Thumb – Always 1
 EPSR - Execution Program Status Register
 Exception Number – Indicates which exception processor is handling
 CPU Instructions MSR and MRS allow access (together or separate)
 For example: MSR PSR, r0
MRS r1, IPSR

APSR N Z C V Q
IPSR EXCEPTION NUMBER
EPSR ICI/IT T ICI/IT

PSR N Z C V Q ICI/IT T ICI/IT EXCEPTION NUMBER

28
Memory Access
 The Cortex-M3 has an internal Harvard architecture
 Separate instruction and data interfaces

 The internal bus matrix converts the internal Harvard to 3 AHB-Lite

interfaces
 I-Code – Instruction accesses to the Code memory space
 D-Code – Data accesses to Code memory space
 System – All accesses to System memory space

 In a typical system:
 Instructions stored in Code space (in Flash)
 SRAM accessed across System bus

 This allows the interrupt latency to be minimized

 The exception vector is fetched over the ICode bus
 In parallel, the processor state is saved over the System bus

29
Memory Map
 Linear 4GB memory map
 Fixed map required to host system components and simplify implementation
 Bus Matrix partitions memory access via the AHB and PPB buses
FFFFFFFF
Vendor Specific
E0100000
APB External PPB
E0040000
M3 Instruction SCS + NVIC
E0000000
Core Data

External Device 1GB

Bus Matrix INTERNAL PPB
A0000000
with SYSTEM
SYSTEM AHB
AHB
Debug Bit-Bander
Debug ICODE AHB External RAM 1GB
Aligner
and Patch DCODE AHB EX
60000000

BB
Peripheral ½GB
40000000

EX+BB
RAM ½GB
20000000
EX = Code execution support
HX = High performance code execution support HX
Code ROM/RAM ½GB
00000000
BB = Bit banding support

30
Thumb-2 Technology
 Thumb-2 ISA was introduced in ARMv7 architecture

 Original16-bit Thumb instructions maintain full compatibility with existing code

+
 New 16-bit Thumb instructions for improved program flow
+
 New 32-bit Thumb instructions for improved performance and code size.
One 32-bit instruction replaces multiple 16-bit opcodes.
32-bit instructions are handled in the same mode ~ no interworking required

ARM

Thumb

Thumb-2

31
Software Compatibility
 Cortex-M0/M1 implements an ISA based primarily on Thumb
 The high-density 16-bit instruction set introduced in ARM7TDMI

 Cortex-M0/M1 includes a few Thumb-2 system instructions

 Enables Cortex-M0/M1 to operate in Thumb state only
 Enables binary upwards compatible with Cortex-M3

 Cortex-M3 implements Thumb-2

Thumb-2

Thumb upwards compatibility

Thumb®

ARM7 class ARM9 class Cortex-M0 Cortex-M3 Cortex-R4 Cortex-A9

32
Instruction Set Comparison
ADC ADD ADR AND ASR B CLZ

BFC BFI BIC CDP CLREX CBNZ CBZ CMN

CMP DBG EOR LDC

LDMIA BKPT BLX ADC ADD ADR LDMDB LDR LDRB

LDRBT BX CPS AND ASR B LDRD LDREX LDREXB

LDREXH DMB BL BIC LDRH LDRHT LDRSB

LDRSBT DSB CMN CMP EOR LDRSHT LDRSH LDRT

MCR ISB LDR LDRB LDM LSL LSR MLS

MCRR MRS LDRH LDRSB LDRSH MLA MOV MOVT

MRC MSR LSL LSR MOV MRRC MUL MVN

NOP NOP REV MUL MVN ORR ORN ORR PLD

PLDW REV16 REVSH POP PUSH ROR PLI POP PUSH

RBIT SEV SXTB RSB SBC STM REV REV16 REVSH

ROR SXTH UXTB STR STRB STRH RRX RSB SBC

SBFX UXTH WFE SUB SVC TST SDIV SEV SMLAL

SMULL WFI YIELD SSAT STC STMIA

CORTEX-M0
STMDB STR STRB STRBT

STRD STREX STREXB STREXH STRH STRHT STRT

SUB SXTB SXTH TBB TBH TEQ TST

UBFX UDIV UMLAL UMULL USAT UXTB UXTH

WFE WFI YIELD IT

CORTEX-M3
Present in ARM7TDMI

33
Nested Vector Interrupt Controller
 NVIC is a core peripheral
 Consistent between Cortex-M cores
 Tailored towards fast and efficient interrupt handling
 Number of interrupts can be configured by device manufacturer
 1 ... 240 interrupt channels for M3
 1 ... 32 interrupt channels for M0
 Each peripheral has its own interrupt vector(s)
 8 – 256 interrupt priorities (1 - 4 Cortex M1/M0)
 Configured via memory-mapped control registers
 Exceptions/interrupts processed in Handler mode
 Supervisor privilege
 Interruptible LDM/STM (and PUSH/POP) for low interrupt latency
 Continued on return from interrupt
 Non Maskable Interrupt (NMI)

34
Nested Vector Interrupt Controller
 When an interrupt occurs: APB
Vendor Specific
External PPB
FFFFFFFF

E0100000

E0040000


M3 Instruction SCS + NVIC

The exception vector is fetched over the ICODE bus

E0000000
Core Data

External Device 1GB

Bus Matrix INTERNAL PPB


A0000000
with SYSTEM
SYSTEM AHB
AHB

In parallel, the processor state is saved over the SYSTEM bus Debug
Debug
Bit-Bander
Aligner
and Patch
ICODE AHB
DCODE AHB EX
External RAM 1GB

60000000
Peripheral ½GB


BB
40000000

Automatic save and restore of processor state EX = Code execution support

EX+BB
RAM

Code ROM/RAM
½GB
20000000

½GB
HX = High performance code execution support HX


00000000
BB = Bit banding support

{PC, xPSR, R0-R3, R12, R14}

 Provides low latency interrupt/exception entry and exit
 Allows handler to be written entirely in ‘C’

 Interrupt Latency for Cortex M3 max. 12 Cycles

 Interrupt Latency into pending interrupts 6 Cycles

35
Vector Table
 ARMv7M architecture implements a re-locatable vector table
 Contains initial stack pointer value
 Contains the address of RESET handler
 Contains the address of the function to execute for a particular handler
 The first sixteen entries are special with the others mapping to specific interrupts

0x40 PERIPHERAL / USER DEFINED

0x34 DEBUG MONITOR

SVC / SWI HANDLER
0x30 SVCALL

0x18 USAGE FAULT

DATA + PREFETCH ABORTS UNDEFINED INSTRUCTIONS
0x14 BUS FAULT
0x10 MEM MANAGE
MPU PROTECTION FAULTS
0x0C HARD FAULT
0x08 NMI
NON MASKABLE INTERRUPT RESET HANDLER Address
0x04 RESET
0x00 INITIAL STACK POINTER VALUE
MSP RESET VALUE

36
Exception & Pre-emption Ordering
 Exception handling order is defined by programmable priority
 Reset, Non Maskable Interrupt (NMI) and Hard Fault have predefined pre-emption.
 NVIC catches exceptions and pre-empts current task based on priority

Exception Name Priority Descriptions

1 Reset -3 (Highest) Reset
Start-up Handlers
Fault Mode &

2 NMI -2 Non-Maskable Interrupt

3 Hard Fault -1 Default fault if other hander not implemented
4 MemManage Fault Programmable MPU violation or access to illegal locations
5 Bus Fault Programmable Fault if AHB interface receives error
6 Usage Fault Programmable Exceptions due to program errors

11 SVCall Programmable System SerVice call

Handlers
System

12 Debug Monitor Programmable Break points, watch points, external debug

14 PendSV Programmable Pendable SerVice request for System Device
15 Systick Programmable System Tick Timer

16 Interrupt #0 Programmable External Interrupt #0

Handlers
Custom

… … … …
… … … …
… … … …
255 Interrupt #239 Programmable External Interrupt #239

37
Exception Model
 Exceptions cause current machine state to be stacked
 Stacked registers conform to Embedded Application Binary Interface (EABI)
 Exception handlers are trivial as register manipulation carried out in
hardware
 No assembler code required
 Simple ‘C’ interrupt service routines
void MY_IRQHandler(void) { /* my handler */ }

PREVIOUS TOP-OF-STACK VALUE

OLD SP POINTED HERE
PSR
PC
LR
R12
R3
R2
R1
NEW SP POINTS HERE
R0

38
Interrupt Response – Tail Chaining
Highest

IRQ1

IRQ2

ARM7TDMI
Push ISR 1 Pop Push ISR 2 Pop
Interrupt Handling
26 Cycles 16 Cycles 26 Cycles 16 Cycles

Cortex-M3 65% Saving

Push ISR 1 ISR 2 Pop
Interrupt Handling Cycle Overhead
12 Cycles 6 Cycles 12 Cycles
Tail-Chaining

ARM7TDMI Cortex-M3
26 cycles from IRQ1 to ISR1  12 cycles from IRQ1 to ISR1
(up to 42 cycles if in LSM) (Interruptible/Continual LSM)
 42 cycles from ISR1 exit to ISR2 entry  6 cycles from ISR1 exit to ISR2 entry
 16 cycles to return from ISR2  12 cycles to return from ISR2

39
Interrupt Response – Late Arriving
Highest

IRQ1

IRQ2

ARM7TDMI
Push Push ISR 1 Pop ISR 2 Pop
Interrupt Handling
26 Cycles 26 Cycles 16 Cycles 16 Cycles

Cortex-M3
Push ISR 1 ISR 2 Pop
Interrupt Handling
12 Cycles 6 Cycles 12 Cycles
Tail-Chaining

ARM7TDMI Cortex-M3
26 cycles to ISR2 entered 12 cycles to ISR entry
 Immediately pre-empted by IRQ1 Parallel stacking & instruction fetch
Additional 26 cycles to enter ISR1. Target ISR may be changed until last
 ISR 1 completes cycle (PC is set)
Additional 16 cycles return to ISR2. When IRQ1 occurs new target ISR set

40
Interrupt Response – Pop Pre-emption
Highest

IRQ1

IRQ2

ARM7TDMI
ISR 1 Pop Push ISR 2 Pop
Interrupt Handling
16 Cycles 26 Cycles 16 Cycles

Cortex-M3
ISR 1 ISR 2 Pop
Interrupt Handling
6 Cycles 12 Cycles
Abandon Pop (1-12 Cycles) Tail-Chaining

ARM7TDMI Cortex-M3
Load multiple not interruptible  Hardware un-stacking interruptible
 Core must complete the recovery of  If interrupted only 6 cycles required
the stack then re-stack to enter the ISR to enter ISR2

41
SYSTICK Timer
 Simple 24 Bit down counter
 4 Registers
 CTRL - Control and Status
 LOAD – Reload Value
 VAL – Current Value
 CALIB - Calibration Value

 Exception Vector #15

 Accesible from Privileged Mode

 Can be protected from user application
 Makes porting OS and software easier, because SYSTICK
timer will be the same across different Cortex-M products

42
Atomic Bit Manipulation
 Internal and peripheral data represented as individual bits Cortex-M3 Memory Map
without the processing overhead normally associated with
this type of action.

 For deterministic systems with lots of peripheral data, such

as microcontrollers, atomic bit manipulation can compact
some types of data by 32 times

Alias Memory
32-Bit Word Alias 0
1

Real Memory
01

43
Bit Manipulation – BFI / BFC
 Insert or clear any number of adjacent bits anywhere in a register
 Ideal for modifying or stripping packet headers
 BFI - Bit Field Insert
 BFC - Bit Filed Clear
Packet stored in R1
1. Packet comes in 1 1 4 4 8 8 C C
32 0
Contents of R0
2. Want to insert data in
front of packet 3 3 5 5 A A C C
32 0
Example:
R0[15:0] into R1[31:16]
[ BFI R1, R0, #16, #16 ]
3. Insertion is executed by
hardware immediately
A A C C 8 8 C C
32 16 0
Resulting Packet in R1

Note: BFC will clear ‘n’ adjacent bits in a register, starting at bit ‘m’.
e.g.: BFC R0, #4, #8 will clear a byte starting from bit 4.

44
 Memory Protection Unit (MPU)
 MPU provides access control for various
memory regions

 Zero Latency Memory Protection

 8 register-stored regions
 Same regions used for instructions and data
 Minimum region size 32 Bytes (max 4GB)
 No address translation or Page Tables

 Configured via memory-mapped control

registers

Not available in Cortex-M0 / Cortex-M1

45
OMAP Processor
OMAP (Open Multimedia Applications Platform) is a family of image/video
processors that was developed by Texas Instruments. They are proprietary system
on chips (SoCs) for portable and mobile multimedia applications. OMAP devices
generally include a general-purpose ARM architecture processor core plus one or
more specialized co-processors. Earlier OMAP variants commonly featured a
variant of the Texas Instruments TMS320 series digital signal processor.

 It is developed byTexas Instruments.

 It is a series of image/video processors.
 OMAP processor is a category of proprietary SOCs for portable and mobile
multimedia applications.
 The OMAP architecture provides a means to coordinatedual processors
across the two basic components of thewireless appliance and to
seamlessly take advantage ofthe unique capabilities of each

OMAP family

The OMAP family consists of three product groups classified by performance and
intended application:

 high-performance applications processors

 basic multimedia applications processors

 integrated modem and applications processors

OMAP Architecture
OMAP Processor

High performance application processors

Used in smart phones which are powerful enough to run significant operating
systems such as Linux, Android, Symbian ,support connectivity to personal
computers and support various audio and video applications.
Basic multimedia application processors

: marketed only to handset manufacturers which are intended to be highly

integrated, low cost chips. Used as digital media coprocessors for mobile devices
with high megapixel digital still video cameras.

Integrated modem and applications processors:

marketed only used by handset manufacturers. They are highly integrated for use
in very low-cost cell phones.

High performance application processors

Basic multimedia application processors Integrated modem and applications processors

Advantage

 High performance
 Low power consumption
 PC like web browsing
 Faster user interfaces
 More flexibility
 Full HD 1080p30 multi standard video encode or decode
 High security
 Less time to market
 Slim and light weight designs

Applications

 Industrial automation
 Medical appliances
 Auto motives
 Mobile phones
 Multimedia/gaming applications
 Consumer