1.

ARM Microcontroller Introduction

2. ARM Cortex-M4 - Introduction

3. ARM Cortex-M4 - Key Features and Applications

4. Cortex-M4 Block diagram & Architecture.

5. Registers and Memory

6. Operating modes and states

7. Low power characteristics - Cortex-M4

ARM Microcontroller Introduction:
 Abbreviation of ARM: Advanced RISC Machines.

 ARM doesn’t develop microcontrollers silicon chip but it only provides IP core (Intellectual Property)
for a microprocessor.

 The designs ARM provides are known as Intellectual Property (IP).

 The business through which it sells the design to the various manufacturer is known as IP licensing.
ARM Embedded System
 CLASSIC ARM
PROCESSOR

"The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions. Thumb instructions are 16 bits long, and have a corresponding 32-bit ARM
instruction that has the same effect on processor model."

Code density refers loosely to how many microprocessor instructions it takes to perform a
requested action, and how much space each instruction takes up. Generally speaking, the less
space an instruction takes and the more work per instruction that a microprocessor can do, the
more dense its code is.
ARM Cortex-M4
INTRODUCTION to ARM Cortex-M4

 It consists of 32-bit processor cores.

 All internal registers such as general purpose and special function, are of 32-bit.

 Moreover, data paths, functional units ( ALU) which perform arithmetic (addition, subtraction, multiplication, etc)
and logical operations ( AND, OR, less than, greater than, etc) on data are also of 32-bit size.

 Bus interfaces such as memory/data buses are also 32-bit.

 Hence, size of functional unit, data path, internal registers, interfacing buses, memory address range are the main
factors that define the 32-bit size of ARM Cortex-M4 processor.

 The size of processor in terms of bits defines the maximum addressable range or the maximum address range it can
handle.

 For example, ARM Cortex-M4 microcontrollers can handle 2^32 = 4GB of memory address space
ARM Cortex-M4 is a processor core specifically designed for :

 Efficient and high-performance execution of signal processing tasks and low power consumption.
 Promised - low interrupt latency.
 Support for Floating Point arithmetic.
 Most suitable for real time application which requires a very quick interrupt response (it can not afford to delay)

ARM Cortex-M4 is suitable for a variety of applications in embedded systems:

 Automotive: Used in automotive control systems, including engine control units (ECUs) and
Advanced driver assistance systems (ADAS).
 Industrial: Employed in industrial automation, motor control, and sensor processing.
 Consumer Electronics: Found in audio processing, wearable devices, and home automation systems.
 Medical: Applied in medical devices requiring reliable signal processing and control.
Key Features

Architecture:
 Based on the ARMv7-M architecture.
 Harvard architecture with separate instruction and data buses.
 Thumb-2 instruction set for improved code density and performance.

Performance:
 Operates at up to 200 MHz.
 32-bit processor core with a 3-stage pipeline (FETCH _DECODE_ EXECUTE).
 Single-cycle multiply and hardware divide for efficient mathematical operations.

Digital Signal Processing (DSP) Capabilities:

 Enhanced with SIMD (Single Instruction Multiple Data) instructions.
 Hardware support for signal processing and control functions.
 Optional Floating Point Unit (FPU) for single-precision (32-bit) operations.

Memory:
 Up to 4 GB addressable memory space.
 Support for various memory configurations including Tightly Coupled Memory (TCM), on-chip
Flash, SRAM, and external memory interfaces.
Peripherals
 Extensive range of integrated peripherals including timers, analog-to-digital converters, digital-to-analog
converters, communication interfaces (USART, I2C, SPI), and more.
 Interrupts with nested vectored interrupt controller (NVIC) for fast interrupt handling.

Power Efficiency:
 Designed for low-power operation with various power-saving modes.
 Suitable for battery-operated devices and applications requiring energy efficiency.

Supports Sleep Modes

 Up to 240 Wake-up Interrupts
 Integrated WFI (Wait For Interrupt) and WFE (Wait For Event) Instructions and Sleep on Exit capability.
 Sleep & Deep Sleep Signals.

Multiple high-performance bus interfaces

 Low-cost debug solution with the optional ability to:
.  implement breakpoints and code patches
 implement watch points, tracing, and system profiling
 support printf style debugging.
 bridge to a Trace Port Analyzer (TPA)

Optional Memory Protection Unit (MPU).

 Defines memory regions and their access permissions.

 Enhances security and reliability by preventing unauthorized access

Interfaces: The processor has the following external interfaces:

 multiple memory and device bus interfaces

 ETM interface
 trace port interface
 debug port interface.
Development Ecosystem

Development Tools: Supported by a wide range of development tools including ARM's Keil MDK,
IAR Embedded Workbench, and open-source tools like GCC.

RTOS Support: Compatible with various real-time operating systems (RTOS) such as FreeRTOS,
RTX, and others.

Extensive Documentation and Community Support: Comprehensive documentation, community

forums, and technical support available to assist developers.
Cortex-M4 Main Components
Processor Core:

ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.

FPU (Floating Point Unit): Optional unit for single-precision (32-bit) floating-point calculations.

Hardware support for addition, sub, mul, division and square root.

Registers: Includes a set of general-purpose and special-function registers for data storage and manipulation .

Harvard Architecture: Separate instruction and data buses for simultaneous access.

Pipeline: Fetch Stage: Retrieves instructions from memory. Decode Stage: Decodes the fetched instructions.
Execute Stage: Executes the decoded instructions using the ALU and FPU.

Support for big endian and small endian bytes access.

Memory Interfaces:

 Code Bus: Dedicated bus for instruction fetches.

 System Bus: Handles data transfers between the core and memory/peripherals.
 Data Bus: Dedicated bus for data access.
Bus Interfaces:

 AHB-Lite Bus Interface: High-performance bus interface for connecting to system memory and peripherals.
 APB (Advanced Peripheral Bus) Interface: Used for connecting to lower-speed peripherals.

Memory Protection Unit (MPU):

 MPU: Provides memory protection features to enhance security and reliability.

 Define multiple memory regions with configurable attributes, helping prevent unexpected or unauthorized access.

Nested Vectored Interrupt Controller (NVIC):

 NVIC: Manages interrupt handling with low latency and flexible priority levels.
 Interrupt Lines: Supports up to 240 interrupt lines.
 Priority Levels: Configurable priority levels for interrupts.

Wake-Up Interrupt Controller (WIC):

 Provide ultra low power sleep mode support.

 Its main function is to allow the system to conserve energy by entering a low-power state while still being able to
respond to specific interrupt signals that require immediate attention, effectively "waking up" the system.
Debug Interface: Supports debugging through JTAG and Serial Wire Debug (SWD) interfaces.

Integrated Peripherals:

 Timers: Multiple timer modules for various timing and counting functions.
 ADC (Analog-to-Digital Converter): Converts analog signals to digital data.
 DAC (Digital-to-Analog Converter): Converts digital data to analog signals.
 Communication Interfaces: Includes USART, I2C, SPI for serial communication.

Clock and Reset Control:

 Clock Control Unit: Manages the clock signals for the processor and peripherals.
 Reset Control Unit: Handles reset signals to initialize or restart the processor and peripherals.

Power Management:

 Power Control Unit: Manages power-saving modes and dynamic voltage and frequency scaling
(DVFS) for energy efficiency.
Trace Interface: Includes the Instrumentation Trace Macrocell (ITM) and Data Watchpoint and Trace (DWT) units
for real-time trace and debugging.

Embedded Trace Macrocell:

 It is a debug and trace component.

 It allows developers to trace program execution in real-time, providing insights into the behavior of the code
running on the microcontroller.
Instrumentation Trace Macrocell:

 It is another debug and trace component available in ARM Cortex-M4 processors.

 ITM provides a way to output trace information for debugging purposes, typically using a SWO (Single
Wire Output) pin for trace data.
Data Watch point and Trace (DWT) :

 It is a debugging tool that enables various data and event tracing functionalities.
 DWT uses a set of comparators and counters to monitor and capture data events and program execution
metrics

** Data Watch points: Allows the monitoring of specific memory addresses for read or write operations.
Flash Patch and Breakpoint (FPB) It is a powerful debugging feature that allows developers to set
breakpoints and patch program code in flash memory.

 Breakpoint Support: The FPB unit can set hardware breakpoints in flash memory, which can be used
to halt program execution at specific points for debugging.

 Patch Functionality: FPB allows for patching instructions in flash memory with new instructions,
enabling developers to test fixes or changes without rewriting the flash memory.

 Eight Hardware Breakpoints: The Cortex-M4 supports up to eight hardware breakpoints, which
are more than sufficient for most debugging tasks.

Trace Port Interface Unit (TPIU) :

 It facilitates the output of trace data for debugging purpose

 TPIU collects trace data from ITM, DWT, and ETM and outputs it via a trace port.

 The TPIU acts as a bridge between the trace sources within the Cortex-M4 (ITM, DWT, ETM) and
the external trace capture tools.
Processor Core:

 ARMv7-M Architecture: The Cortex-M4 is based on the ARMv7-M architecture, which is optimized for low power and
high performance.
 32-bit Core: It is a 32-bit processor, capable of handling 32-bit wide data paths and operations.

Pipeline:
 3-Stage Pipeline: The processor employs a 3-stage pipeline (fetch, decode, execute), which helps improve instruction
throughput and performance.

Instruction Set:
 Thumb-2 Technology: Utilizes the Thumb-2 instruction set, providing a mix of 16-bit and 32-bit instructions. This
enhances code density and performance, making it efficient in terms of memory usage and processing power.

Flash Memory
 Non-volatile Storage: Used to store the firmware code and can be programmed and erased in blocks.
 Size: Varies from model to model, ranging from a few kilobytes to several megabytes.

SRAM (Static RAM)

 Volatile Memory: Used for runtime data storage, such as variables and stack space.
 Size: Also varies, typically ranging from a few kilobytes to several hundred kilobytes.
Memory Architecture

1.Harvard Architecture:

Separate Instruction and Data Buses: The Cortex-M4 uses a Harvard architecture with separate buses for
instructions and data, allowing for simultaneous access to instructions and data, which improves performance.

2.Memory Map:
Unified Address Space: The Cortex-M4 has a unified address space for code, data, and peripherals,
simplifying the memory management.

3.Memory Protection Unit (MPU):

Security and Protection: The MPU provides memory protection features, allowing for the separation of tasks
and enhancing the security and reliability of applications.
Performance Features

1.Digital Signal Processing (DSP):

 DSP Instructions: Includes specialized DSP instructions such as Single Instruction Multiple Data
(SIMD) instructions, which enable efficient processing of mathematical and signal processing
tasks.
 Optional Floating Point Unit (FPU): The Cortex-M4 optionally includes a hardware Floating
Point Unit (FPU) for single-precision (32-bit) floating-point arithmetic, accelerating computation-
heavy applications.

2.Interrupt Handling:

 Nested Vectored Interrupt Controller (NVIC): The NVIC supports low-latency interrupt
processing with up to 240 interrupt lines and priority levels, enabling responsive and flexible
interrupt handling.
Power Management

Low Power Modes:

 Sleep and Deep Sleep Modes: It help to conserve power when the processor is idle.
Dynamic Voltage and Frequency Scaling (DVFS):
 Power Efficiency: DVFS allows the adjustment of voltage and frequency based on the processing
needs, optimizing power consumption without compromising performance.

Peripherals and Interfaces

 Integrated Peripherals: Timers, ADC, DAC

 Interfaces: USART, I2C, SPI: facilitating connectivity with other devices and components.

Debug and Trace

Debug Interface:
 Integrated Debug and Trace.

Instrumentation Trace Macrocell (ITM):

 Real-time Monitoring: ITM enables real-time monitoring and debugging of the processor's operation,
providing valuable insights during development.
 ARM Cortex-M4 Processor
• 32 bit architecture & Harvard bus architecture
• Digital signal controller
• Operates upto 120MHz DSC
• Ultra low power Fast interrupt response
• 512kB flash program memory MAC unit
• 96kB of SRAM data memory Barrel shifter
• 4032 byte of EEPROM data memory Accumulator
• 165 GPIO
• 12 bit ADC
• 2 Analog comparators & 10 bit DAC
• 4 General purpose timers
• 32 bit registers
• 32 bit internal data path
• Integrated memory protection unit
• 3 I2C bus interface
• 32 bit bus interface
• 4GB memory location 2^32=4GB
• Two general purpose PWMs with 6 output each and one motor control PWM
 1) Floating Point Unit(FPU):
 32 bit instructions for single precision data processing operations.
 32 dedicated 32 bit single precision register.
 Decoupled 3 stage pipeline.
 Hardware support for conversion, addition, subtraction, multiplication, division and square root.
. 2) Memories
 Upto 1Mb of flash memory.
 Upto 192+kb of SRAM including 64 kilo bytes of CCM (Core Coupled Memory) data Ram.
 Flexible, Static memory controller, supporting compact flash, SRAM, PSRAM, NOR&, NAND memories.

3) LCD parallel interface

4) Clock, reset and supply management:
 1.8V to 2.6V application supply .
 4 to 26 MHZ crystal oscillator.
 Internal 16MHz factory trimmed RC (1% accuracy).
 32KHz oscillator for RTC with calibration.
 Internal 22KHz RC with calibration.

5) Low Power Operation:

 Sleep, stop and standby modes.
 VBAT supply for RTC, 20*32 bit backup registers, optional 4KB backup SRAM.

6) 3*12 bit , 2.4 MSPS A/D converter, upto 24 channel and 7.2 MSPS in triple interleaved mode,2*12 bit D/A
converter.

7) General purpose DMA:

16 DMA controller with FIFO’s .

8) TIMERS:
 Upto 17 Timer: upto twelve 16 bit and two 32 bit timers upto 168mHz each with upto 4 IC/OC/PWM or
pulse counter and quadrature(incremental) encoder input.

9) DEBUG MODE:
 Serial wire debug (swp), STAG interfaces, Trace macrocell.
10) Up to 140 I/O ports with interrupt capacity:
 Up to 136 fact Digital Outputs up to 84 MHz
 Up to 138 5V tolerant I/Os
11) Up to 15 Communication interfaces:
 Up to 3x12C interfaces(System Management Bus (SMBus) and Power Management Bus (PMBus).
 Up to 4 USART
 Up to 3SPICS (42mbits/s) with muxed full duplexer 128 to achieve audio class accuracy via internal
audio or external clock.
 2xLAN interfaces (2.0B active)
 SDIO- Secure Digital Input Output interfaces
12) Advanced Connectivity:
 USB 2.0 full speed device/host/OTG controller with an chip PLM.
 USB 2.0 high speed/full speed device/host OTG controller with dedicated DMA, on chip full speed
PLU and UPLI.
 10/100 Ethernet MAC with dedicated DMA (Supports IEEE 1588V2 hardware, M11/8M11 )

13) 8 to 14 bit parallel camera interface upto 54 m bytes/second.

14) True random number generator.
15) CRC Calculation unit.
16) 92 bit unique IO.
17) Real-Time Clock & hardware calendar.
 EIGHT MOUNTERS:
 Cortex-M4 with FPU core I-bus, D-bus, S-bus
 DMA1 memory bus
 DMA2 memory bus
 DMA3 peripheral bus
 Ethernet DMA bus
 USB OTG HS DMA Bus
SEVEN SLAVES:
 Internal flash memory 1 code bus
 Internal flash decode bus
 Main internal SRAM(112KB)
 Auxiliary internal SRAM(16KB)
 AHB1 peripherals including AHB to APB bridges and APB peripherals.
 AHB2 peripherals
(Cortex-M4 supports different bus protocols depending on the system configuration. It typically interfaces with the
Advanced High-performance Bus (AHB) or the Advanced Peripheral Bus (APB) in ARM-based systems)
AHB is designed for high-performance communication between high-speed peripherals and memory units.
APB is optimized for lower-speed peripheral communication and is generally used for connecting slower peripherals and
configuration registers.
 FSMC : FSMC is a parallel line interface used to connect microcontrollers to external memories (like
NAND/NOR Flash etc) and transfer data at high speed, it is used in applications that require to process a
large amount of data
 ARM Core Data Flow Model
Load–store architecture is an
instruction set architecture that
divides instructions into two
 It consist of ALU, Barrel shifter, categories:
reg bank, address reg and
instruction decoder 1. Memory access (load and store)

 From reg bank A and B are data Load: instruction copies the data
bus connected. from memory to registers),
Store: instruction copies the data
 A bus to ALU from registers to memory.
B BUS to ALU and Barrel shifter.
and
 Through Rm & Rn register data
sent to ALU and Barrel shifter. 2. ALU operations (which only
occur between registers)
 ALU and Barrel shifter are
combinational circuit, both
operation done in one cycle.
 BARREL SHIFTER

R5=5 R7=8

MOV R7,R5,LSL #2

20
• ARM doesn't have actual shift operations
• Barrel shifter provides the mechanism to carry out the shifting operations.
• ARM has the barrel shifter in the data path
BARREL SHIFTER OPERATIONS
BARREL SHIFTER OPERATIONS
BARREL SHIFTER OPERATIONS
 Cortex-M4 Register Bank

R0-12 are general purpose

registers.

R13-R15 are special

function registers.
General-Purpose Registers (R0-R12)
Purpose: Used for temporary data storage and parameter passing.
Configuration: Directly manipulated in assembly or through inline assembly in C.

Program Counter (PC) –R15

Purpose: Holds the address of the next instruction to execute.
Configuration: The PC is typically manipulated indirectly through instructions that control program flow
(e.g., branches, calls).

Stack Pointer (SP) – R13

Purpose: Points to the top of the stack. The Cortex-M4 supports two stack pointers: Main Stack Pointer
(MSP) and Process Stack Pointer (PSP).
Configuration:
MSP Initialization: The MSP is used during reset and interrupt handling.
PSP Initialization: Used for normal program execution in thread mode.

Link Register (LR) – R14

Purpose: Stores the return address for function calls and exceptions.
Configuration: The LR is automatically set by the processor during function calls and exception
handling.
Application Program Status Register (APSR)
Purpose: Holds the condition flags (Zero, Negative, Carry, Overflow).
Configuration: Flags are set or cleared automatically by arithmetic and logical instructions.

Interrupt Program Status Register (IPSR)

Purpose: Indicates the currently active interrupt or exception.
Configuration: The IPSR is automatically managed by the processor during interrupt handling.

Execution Program Status Register (EPSR)

Purpose: Contains the Thumb state bit and other execution status information.
Configuration: Managed internally by the processor.
 MASK REGISTERS
PRIMASK Register

Purpose: Controls the masking of exceptions with configurable priority levels.

Configuration: The PRIMASK register has a single bit (PRIMASK[0]).
0: No effect.
1: Masks all exceptions except for Non-Maskable Interrupt (NMI) and
HardFault

FAULTMASK Register
Purpose: Masks all exceptions except for NMI.
Configuration: The FAULTMASK register has a single bit (FAULTMASK[0]).
0: No effect.
1: Masks all exceptions except NMI.

BASEPRI Register
Purpose: Sets the base priority for exception handling, masking all exceptions
with a priority value equal to or less than BASEPRI.
Configuration: The BASEPRI register can hold an 8-bit value.
0x00: No effect, all interrupts are allowed.
Other values: Masks interrupts with priority levels equal to or lower than the
specified BASEPRI value.
CONTROL Register: It controls the stack pointer selection and the execution privilege level.

CONTROL[0] (nPRIV):

Defines the privilege level for code execution.

0: Privileged
1: Unprivileged

CONTROL[1] (SPSEL):

Selects the current stack pointer.

0: Main Stack Pointer (MSP)
1: Process Stack Pointer (PSP)

CONTROL[2] (FPCA):

Floating-point context active.

This is used in processors with a Floating Point Unit (FPU).
 GPIO Registers Address
The Arm chips have two types of buses:
• APB (Advanced Peripheral Bus)
• AHB (Advanced High Performance Bus).

The AHB is a high performance bus designed to interface memory and fast I/Os directly to the CPU.
The APB is designed for lower speed and low power consumption memory and peripherals.

Address ranges assigned to Ports of STM32F4xx chip.

 GPIO Port A: 0x4002 0000 - 0x4002 03FF
 GPIO Port B: 0x4002 0400 - 0x4002 07FF
 GPIO Port C: 0x4002 0800 - 0x4002 0BFF
 GPIO Registers Address
.
GPIOx_ODR Output Data Register (x=A,
B,C, ..)

• Bits 31:16 Reserved, must be kept at reset value.

• Bits 15:0 ODRy: Port output data (y = 0..15)
• These bits can be read and written by software.
Direction Register
• In STM Arm the direction register is part of the
GPIOx_MODER which stands for GPIO Mode Register.

• For each GPIO pin, there are two corresponding bits in

the MODER register. These two bits need to be a 00 to
configure the port pin as input and a 01 as output.
•
 Direction Register

• MODERy[1:0]: Port x configuration bits (y = 0..15)

• These bits are written by software to configure the I/O
direction mode.
• 00: Input
• 01: General purpose output mode
• 10: Alternate function mode
• 11: Analog mode
 MEMORY SYSTEM

 Cortex-M4 has a well-defined memory map,

 Optional Memory Protection Unit (MPU) that can enhance the reliability and security of the system by:

 Defining Memory Regions: The MPU can define up to 8 regions, each with specific access permissions
and attributes.
 Access Control: It can control access permissions (read, write, execute) for different regions of memory.
 Fault Handling: Generates faults when illegal memory accesses are detected, allowing for robust error
handling

 4GB linear address space

 Support for little endian and big endian memory systems

Non-Memory Mapped Region:

 Non-memory mapped region includes internal general purpose and special function registers of CPU.

 These registers do not have addresses. We can access them using internal register names in assembly language.

Memory Mapped Region of Microcontrollers:

 The addressable memory space of a microcontroller or microprocessor depends on their address bus width.

 For instance, if we take the example of ARM Cortex M4 32-bit microcontroller, its addressable memory space is
2^32 which is equal to 4 gigabytes of memory.

 Each byte of this memory space has a unique memory address and the Cortex M4 microcontroller can access
each memory location either to read and write data to each memory location.
Memory Mapped Peripherals Registers

In contrast microcontroller internal registers, microcontrollers also have memory mapped I/O region
which belongs to different peripherals of a microcontroller such as GPIO, ADC, UART, SPI, I2C, Timers
and other peripherals that are supported by a specific microcontroller
BYTE: 8 BITS, Word: 4 Byte, Half word: 2 Byte
GPIO Port Mapping

Here is an example of GPIO port mapping in a typical Cortex-M4 microcontroller

(e.g., STM32F4 series):

 GPIOA Base Address: 0x40020000

 GPIOB Base Address: 0x40020400
 GPIOC Base Address: 0x40020800
 GPIOD Base Address: 0x40020C00
 GPIOE Base Address: 0x40021000
 GPIOF Base Address: 0x40021400
 GPIOG Base Address: 0x40021800
 GPIOH Base Address: 0x40021C00
Each GPIO port typically contains multiple registers for configuration, input/output data, and control,
such as:

 GPIOx_MODER: GPIO port mode register

 GPIOx_OTYPER: GPIO port output type register

 GPIOx_OSPEEDR: GPIO port output speed register

 GPIOx_PUPDR: GPIO port pull-up/pull-down register

 GPIOx_IDR: GPIO port input data register

 GPIOx_ODR: GPIO port output data register

 GPIOx_BSRR: GPIO port bit set/reset register

 GPIOx_LCKR: GPIO port configuration lock register

 GPIOx_AFRL: GPIO alternate function low register

 GPIOx_AFRH: GPIO alternate function high register

operating modes and states:

It supports various operating modes and states that help manage power consumption and performance.
Operating Modes: Two primary modes

1. Thread Mode:

 Description: The mode in which the processor executes application code.

 Context: Can be entered on reset or when returning from an interrupt or exception.
 Privileges: Can operate in either privileged or unprivileged level.

2. Handler Mode:

 Description: The mode in which the processor executes exception or interrupt handlers.
 Context: Entered when an interrupt or exception occurs.
 Privileges: Always operates in a privileged level.
Processor States: The Cortex-M4 has several processor states related to power and operational modes.

1. Active State:
 Description: The normal operational state where the CPU executes instructions.
 Power Consumption: Full power.

2. Sleep State:
Sleep Now (Sleep-on-Exit):
 Description: Processor enters sleep mode after exiting an interrupt service routine.
Normal Sleep:
 Description: Entered by executing the WFI (Wait For Interrupt) or WFE (Wait For Event) instructions.
 Power Consumption: Reduced power consumption; the core clock is stopped, but the system clock continues
running.

3. Deep Sleep State:

 Description: Entered by executing the WFI or WFE instructions with the SLEEPDEEP bit set in the System Control
Register (SCR).
 Power Consumption: Significantly lower than in normal sleep; the system clock and other peripherals can be stopped
depending on the implementation.
 Variants: Depending on the implementation, the processor can enter deeper sleep states, such as Power Down or Deep
Power Down, where more peripherals are powered down to save energy
Power Management Features:Cortex-M4 includes several features to manage power consumption effectively:

 SysTick Timer : Can be used to implement a tick-less idle mode in an RTOS to reduce power consumption.
 NVIC : Manages low-latency interrupt handling,
 Sleep and Deep Sleep Modes: Utilize the WFI and WFE instructions to manage low power states.
 Clock Gating: The processor can gate clocks to unused peripherals to save power.

An embedded system using a Cortex-M4 might have a power management strategy as follows:

 Normal Operation: The system runs in Active State executing application code in Thread Mode.
 Idle Periods: When the system is idle, it enters Sleep State using the WFI instruction to reduce power
consumption while waiting for an interrupt.
 Low Power Modes: During longer periods of inactivity, the system enters Deep Sleep State.
 Interrupt Handling: When an interrupt occurs, the processor switches to Handler Mode, processes the
interrupt, and depending on the configuration, either returns to Active State or remains in Sleep State if Sleep-
on-Exit is enabled.
 EXCEPTIONS and INTERRUPTS

Exceptions:

Exceptions are anomalies or unusual conditions that occur during the execution of a program.
They can be due to various reasons like programming errors, hardware failures, or resource limitations.

In the context of processors, exceptions (also called traps or faults) are events that disrupt the normal flow of
execution and are typically used to handle unusual conditions such as hardware malfunctions, illegal
instructions, or other types of errors.
EXCEPTION HANDLING :

Exception handling in ARM processors is a fundamental part of how ARM architectures deal with unexpected
or exceptional conditions during execution.

ARM EXCEPTION TYPES:

 Reset: Occurs when the processor is reset.

 Undefined Instruction: Occurs when the processor encounters an instruction that is not defined.
 Software Interrupt (SWI): Triggered by the SWI instruction for system calls.
 Prefetch Abort: Occurs when an instruction fetch fails.
 Data Abort: Occurs when a data access fails.
 IRQ (Interrupt Request): Triggered by external devices.
 FIQ (Fast Interrupt Request): Higher priority and faster response than IRQ.
Exception Handling Steps
1.Exception Occurrence: An exception occurs (e.g., an undefined instruction is executed).

2.Switch the Mode: The processor switches to a specific mode corresponding to the exception (e.g., Undefined Instruction
mode).

3.Vector Table Lookup: Processor uses the exception type to look up the appropriate handler address in the vector table.

4.State Save: The current program counter (PC) and processor status are saved.

5.Handler Execution: The processor jumps to the exception handler.

6.Exception Handling: The handler processes the exception (e.g., logging, correcting the error).

7.Return to Normal Execution: The processor restores the saved state and resumes normal execution.
Interrupts: Signals emitted by hardware or software indicating an event that needs immediate attention.
They temporarily halt the CPU's current activities to execute a function called an interrupt handler or
interrupt service routine (ISR).

Interrupt Latency: amount of time between the generation of an interrupt and its handling

Types of Interrupt: Software interrupts or Hardware interrupts

INTERRUPT HANDLING

Interrupt handling in ARM processors involves managing signals from hardware devices that require immediate
attention.
This allows peripheral devices like timers, keyboards, and network cards to signal the processor when they need
to be serviced
Steps in Handling an Interrupt
1.Interrupt Occurrence: Hardware device triggers an interrupt.
2.Mode Switch: Processor switches to IRQ or FIQ mode.
3.Vector Table Lookup: Processor fetches the address of the interrupt handler from the vector table.
4.State Save: Current state (registers) is saved to allow the interrupted task to resume correctly later.
5.Handler Execution: Interrupt handler is executed to service the interrupt.
6.State Restore: Saved state is restored.
7.Return to Normal Execution: Processor resumes execution of the interrupted task.
ARM Cortex-M4 processor offers flexible exception and interrupt management,
providing efficient and versatile control over how the system responds to both
synchronous (exceptions) and asynchronous (interrupts) events.

EXCEPTIONS AND INTERRUPTS

NVIC (Nested Vectored Interrupt Controller)

NVIC is an integral part of the ARM Cortex-M4 processor, which handles exceptions and
interrupts
EXCEPTIONS AND INTERRUPTS NVIC : Handles exceptions and interrupts
 key points about the NVIC in the Cortex-M4:

 Interrupt Priority Levels: NVIC supports up to 256 priority levels,

 Nested Interrupts: Higher priority interrupts can preempt lower priority ones, which is crucial for responsive and
real-time applications.
 Interrupt Vector Table: The NVIC uses an interrupt vector table to manage the addresses of the interrupt service
routines (ISRs). This table is typically located at the beginning of the memory space.
 Peripheral Interrupts: The NVIC can manage interrupts from various peripherals connected to the Cortex-M4, such
as timers, serial communication interfaces, and GPIOs.
 Low-Latency Interrupts: The NVIC is designed for low-latency interrupt processing, making it suitable for real-time
and embedded applications.
 System Control Block (SCB): The SCB is part of the NVIC and provides system control and configuration, including
the configuration of the priority of system exceptions.
 Interrupt Enable and Disable: The NVIC allows for enabling and disabling interrupts selectively, providing control
over which interrupts can occur at any given time.
 Low power characteristics - Cortex-M4
Cortex-M4 processor is known for its efficient power management, making it suitable for various low-power
applications.

Here are the primary low power characteristics of the Cortex-M4:

1. Sleep Modes

 Sleep Mode: The CPU clock is stopped while peripheral clocks continue to run. This mode allows the processor
to wake up quickly when needed.
 Deep Sleep Mode: Both the CPU and peripheral clocks are stopped, significantly reducing power consumption.
The wake-up time is longer than in Sleep Mode but still relatively fast.
 Stop Mode: Most of the system clocks are stopped, reducing power consumption further. The system requires a
longer time to wake up compared to Sleep and Deep Sleep modes.
 Standby Mode: The highest power-saving mode, where most of the system is powered down, retaining only
essential information in SRAM. This mode has the longest wake-up time.
2. Dynamic Voltage and Frequency Scaling (DVFS)
 Cortex-M4 can adjust its operating voltage and frequency according to the required performance, allowing
the system to reduce power consumption when full performance is not necessary.

3. Low Power Peripheral Interfaces

 Power-Optimized Peripheral Interfaces: Interfaces such as UART, SPI, and I2C are designed to operate
efficiently, reducing power consumption when communicating with peripherals.

4. Wake-Up Interrupt Controller (WIC)

 WIC enables the Cortex-M4 to remain in Deep Sleep mode until an interrupt occurs, allowing the processor
to stay in low power states for longer periods and wake up only when necessary.

5. Clock Gating
 Cortex-M4 can gate clocks to unused peripherals, stopping the clock supply to these peripherals and thus
reducing dynamic power consumption
6. Low-Power Run and Low-Power Sleep Modes
 These modes allow the system to operate at reduced clock frequencies and voltages while maintaining
functionality, balancing performance and power consumption.

7. Efficient Processing Capabilities

 Thumb-2 Instruction Set: The Cortex-M4 uses the Thumb-2 instruction set, providing a balance between
code density and performance, contributing to power efficiency.
 Digital Signal Processing (DSP) Instructions: The integrated DSP instructions and single-cycle multiply-
accumulate (MAC) operations allow efficient execution of complex algorithms, reducing the need for higher
frequency operation.

8. Energy Management Features

 Flexible Power Management: The Cortex-M4 can be integrated with various power management strategies,
including software-controlled power modes and hardware features that monitor and adjust power consumption
dynamically.