Digital Calculator

BY
Sagar Tripathi (Enrolment No. 20/11/EE/023)
Sheersho Banerjee (Enrolment No. 20/11/EE/026)
Estari Saikiran (Enrolment No. 20/11/EE/016)
Raj Sonkar (Enrolment No. 20/11/EE/048)

under the guidance of

Prof. Varun Saxena, School of Engineering JNU, Delhi

in the partial fulfillment of the requirements

for the award of the degree of

Bachelor of Technology
(a part of Five-Year Dual Degree Course)

School of Engineering

Jawaharlal Nehru University, Delhi

December, 2023
 JAWAHARLAL NEHRU UNIVERSITY
SCHOOL OF ENGINEERING

DECLARATION

We declare that the project work entitled “Digital Calculator” which is submitted by us in partial
fulfillment of the requirement for the award of degree B.Tech. (a part of Dual-Degree Programme)
to School of Engineering, Jawaharlal Nehru University, Delhi comprises only our original work and
due acknowledgement has been made in the text to all other material used.

Sheersho Banerjee Estari Saikiran

7838972785 9515571954

Sagar Tripathi Raj Sonkar

8094753613 93057 58414

Dr. Varun Saxena

(Supervisor)
 JAWAHARLAL NEHRU UNIVERSITY
SCHOOL OF ENGINEERING

CERTIFICATE

This is to certify that the synopsis entitled “Digital Calculator” being submitted by Mr. Sheersho
Banerjee (Enrolment No.- 20/11/EE/026), Mr. Sagar Tripathi (Enrolment No. 20/11/EE/023),
Mr. Estari Saikiran (Enrolment No. 20/11/EE/016), and Mr. Raj Sonkar (Enrolment No.
20/11/EE/048) in fulfillment of the requirements for the award of the Bachelor of Technology (part
of Five-Year Dual Degree Course) in Electronics & Communication Engineering, will be carried
out by him under my supervision.

In my opinion, this work fulfills all the requirements of an Engineering Degree in the respective
stream as per the regulations of the School of Engineering, Jawaharlal Nehru University, Delhi.
This thesis does not contain any work, which has been previously submitted for the award of any
other degree.

Dr. Varun Saxena

(Supervisor)
Assistant Professor
School of Engineering
Jawaharlal Nehru University, Delhi
 JAWAHARLAL NEHRU UNIVERSITY
SCHOOL OF ENGINEERING

ACKNOWLEDGMENT

We are very thankful to our mentor Dr. Varun Saxena for his invaluable support, patience, time and
guidance in seeing us in the completion of this project.

Sheersho Banerjee Estari Saikiran

7838972785 9515571954

Sagar Tripathi Raj Sonkar

8094753613 93057 58414

Dr. Varun Saxena

(Supervisor)
 ABSTRACT

This project aims to design and implement a 4-bit adder, subtractor, and multiplier
using logic gates and integrated circuits (ICs) on a breadboard. These fundamental
arithmetic operations are essential components of digital systems and play a crucial
role in various applications, including computing, and communication. The
fundamental concepts of adders, subtractors, and multipliers are used in the
arithmetic logic unit (ALU) of a computer. The ALU is a digital circuit that performs
arithmetic and logic operations on binary data. It is a crucial component of the central
processing unit (CPU). By constructing these circuits using logic gates, we can gain a
deeper understanding of their underlying principles and the practical aspects of digital
electronics circuit design.
LIST OF CONTENTS
Content Page No.
Declaration………………………………………………...………….....................................i
Certificate…………………………………………...……………..............................................ii
Acknowledgement …………………………………………..........................………iii
Table of Contents…………………………...……………………………….....................................iv
List of Figures…………..…………………………………………..……………………….........v-vii
Abstract……………………………………………………………………......………………..….viii
Chapter 1: INTRODUCTION and THESIS OVERVIEW
1.1 Introduction………………………………………………………………..…………………...1-3
1.2 Thesis Objective …………………………………………………………...….............................3
1.3 Organizations of Chapters…………………………………….…………..………………...….4-5
Chapter 2: LITERATURE SURVEY
2.1 Introduction.....................................................................................................................6
2.2 IC 7408 ……………………………………….......................……..6-13
2.2.1. S-Band……………………………………………………………............................…6
2.2.2. C-Band………………………………….………………………………………......7-
10
2.2.3. X-Band………………………………….……………………………….……………
11
2.2.4. Ku-Band………………………………………………...………………………….…
12
2.3 A…………………………………………………………………...……………………………13
Chapter 3: PROPOSED WORK AND METHODOLOGY
3.1 Adder................................................………………………………………………….... 14
3.2 Subtractor …………………………………………………….………………………...14
3.3 Multiplier …………………………………………………….………………………...15
Chapter 4: RESULT DISCUSSION
Introduction….……………………………………………..………………………………...… 16
4.2 Ajjjjjkkj………………………………………………………………………………...…… 17-
23
4.2.1 Askk…………………………………...………………................................................18
4.2.2 Llfkkfkf ……………………………………………. ………………………………...21
4.2.3 Log-Periodic Toothed Trapezoidal Antenna..................................................................22
4.2.4 Dipole Array..................................................................................................................23
Chapter 5: CONCLUSION AND FUTURE SCOPE
5.1 Conclusion……………….…………………………………………………………………...…24
5.2 Future Scope………………………………………………………….....................................…26
REFERENCES ...........................................................................................................................27-30

LIST OF FIGURES

Details of Figure Page No.

1.1 Ultrawide band, wide band, and narrow band structure…………….……………….…5
1.2 Frequency bands…………………………………………………………………….….5
3.1 Structure of a Microstrip Patch Antenna…………………………………………….…9
3.2 Basic principle of patch antenna………………………………………………………10
3.3 Microstrip Patch Antenna…………………………………………………………..…11
3.4 (a)Top View of Antenna Figure…………………………………...………………….12
CHAPTER-1
INTRODUCTION and THESIS OVERVIEW

1.1. INTRODUCTION

In the realm of digital electronics, arithmetic operations form the foundation for performing
complex computations. Among these operations, adders, subtractors, and multipliers are particularly
fundamental. These circuits enable us to manipulate and process binary data, which is the
cornerstone of modern digital systems.

The 4-bit adder, subtractor, and multiplier circuits to be designed in this project will employ logic
gates as the basic building blocks. Logic gates are electronic circuits that perform specific logical
operations, such as AND, OR, NOT, and XOR. By combining these logic gates in a structured
manner, we can construct more complex circuits that execute the desired arithmetic operations.

The implementation of these circuits will utilize integrated circuits (ICs), which are small electronic
devices that encapsulate numerous transistors and other components. ICs offer several advantages,
including compactness, reliability, and ease of use. They provide a convenient and practical means
of constructing complex electronic circuits.

A 2-bit adder can be implemented as an FSM. The inputs are the two bits to be added, and the
output is the sum of the two bits. The states of the FSM represent the carry bit and the sum of the
two bits.

1.2. THESIS OBJECTIVE

The primary objective of this thesis is to :

 (i) Perform binary addition of two 4-bit numbers.

(ii) Perform binary subtraction of two 4-bit numbers.

(iii) Perform binary addition of two 2-bit numbers

1.3. ORGANIZATIONS OF CHAPTERS

The thesis consists of five chapters and the overview of all the chapter are as follows:

Chapter 1: This chapter provides a brief introduction on the background, the objectives of the
thesis involved in accomplishing the thesis.
Chapter 2: This chapter gives an overview of available literature on the various IC’s.
Chapter 3: describes the details of proposed work and methodology used in this project
implementation.
Chapter 4: This chapter gives the discussion about the simulated and measured results.
Chapter 5: presents the conclusion of this research work and future scope of the work.
References: In the last section of this thesis, used references are given.

CHAPTER-2
LITERATURE SURVEY

2.1. INTRODUCTION

2.2 ABCDEFG HIGJLM NOP (Sub-headings)

CHAPTER-3

PROPOSED WORK AND METHODOLOGY

This chapter includes the working of the Adder, Subtractor, and Multiplier

Adder :-

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A
and B and the third input is an input carry as C-in. The output carry is designated as C-out and the
normal output is designated as S which is sum.

One full adder can help us in adding two numbers each of one bit only, so we will use N-full adders
for adding two numbers each of N-bits.

We have implemented a 4-Bit Adder. In this we have connected a series of four full adders. The
first full adder will add the Least Significant Bits (LSB) of the two numbers A and B with zero
carry input (Cin). The carry output (Cout) from the first full adder will be taken as the carry input
(Cin) of the second full adder and so on till the Most Significant Bit (MSB). The carry output
(Cout) from the last full adder will be the carry of the entire sum of A and B.
Subtractor :-

For the subtraction of two numbers of A and B, where we will subtract B from A, we will subtract
by taking the 2’s complement and add it to A bit by bit. We will first start by taking the 1’s
complement of B by passing each bit of B with 1 using a control line ‘M’ in the XOR gate.

1’ s Complement

B XOR 1 = B’

To take the 2’s complement from the 1’s complement we will add 1 from the control line ‘M’
which will go into the Cin of the first full adder.

2’ Complement

(B XOR 1) +1 = B’ + 1

Multiplier :-

For multiplying two 2-bit numbers A and B, and the product P, we will use the ‘Shift and Add’
algorithm. In this we will multiply the two binary numbers the same way we multiply two decimal
(base-10) numbers. If we are multiplying two numbers of N-bits each, then the product P will be
stored in a size of 2*N-bits.
A0B0 or A0.B0 is the Bitwise AND of A0 and B0, and this will give us P0. In the second step we
have to add B0A1 and B1A0 which will give P1 as the sum and carry C1 which will get added to
B1A1. Their subsequent sum will be P2 and the carry C2 will be P3.
CHAPTER-4
RESULT DISCUSSION :-
CHAPTER-5
CONCLUSION AND FUTURE SCOPE

5.1. CONCLUSION

5.2. FUTURE SCOPE

REFERENCES
[1] R. Garg, P. Bhartia, I. Bahl, and A. Ittipiboon, “Microstrip Antenna Design HandBook,” Artech
House Inc, 2001.
[2] S. John, “Strong localization of photons in certain disordered dielectric superlattices,” Physical
Review Letters, Vol. 58, No. 23, pp. 2486–2489, 1987.
[3] E. Yablonovitch, “Inhibited spontaneous emission in solid-state physics and electronics,”
Physical Review Letters, Vol. 58, No. 20, pp. 2059–2062, 1987.
[4]