DIGITAL INDUSTRIES SOFTWARE

Packetized scan test

Take a leap forward in DFT for complex SoCs with Tessent Streaming
Scan Network

Executive summary
The Siemens solution for packetized delivery of scan test patterns, Tessent™
Streaming Scan Network (SSN), is a significant advancement in DFT for today’s
complex SoCs.

It enables simultaneous testing of any number of cores with few chip-level pins, plus
reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT
solution without compromises between implementation effort and manufacturing
test cost. This paper describes the basic components of the SSN and presents short
case studies of its use.

Author: Geir Eide

siemens.com/software
White Paper – Packetized scan test

Test challenges

Let’s take a brief look at some of the Since at least one output channel is
challenges facing DFT engineers today. needed per core instance, this can limit
the number of identical cores that can
Planning and layout be tested concurrently.
To test a group of cores concurrently
using a traditional hierarchical pin-mux Also, because the capture clock is
scan test approach, scan channel inputs usually applied simultaneously to all
and outputs are connected directly to a cores, the number of pipeline stages
limited number of chip-level pins must be equal between a scan input pin
through a set of muxes. Which cores can and all the identical core instances it
be tested together has to be determined drives. This can be challenging in the
early in the design flow. In a linear presence of tiling where no routing or
bottom-up flow, where the number of logic may exist outside the cores.
scan channels and compression
configuration per core is fixed, this could Tile-based designs with abutment
result in sub-optimal results and wasted Tile-based layout adds further
test bandwidth. complexity and constraints to DFT
architectures. Cores are designed to
Effective handling of identical cores abut one another such that connections
One way to optimize test pattern flow from one core to the next, virtually
volume for identical core instances is to eliminating top-level routing. Any
broadcast the same pattern to the scan connectivity between cores has to flow
inputs from the same top-level pins. through cores that are between them.
Outputs are often observed Top-level logic has to be pushed into the
independently to guarantee test cores and designed as part of the cores.
coverage and to ensure diagnosability.

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Solution: packetized test delivery

Tessent SSN decouples test delivery and With SSN, the compression and number
core-level DFT requirements so core- of scan channels for a core are
level compression configuration can be determined based on what results in the
defined completely independently of most compact pattern set for that core
chip IO limitations. Grouping cores for by itself.
concurrent testing is selected
programmatically, not hard-wired. This Compression can be configured once
concept dramatically reduces the DFT and for all for cores that are used in
planning and implementation effort. multiple designs. SSN automatically
distributes the available bandwidth
among the active cores based on what’s
required for each core, eliminating
whitespace in the test data (figure 1).

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Figure 1: SSN enables a true bottom-up flow with multiple test cost reduction capabilities.

In addition to the planning, a simple example with a 6-core design

implementation, and test cost benefits, that uses SSN. Each core typically
the SSN architecture eases routing and contains one Streaming Scan Host (SSH)
timing closure, and is fully compatible node (light blue box). The SSH drives
with tile-based design with abutment. local scan resources with data delivered
on the SSN bus. Although just a single
SSN still supports all ATPG pattern types compressor/compactor is shown in
and fault models, is compatible with all figure 2, the SSH node can interface
Tessent DFT methodologies and with one or more Tessent TestKompress
products, and has full support for embedded deterministic test (EDT)
diagnosis and yield analysis. controller(s), uncompressed scan
chains, or a combination of the two.
SSN technology and concepts
SSN is a bus-based scan data
distribution architecture. Figure 2 shows

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Figure 2: SSN used in a 6-core design

Each SSH has two external interfaces: no need to send any opcode or address
An IEEE 1687 IJTAG interface and a information with each packet. Each SSH
parallel SSN data bus. The IJTAG network controls the local scan operations for
is used to configure all nodes in the SSN the core, including transitions between
network prior to the application of scan load/unload and capture stages. All scan
test patterns. Each node is loaded with signals and EDT controls are generated
information related to the protocol such by the SSH local to the core.
as the active bus width, its location in
the series of nodes driven, the number The SSN bus width is selected based on
of shift cycles per scan pattern, chip-level pin availability and is
scan_enable transition timing independent of the number and size of
information, etc. the scanned cores, and the number of
channels needed by the EDT
Following this setup, the entire scan test controller(s) in each core. With the same
pattern set is applied as packetized data parallel bus width, each core has the
that is streamed on the parallel SSN bus. same plug-and-play interface, allowing
The SSHs are programmed just once per SSN to scale efficiently as the design
pattern set and only the scan payload is floorplan, number of cores, or the
streamed following the setup. There is content of the cores change.

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With SSN, the bus width and channel Consider the example shown in figure 3
count of the cores are independent of where two blocks are being tested at the
each other. Scan test data is delivered same time. Block A has five scan
synchronously across the bus in a packet channels and loads/unloads five bits per
format to each core. The number of bits shift cycle. Block B has four channels.
a core can receive per packet is For both blocks to perform one shift
algorithmically determined from the cycle, nine bits have to be delivered. In a
pattern statistics of the cores running conventional pin-mux scan access
concurrently, but cannot be greater than method, this would have required nine
the number of scan (EDT) channels. The chip-level scan input pins and nine scan
data delivered from the tester may be output pins. With SSN, the packet size is
viewed as a continuous stream of set to nine bits independent of the SSN
packets that may wrap around SSN bus bus width, which is eight bits in this
boundaries. example.

Figure 3: Testing two blocks at the same time.

The ability to route the bus carrying the flexibility in accessing any combination
data from one core to the next while of cores without changing the
dynamically controlling which cores are hardware. Unlike pin-mux architectures,
active/inactive/bypassed means one has this flexibility does not come at the

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expense of routing congestion. There is buses. On the output side, a bus

no need to try and predict at design frequency divider (BFD) node is added
time how to group cores that are to be to convert the SSN output bus back to a
tested concurrently. Whether 200 MHz 64-bit bus driving the output
performing ATPG on groups of cores or pins.
retargeting patterns from different
cores, the same SSN network can Optimizing test time and data
provide access to one core at a time, all volume
cores simultaneously, or anything in- When ATPG is run with multiple
between. interacting cores in external test mode,
it is necessary to align capture cycles of
Time multiplexing all the affected cores. With SSN, the
When driving multiple cores SSHs are programmed such that each
concurrently, the packet typically spans core can shift independently, but
multiple bus widths, resulting in an capture occurs concurrently once all
internal shift frequency slower than the cores have completed scan load/unload.
SSN bus frequency. In many cases, it is
possible to implement a 400MHz SSN In other situations, such as when ATPG
bus, but not possible to shift data for wrapped cores with OCCs run in
through the chip-level pins at more than isolation, it is more effective if each core
200 MHz. Assume that the SoC has can independently transition between
enough pins to implement 64 scan shift and capture. A core with short scan
inputs and 64 scan outputs. chains should not need to wait for other
cores to complete shifting before they
One option would be to implement a can capture. Often there are significant
64-bit bus throughout the chip and imbalances in the pattern counts of
operate it at 200 MHz. Alternatively, as different cores.
shown in figure 4, the data can be
scanned into the chip through 64 pins at Traditional retargeting methods add
200 MHz and a bus frequency multiplier padding for the cores with fewer
(BFM) added between the scan inputs patterns resulting in wasted data, cycles,
and the first SSH to convert this input and test time. If a core requires many
stream to a 32-bit, 400 MHz bus. This fewer overall shift cycles across a
32-bit bus is then used across the chip, pattern set than other cores, it can be
connecting all SSH nodes with 32- bit sent fewer bits per packet.

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For example, a core with 4 channels instead of every packet. The result is
does not need to be allocated 4 bits per that the total number of packets
packet. It can be throttled down and remains the same, but the size of the
sent only 1 bit per packet such that it packets is reduced, speeding up the
shifts internally every four packets overall test time.

Figure 4: Time multiplexing.

Effective testing of identical cores

Many SoCs achieve high throughput by parallel processing cores that are replicated
multiple times. In pin-mux scan architectures, the scan inputs may be broadcast to
identical core instances, but the scan outputs are usually observed independently to
ensure lossless mapping and observability for diagnosis. SSN provides a scalable
method for testing any number of identical core instances in near-constant test time,
independent of the number of available chip-level pins. Input data, expected
responses, and compare/nocompare mask data are scanned in within each packet, as
illustrated in figure 5.

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Figure 5: Testing any number of identical core instances.

The same packet data is used by each outputs of one core connect to the
identical core instance, as it inputs of the next adjacent core. A chip
synchronously moves through the with SSN usually has a single SSN
network. Each core performs its own on- datapath (parallel bus) that goes
chip comparison. A pass/fail “sticky” bit through all cores. Depending on the
is observed on TDO. The optional floorplan and pad locations, it may be
accumulated per-shift status can be preferable for physical design to
added to the packet and observed on implement multiple, physically
the SSN outputs. independent datapaths. Each datapath
is also configurable and can include
Tile-based designs muxes that can be programmed to
SSN is designed to support the include or exclude segments of the
abutment of cores in tile-based designs network similar to the Segment
with no routing outside the cores. The Insertion Bit (SIB) in IJTAG networks.

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Implementing SSN

Table 1 summarizes the requirements What is not needed is any up from

and recommendations for implementing planning of which regions run in parallel
SSN in a design. For instance, as IJTAG is or relative order.
used to program the SSN circuitry, IJTAG
infrastructure is required. To enable The SSN implementation flow is
independent shift and capture, standard described in detail in the “Tessent SSN
(Tessent or 3rd party) OCC is required. Workflows” section of the Tessent Shell
User’s Manual. A testcase
Two considerations to weight during the demonstrating this flow is included in
design planning phase are, first, to the Tessent Shell release tree. The flow
optimize compression at the core level is fully integrated with all other Tessent
to whatever provides you the best DFT such as memory BIST.
results (most compact pattern set) for
that core in isolation. There is no need A comprehensive set of SSN verification
to take chip-level resources or even the capabilities, including DRCs, dedicated
planned SSN bus width into testbenches, and network integrity
consideration. patterns, are available throughout the
flow to ensure that any potential
Second, at the chip level, the SSN bus problems or mistakes are captured early.
should be planned out based on the After SSN insertion is complete, before
number of pins available, and the block synthesis. Later in the flow, loopback
diagram of the design. The SSN patterns help validate the SSN network
datapath should be planned through down to the individual cores, without
physical regions of the design. In having to perform a complete
addition to the actual connectivity, in simulation of the scan patterns.
this planning, you will also plan for
muxes as needed for debug return The failure diagnosis flow is virtually
paths, and pipelines needed for timing. identical to that of a hierarchical DFT
flow. Failures captured on the tester are
reverse mapped to core-level failures.

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After the reverse mapping, layout-aware

diagnosis is performed with no
limitations.

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Industry results

Adopters of Siemens’ packetized test— Tessent Streaming Scan Network have now
completed SoC designs and are sharing their stories. Their experiences reveal that
SSN offers good automation, compatibility with existing DFT and design flows, a
common architecture for all design types, and solid field support. Specific benefits of
SSN include cutting DFT development time in half, easing routing and timing closure,
and reducing test time and test data by up to 4X.

Broadcom case study

Broadcom Central Engineering designs CPUs; some are targeted to very low-power
applications, others to high-performance applications. They typically have multiple
voltage domains, 1-3 GHz frequencies, many instantiated cores. Challenges include
low-power test, high-speed designs, and managing test cost. They were asked to
implement a scalable test solution for homogenous multi-core high-speed CPU
blocks.

Broadcom implemented SSN on a design with 12 identical CPUs, running at over

2.5GHz. They found that testing the identical cores with SSN reduced overall test time
by 15%. There was also a significant power benefit; their Shmoo plot showed a 30mV
difference between SSN vs. EDT when testing 12 cores in parallel. This is possible with
SSN because shift and capture is done independently across the cores that are tested
simultaneously, as shown in figure 6.

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Figure 6. Independent capture reduces test time and allows for a larger number of cores to be tested
in parallel without exceeding the power budget.

Intel case studies time and allows for a larger number of

At the 2020 ITC, Intel compared the SSN cores to be tested in parallel without
method to their traditional pin-mux exceeding the power budget.
approach and found a 43% reduction in
test data volume and a 43% reduction of According to their presentation, the
test cycles. Implementation and test implementation was straightforward,
retargeting tasks were between 10x-20x requiring no more effort than their
faster. custom fabrics. Setting up the IJTAG
requirements took a little more time
At ITC 2021, Intel’s Devices because it was new to them, but they
Development Group described their SSN found the ICL (Instrument Connectivity
implementation on a multi-die design, Language) extract to be a very efficient
in which different die using different test form of validation. They saw over 2X
fabrics share the same IO. Two of the die efficiency gains with pattern retargeting
used SSN and the other two used a and testing multiple cores in parallel.
custom test fabric. This approach allows SSN can automatically tune the
them to phase in SSN over time. Figure bandwidth, as shown in figure 7.
6. Independent capture reduces test

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Each bar represents cores tested directs more test resources to the cores
simultaneously. The total test time that need more data, resulting in a
depends on the core with the highest scenario shown on the right side.
number of cycles. SSN automatically

Figure 7. Bandwidth tuning for more efficient use of compute resources.

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Summary

The SSN technology described in this fast streaming of data to/ from and
paper solves many of the scan throughout the chip. It simplifies design
distribution challenges in complex SoCs. planning and implementation and is
By decoupling chip and core level DFT, it especially well suited for tile-based
enables concurrent testing of any designs.
number of cores with few chip- level
pins, and it has multiple features to The SSN implementation flow is based
reduce test time and test data volume. on Tessent Shell flow for hierarchical
designs. SSN is fully supported by
It can test any number of identical core Tessent TestKompress™ and Tessent
instances in near-constant time, Diagnosis, and can co-exist with all
minimizes padding in the presence of other Tessent DFT technologies such as
cores with mismatched pattern counts Tessent MemoryBIST and Tessent
and/or scan chain lengths, and enables LogicBIST.

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