Apple Laptop A1466 Boot Sequence Repair Process
Apple Laptop A1466 Boot Sequence Repair Process
Detailed explanation of the Apple laptop A1466 boot sequence repair process
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for 820-3437 and 820-00165 , which means that it can be used on Apple notebook Air machines from 2013 to 2017 .
Let's first look at their voltage generation order
1. PP3V42_G3H=3.42V
2. PPBUS_G3H=8.6V
3. PP3V3_S5_REG_R=3.3V
4. PP5V_S4RS3=5V
There are also memory voltage and CPU voltage in the future. I will update this later. If you can fix the above four voltages, you can fix 80%
Air machine is 14.5V , which goes through a power supply board to the power interface J7000 of the motherboard . Although the power su
functions, it doesn’t cost much to buy one. I will not go into details again. I will only analyze the power-on timing of the motherboard.
Protective isolation
PPDCIN_G3H=14.5V , PPDCIN_G3H is turned on through Q7010 , generating PPDCIN_G3H_ISOL=14.5V , PPDCIN_G3H_ISOL is sent to the V
R7005/D7005 for power supply (or in battery mode, PPBUS_G3H is used to power the Vin pin of U7090 through R7006/D7005 ), and at the
R7080/R7081 to the SHDN pin as the chip start signal. After U7090 receives power supply and start signal, it generates PP3V42_G3H=3.42V
comes out first and is a very important voltage. After getting the machine, the first thing you need to check is this voltage. This voltage will
and EC . In the actual maintenance process, this voltage often has problems.
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PPDCIN_G3H_ISOL=14.5V is converted into CHGR_DCIN through D7105/R7105 to supply power to the second foot DCIN of U7100 . PPDCIN
isolation tube Q7180 and the current sensing resistor R7120 , and the voltage PPBUS_G3H=8.6V is generated by the PWM control Q7130 o
PPDCIN_G3H_ISOL=14.5V is divided by two resistors R7110/R7111 in series to generate CHGR_ACIN signal and send it to the third pin ACIN
insertion detection signal. The voltage obtained by the resistor division of this pin is 3.8V
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The second pin of U7100 is DCIN, the 19th pin VDD outputs 5V PP5V1_CHGR_VDDP , and then supplies power to the 20th pin after passing
mainly powers the internal chip module.
The 13th pin of U7100, SMB_RST_N , is the reset signal and must be pulled high to 3.42V
Pin 6 of U7100 is the voltage setting pin CHGR_CELL for setting the common point .
The power supply voltage of CELL is 12.6V, the ground voltage of CELL is 8.6V , and the floating voltage of CELL is 4.2V . This can explain wh
the 15- inch Apple notebook is 12.6V . If you are interested, you can check how the CELL pins of the 15- inch notebook are connected to th
ACIN conditions are met, the chip will send a signal SMC_BC_ACOK , which goes directly to EC and is pulled up to 3.42V .
EC standby
PP3V42_G3H = 3.42V power supply to VBAT , VDDA , VDD pins to provide voltage
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2.
Get the PP3V3_S5_AVREF_SMC power supply VREFA+ and SMC_REST_L reset signal of U5110 4. Get the SMC_BC_ACOK adapter detection v
Then the EC internal program starts to work and configures the GPIO pins
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Below are the 11 major standby conditions of Air that I personally compiled , specifically for the 11 major standby conditions of the 4th and
Apple notebooks
1.VCCRTC
32.768 pins
5.DSWVRMEN
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6.VCCDSW3_3 7.DPWROK
8. SLP_SUS
9. VCCSUS3_3
10. RSMRST
11. SUSCLK
12.PWRBTN PCH 1
1After the standby condition is met, press the switch, and the switch signal is sent to EC . EC detects that the LID sleep lid switch is at a high
high power-on signal to the bridge PWBRTN* with a delay . PWRBTN* is the standard power-on pin inside the CPU . After PWRBTN* reache
SLP_S5*/ SLP_S4*/ SLP_S3*/ SLP_S0* to EC , and then delays the issuance of SM_PG_CNTL1. Apple's laptops do not have a CMOS battery, a
VCCRTC comes from PPVRTC_G3H
The standby clock of the bridge module does not have a 32.768 crystal oscillator, the secondary clock comes from U1900, PCH_CLK32K_RTC
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S5_PWRGD of U7501 is pulled up by PP3V42_G3H and sent to EC to get PW_DSW_PWRGD to DPWORK of PCH
trigger
The power button generates SMC_ONOFF_L to EC , EC generates PM_PWRBTN_L to the bridge, and after the standby conditions of the brid
PWRBTN is received , PM_SLP_S5_L/PM_SLP_S4_L/PM_SLP_S3_L/PM_SLP_S0_L is generated
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PM_SLP_S5_L/PM_SLP_S4_L/PM_SLP_S3_L/PM_SLP_S0_L is sent from the bridge module and reaches the EC. The next signal that needs att
P5VS4RS3_PGOOD
PP1V8S3_PGOOD
DDRREG_PGOOD
P1V05S0_PGOOD
Finally, ALL_SYS_PWRGD is sent to the second pin of U1930 and combined with the first pin to get CPU_VCCST_PWRGD
After CPU_VCCST_PWRGD reaches the CPU , the CPU sends CPU_VR_EN , which reaches the VR_ON pin of U7200 to turn on the CPU power
CPU_VR_READY to the internal pin of the CPU.
PM_PCH_PWROK , PM_PCH_SYS_PWROK signals are sent to CPU pins SYS_PWROK , PCH_PWROK , APWROK . After all signals are normal, 2
oscillating normally, BIOS is read through SPI bus.
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Finally, the CPU sends a platform reset of 3.3V after a delay of PLTRST to reset each device on the motherboard. The CPU completes its inte
an SVID signal after receiving PROCPWRGD . The CPU sends an SVID waveform to the CPU power chip to adjust the CPU core voltage to th
CPU conditions are met, the motherboard starts to read the BIOS self-test . When the self-test is completed, the machine turns on.
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