Scribd
Upload
84 views2 pages

Digital Electronics Dec 2022

De

Uploaded by

ravi190917
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
84 views2 pages

Digital Electronics Dec 2022

De

Uploaded by

ravi190917
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Code No: R2022022 R20 SET - 1

II B. Tech II Semester Supplementary Examinations, December - 2022


DIGITAL ELECTRONICS
(Electrical and Electronics Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions, each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~
UNIT-I
1 a) State and Explain the DeMorgan’s Theorem and Consensus Theorem [7M]
b) Realize 2 input X-OR and X-NOR gates using only NOR gates and only NAND [7M]
gates
Or
2 a) Convert the following numbers [8M]
i) (615)10 = ( )16
ii) (214)16 = ( )8
iii) (0.8125)10=( )2
iv) (658.825)10=( )4
b) Express the Boolean function F(p, q, r, s)=s(p’+q)+q’s in a sum of minterms and a [6M]
product of maxterms.
UNIT-II
3 a) Perform BCD addition and Excess-3 addition for the following numbers [6M]
0001 0011 and 0010 0110.
b) With a neat diagram, explain in detail about the working of a 4 bit look ahead adder. [8M]
Also mention its advantages over conventional adder.
Or
4 a) Simplify the Boolean function [7M]
F(A,B,C,D)=Σm(0,2,3,7,11,12,14,15) using tabulation method.
b) Explain full- Adder. Implement a full- Adder using half Adders. [7M]
UNIT-III
5 a) Obtain an 8×1 multiplexer with a dual 4-line to 1-line multiplexers having separate [7M]
enable inputs but common selection lines. Use block diagram construction.
b) Design a 4-bit magnitude comparator with three outputs : A>B, A=B, A<B [7M]
Or
6 a) Design BCD to grey code converter and draw the logic diagram. [7M]
b) Use PLA with 3 inputs, 4 AND terms and two outputs to implement the following [7M]
Boolean functions F1(A,B,C)= ∑m(3,5,6,7) and F2(A,B,C)= ∑m(1,2,3,4)

1 of 2

|'''|'|'|''|''||'|||
Code No: R2022022 R20 SET - 1

UNIT-IV
7 a) Realize JK Flip flop using SR Flip flop and derive their characteristic equations. [7M]
b) Design 4-bit Asynchronous counter using JK flip flop with its timing diagram. [7M]
Or
8 a) Write difference between Combinational & Sequential circuits. [7M]
b) Build a 4bit universal shift register using D flipflops and multiplexers. [7M]
UNIT-V
9 a) Design 4-stage twisted ring counter with circuit diagram, state transition diagram [7M]
and state table.
b) A clocked sequential circuit with single input x and single output z produces output [7M]
z=1, whenever the input x completes the sequence 1011 and overlapping is allowed:
i) Obtain the state diagram ii) Obtain its minimum state table and design circuit with
D flip flop.
Or
10 a) Explain capabilities and limitations of finite state machine. [7M]
b) Draw state diagram in Mealy model for the following state table. [7M]

2 of 2

|'''|'|'|''|''||'|||

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy