1

INSTITUTE OF AERONAUTICAL ENGINEERING

(AUTONOMOUS )
Dundigal, Hyderabad - 500 043

L ECTURE N OTES :

VLSI DESIGN(AECB27)

D RAFTED BY :
K.S.I NDRANI ( IARE 10663)
Assistant Professor

D EPARTMENT O F E LECTRONICS AND C OMMUNICATION E NGINEERING

 2

I NSTITUTE OF A ERONAUTICAL E NGINEERING

September 30, 2021
Contents

Contents 1

List of Figures 4

Abbreviations 8

Symbols 9

1 MOSFETS 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 IC Invention: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Moore’s Law: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 IC Invention: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Moore’s Law: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 IC Technology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Scale of Integration: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 MOS TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5.1 MOS Transistor Symbol: . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5.2 ENHANCEMENT AND DEPLETION MODE MOS TRANSISTORS . 7
1.5.3 Working of Enhancement Mode Transistor . . . . . . . . . . . . . . . . 9
1.5.4 Case 1: Vgs = 0V and Vgs < Vt . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.5 Case 2:Vgs > Vt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.6 NMOS FABRICATION . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 CMOS FABRICATION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6.1 N-Well Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.7 Basic Electrical Properties of MOS and Bi CMOS circuits . . . . . . . . . . . . 17
1.7.1 ID −VDS Characteristics of MOS Transistor : . . . . . . . . . . . . . . . 17
1.7.2 Drain-to-Source Current IDS Versus Voltage VDS Relationships: . . . . . 18
1.7.3 Non-saturated Region : . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7.4 (i).Load resistance RL : . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.7.5 nMOS depletion mode transistor pull-up : . . . . . . . . . . . . . . . . 31
1.8 BiCMOS INVERTER: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.8.1 Comparison of BiCMOS and C-MOS technologies . . . . . . . . . . . . 35

2 VLSI DESIGN STYLES 37

1
Contents 2

2.1 VLSI DESIGN FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.1.1 Front-end design (Logical design): . . . . . . . . . . . . . . . . . . . . . 38
2.1.2 Back-end design (Physical design): . . . . . . . . . . . . . . . . . . . . 39
2.2 MOS LAYERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3 STICK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4 NMOS and CMOS Design Style : . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5 Stick Diagrams – Some Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6 Design Rules and Layout : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.7 Why we use design rules?: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.8 Types of Design Rules: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.9 Scalable Design Rules :e.g. SCMOS, λ -based design rules . . . . . . . . . . . . 48
2.10 Absolute Design Rules:e.g. µ -based design rules . . . . . . . . . . . . . . . . . 48
2.11 LAMBDA BASED DESIGN RULES . . . . . . . . . . . . . . . . . . . . . . . 49
2.12 CONTACT CUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.13 Other design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.14 CMOS λ x-based Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.15 µm CMOS Design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.16 2µm CMOS Design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.17 Scaling of MOS circuits: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3 BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 64

3.1 BASIC CIRCUIT CONCEPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1.1 Sheet Resistance RS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2 Sheet resistance concept applied to MOS Transistors and Inverterts: . . . . . . . 65
3.3 Sheet resistance for Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4 Area capacitance of layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.5 Standard unit of capacitance □cg . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.6 Calculation for capacitance value . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7 INVERTER DELAYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.8 CMOS inverter pair delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.9 Formal estimation of CMOS inverter delay . . . . . . . . . . . . . . . . . . . . . 70
3.10 Fall time estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.11 Cascaded Inverters as drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.12 Super buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.13 BiCMOS drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.14 Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.15 Design of long polysilicon wires . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.16 Wiring capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.16.1 (i) Fringing fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.16.2 (ii) Interlayer capacitances . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.16.3 (iii)peripheral capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.17 Fan – in and Fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.18 Choice of layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.19 Complex gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.19.1 CMOS Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Contents 3

3.19.2 Complex Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.19.3 Pass Transistors and Transmission Gates . . . . . . . . . . . . . . . . . 86
3.19.4 Dynamic CMOS design . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4 Data Path Subsystems 96

4.1 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.1 Single-Bit Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.2 n-Bit Parallel Adder or Ripple Carry Adder . . . . . . . . . . . . . . . . 99
4.2.3 Carry lookahead adder (CLA) . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.4 Manchester carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4 Parity generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.5 Zero-One detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.6 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.7 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.7.1 Asynchronous(Ripple counters) . . . . . . . . . . . . . . . . . . . . . . 109
4.7.2 Synchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.7.3 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.8 MEMORY ELEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.8.1 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5 LOGIC DESIGN AND TESTING STRATEGIES 114

5.1 Programmable logic devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1.1 PLA s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1.2 Programming Array Logic . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.3 Field Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . 117
5.1.4 Gate Array Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.1.5 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.1.6 NEED FOR TESTING MOTIVATION . . . . . . . . . . . . . . . . . . 120
5.1.7 Challenges in VLSI Testing . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1.8 TEST PRINCIPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.9 Exhaustive Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.10 Stuck at Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.11 CONTROLLABILITY AND OBSERVABILITY . . . . . . . . . . . . . 125
5.1.12 DESIGN FOR TESTABILITY . . . . . . . . . . . . . . . . . . . . . . 125
5.1.13 Built in Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Bibliography 134
List of Figures

1.1 IC shrinkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 MOS TRANSISTOR SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 (c) Enhancement P-type MOSFET (d) Depletion P-type MOSFET . . . . . . . . 8
1.4 Cut-off Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 formation of a channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 (c) Linear Region. (d) Saturation Region . . . . . . . . . . . . . . . . . . . . . . 10
1.7 MOS V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 Fabrication Process of NMOS Device . . . . . . . . . . . . . . . . . . . . . . . 12
1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.14 Depletion mode device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.15 Enhancement device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.16 nMos structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4
List of Figures 5

1.37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.1 VLSI DESIGN FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2 nMOS ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3 nMOS depletion mode inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.4 NMOS DEPLETION NAND NOR . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5 NMOS DEPLETION example for function F . . . . . . . . . . . . . . . . . . . 43
2.6 CMOS INVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7 CMOS NAND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.8 Rule 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.9 Rule 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.10 Rule 4 Demarcation line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.11 CMOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.12 CMOS stick layout design style . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.13 semiconductor manufacturing technology . . . . . . . . . . . . . . . . . . . . . 47
2.14 LAMBDA BASED DESIGN RULES . . . . . . . . . . . . . . . . . . . . . . . 50
2.15 Layout1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.16 Layout 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.17 MOS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.18 Layout 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.19 Layout 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.20 nMOS CMOS Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.21 contact to polysilicon diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.22 pwell rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.23 fig1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.24 2µm design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.25 scaling of MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.26 scaling of MOS electrical parameters1 . . . . . . . . . . . . . . . . . . . . . . . 61
2.27 scaling of MOS electrical parameters2 . . . . . . . . . . . . . . . . . . . . . . . 62
List of Figures 6

2.28 scaling of MOS electrical parameters . . . . . . . . . . . . . . . . . . . . . . . 63

3.1 conducting material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.2 General logic gate using pull-up and pull-down networks . . . . . . . . . . . . . 82
3.3 2-input NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.4 input NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5 CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.6 CMOS compound gate for function Y (A B C) · . . . . . . . . . . . . . . . . . . 86
3.7 CMOS compound gate for function Y (A · B) (C · D) . . . . . . . . . . . . . . . 87
3.8 CMOS compound gate for function Y (A · B) (C · D) . . . . . . . . . . . . . . . 88
3.9 Pass transistor strong and degraded outputs . . . . . . . . . . . . . . . . . . . . 89
3.10 Transmission gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.11 foot dynamic invertar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.12 generalized footed and unfooted dynamic gates . . . . . . . . . . . . . . . . . . 91
3.13 incorrect connection of dynamic gates . . . . . . . . . . . . . . . . . . . . . . . 92
3.14 figure a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.15 figure b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.16 figure c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.1 4 x 4 crossbar switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.2 Barrel shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3 Full adder truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.4 Logic gate implementation of 1-Bit adder . . . . . . . . . . . . . . . . . . . . . 99
4.5 4-bit ripple carry adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.6 Full adder stage at i with Pi and Gi shown . . . . . . . . . . . . . . . . . . . . . 100
4.7 4-Bit carry lookahead adder implementation in detail . . . . . . . . . . . . . . . 100
4.8 An adder element based on the pass/generate concept . . . . . . . . . . . . . . . 101
4.9 Manchester cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.10 Cascaded Manchester carry-chain elements with buffering . . . . . . . . . . . . 102
4.11 bit multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.12 table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.13 Basic cell to construct a parallel multiplier . . . . . . . . . . . . . . . . . . . . . 104
4.14 Array multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.15 Even parity generator using logic gates . . . . . . . . . . . . . . . . . . . . . . . 106
4.16 Odd parity generator logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.17 One-zero detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.18 bit Digital Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.19 latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.20 transmission gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.21 Memories in a microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.22 SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.23 Read-Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.24 SRAM data retention waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.1 Barrel shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.2 PLA structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
List of Figures 7

5.3 PAL IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.4 FPGA Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Standard-Cells Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.6 Based Design 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.7 fault coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.8 fault detection effeciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.9 defect level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.10 a phase shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.11 Standard Linear Feedback Shift Register . . . . . . . . . . . . . . . . . . . . . . 131
5.12 Ones count compression circuit structure . . . . . . . . . . . . . . . . . . . . . . 131
5.13 Transition count compression circuit structure . . . . . . . . . . . . . . . . . . . 132
5.14 Syndrome testing circuit structure . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.15 BILBO Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Abbreviations

TVC Thrust Vector Control

LOX Liquid OXygen
LVDT Liquid Propellant Rocket Engine
RC Reinforced Concrete

8
Symbols

Del Elasticity tensor

σ Stress tensor
ε Strain tensor
Veq Equivalent velocity
ṁ Mass flow rate
Isp Specific Impulse
c Effective exhaust velocity
It Total impulse
υ Exhaust velocity
mp Propellant mass
me Empty mass
Aex Exit Area
pex Exhaust pressure
PSL−a Ambient pressure at sea level
FSL−a Sea level thrust of the rocket
W˙sp Specific propellant consumption rate
Cw Weight flow coefficient
Cf Thrust coefficient

9
Chapter 1

MOSFETS

Course Outcomes
After successful completion of this module, students should be able to:

1
Chapter 1. MOSFETS 2

CO 1 Describe the MOSFET fundamentals latest

trends in
the tech-
nology in
line with
forecast
made by
Moore for
computing
the param-
eters with
constant or
combined
scaling
models.
Understand
CO 2 Examine the conditions for optimum performance of inverters using Analyze
the volt- ampere and threshold voltage characteristics of MOSFETS.
CO 3 Explain the oxidation, diffusion, ion implantation & lithography pro- Understand
cesses for pmos, nmos, cmos and BiCMOS transistors fabrication.

1.1 Introduction

INTRODUCTION TO IC TECHNOLOGY:
The development of electronics endless with invention of vaccum tubes and associated electronic
circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid state
devices and consequent development of integrated circuits are responsible for the present status of
communication, computing and instrumentation.
• The first vaccum tube diode was invented by john ambrase Fleming in 1904. • The vaccum triode
was invented by lee de forest in 1906. Early developments of the Integrated Circuit (IC) go back
to 1949. German engineer Werner Jacobi filed a patent for an IC like semiconductor amplifying
Chapter 1. MOSFETS 3

device showing five transistors on a common substrate in a 2-stage amplifier arrangement. Jacobi
disclosed small cheap of hearing aids. Integrated circuits were made possible by experimental dis-
coveries which showed that semiconductor devices could perform the functions of vacuum tubes
and by mid-20th-century technology advancements in semiconductor device fabrication. The in-
tegration of large numbers of tiny transistors into a small chip was an enormous improvement
over the manual assembly of circuits using electronic components. The integrated circuits mass
production capability, reliability, and building-block approach to circuit design ensured the rapid
adoption of standardized ICs in place of designs using discrete transistors. An integrated circuit
(IC) is a small semiconductor-based electronic device consisting of fabricated transistors, resistors
and capacitors. Integrated circuits are the building blocks of most electronic devices and equip-
ment. An integrated circuit is also known as a chip or microchip. There are two main advantages
of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their
components, are printed as a unit by photolithography rather than being constructed one transistor
at a time. Furthermore, much less material is used to construct a packaged IC die than a dis-
crete circuit. Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and positioned close
together. As of 2006, chip areas range from a few square millimeters to around 350 mm2, with up
to 1 million transistors per mm

1.2 IC Invention:

1.2.1 Moore’s Law:

• Gordon E. Moore - Chairman Emeritus of Intel Corporation

• 1965 - observed trends in industry - of transistors on ICs vs release dates
• Noticed number of transistors doubling with release of each new IC generation
• Release dates (separate generations) were all 18-24 months apart
The level of integration of silicon technology as measured in terms of number of devices per IC
Semiconductor industry has followed this prediction with surprising accuracy.
Chapter 1. MOSFETS 4

1.3 Introduction

INTRODUCTION TO IC TECHNOLOGY:
The development of electronics endless with invention of vaccum tubes and associated electronic
circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid state
devices and consequent development of integrated circuits are responsible for the present status of
communication, computing and instrumentation.
• The first vaccum tube diode was invented by john ambrase Fleming in 1904.
• The vaccum triode was invented by lee de forest in 1906.
Early developments of the Integrated Circuit (IC) go back to 1949. German engineer Werner Ja-
cobi filed a patent for an IC like semiconductor amplifying device showing five transistors on a
common substrate in a 2-stage amplifier arrangement. Jacobi disclosed small cheap of hearing
aids. Integrated circuits were made possible by experimental discoveries which showed that semi-
conductor devices could perform the functions of vacuum tubes and by mid-20th-century technol-
ogy advancements in semiconductor device fabrication. The integration of large numbers of tiny
transistors into a small chip was an enormous improvement over the manual assembly of circuits
using electronic components. The integrated circuits mass production capability, reliability, and
building-block approach to circuit design ensured the rapid adoption of standardized ICs in place
of designs using discrete transistors. An integrated circuit (IC) is a small semiconductor-based
electronic device consisting of fabricated transistors, resistors and capacitors. Integrated circuits
are the building blocks of most electronic devices and equipment. An integrated circuit is also
known as a chip or microchip. There are two main advantages of ICs over discrete circuits: cost
and performance. Cost is low because the chips, with all their components, are printed as a unit by
photolithography rather than being constructed one transistor at a time. Furthermore, much less
material is used to construct a packaged IC die than a discrete circuit. Performance is high since
the components switch quickly and consume little power (compared to their discrete counterparts)
because the components are small and positioned close together. As of 2006, chip areas range
from a few square millimeters to around 350 mm2, with up to 1 million transistors per mm
Chapter 1. MOSFETS 5

1.3.1 IC Invention:

1.3.2 Moore’s Law:

• Gordon E. Moore - Chairman Emeritus of Intel Corporation

• 1965 - observed trends in industry - of transistors on ICs vs release dates
• Noticed number of transistors doubling with release of each new IC generation
• Release dates (separate generations) were all 18-24 months apart
The level of integration of silicon technology as measured in terms of number of devices per IC
Semiconductor industry has followed this prediction with surprising accuracy.

1.3.3 IC Technology:

• Speed / Power performance of available technologies

• The microelectronics evolution
• SIA Roadmap
• Semiconductor Manufacturers 2001 Ranking

1.4 Scale of Integration:

Small scale integration(SSI) –1960 The technology was developed by integrating the number
of transistors of 1-100 on a single chip. Ex: Gates, flip-flops, op-amps. Medium scale inte-
gration(MSI) –1967 The technology was developed by integrating the number of transistors of
100- 1000 on a single chip. Ex: Counters, MUX, adders, 4-bit microprocessors. Large scale
integration(LSI) –1972 The technology was developed by integrating the number of transistors
of 1000- 10000 on a single chip. Ex:8-bit microprocessors,ROM,RAM. Very large scale inte-
gration(VLSI) -1978 The technology was developed by integrating the number of transistors of
10000- 1Million on a single chip. Ex:16-32 bit microprocessors, peripherals, complimentary high
MOS. Ultra large scale integration(ULSI) The technology was developed by integrating the
number of transistors of 1Million- 10 Millions on a single chip. Ex: special purpose processors.
Giant scale integration(GSI) The technology was developed by integrating the number of tran-
sistors of above 10 Millions on a single chip. Ex: Embedded system, system on chip. .Fabrication
Chapter 1. MOSFETS 6

technology has advanced to the point that we can put a complete system on a single chip. .Single
chip computer can include a CPU, bus, I/O devices and memory. .This reduces the manufacturing
cost than the equivalent board level system with higher performance and lower power.

1.5 MOS TECHNOLOGY

MOS technology is considered as one of the very important and promising technologies in the
VLSI design process. The circuit designs are realized based on pMOS, nMOS, CMOS and BiC-
MOS devices. The pMOS devices are based on the p-channel MOS transistors. Specifically, the
pMOS channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the
source and drain electrodes. Generally speaking, a pMOS transistor is only constructed in con-
sort with an NMOS transistor. The nMOS technology and design processes provide an excellent
background for other technologies. In particular, some familiarity with nMOS allows a relatively
easy transition to CMOS technology and design. The techniques employed in nMOS technology
for logic design are similar to GaAs technology.. Therefore, understanding the basics of nMOS
design will help in the layout of GaAs circuits In addition to VLSI technology, the VLSI design
processes also provides a new degree of freedom for designers which helps for the significant de-
velopments. With the rapid advances in technology the the size of the ICs is shrinking and the
integration density is increasing. The minimum line width of commercial products over the years
is shown in the graph below.

F IGURE 1.1: IC shrinkage

The graph shows a significant decrease in the size of the chip in recent years which implicitly
indicates the advancements in the VLSI technology.
Chapter 1. MOSFETS 7

F IGURE 1.2: MOS TRANSISTOR SYMBOLS

1.5.1 MOS Transistor Symbol:

1.5.2 ENHANCEMENT AND DEPLETION MODE MOS TRANSISTORS

MOS Transistors are built on a silicon substrate. Silicon which is a group IV material is the eighth
most common element in the universe by mass, but very rarely occurs as the pure free element in
nature. It is most widely distributed in dusts, sands, planetoids, and planets as various forms of sil-
icon dioxide (silica) or silicates. It forms crystal lattice with bonds to four neighbours. Silicon is a
semiconductor. Pure silicon has no free carriers and conducts poorly. But adding dopants to silicon
increases its conductivity. If a group V material i.e. an extra electron is added, it forms an n-type
semiconductor. If a group III material i.e. missing electron pattern is formed (hole), the resulting
semiconductor is called a p-type semiconductor. A junction between p-type and n-type semi-
conductor forms a conduction path. Source and Drain of the Metal Oxide Semiconductor (MOS)
Transistor is formed by the “doped” regions on thesurface of chip. Oxide layer is formed by means
of deposition of the silicon dioxide (SiO2) layer which forms as an insulator and is a very thin pat-
tern. Gate of the MOS transistor is the thin layer of “polysilicon (poly)”; used to apply electric
field to the surface of silicon between Drain and Source, to form a “channel” of electrons or holes.
Control by the Gate voltage is achieved by modulating the conductivity of the semiconductor re-
gion just below the gate. This region is known as the channel. The Metal–Oxide–Semiconductor
Field Effect Transistor (MOSFET) is a transistor which is a voltage-controlled current device, in
which current at two electrodes, drain and source is controlled by the action of an electric field at
Chapter 1. MOSFETS 8

another electrode gate having in-between semiconductor and a very thin metal oxide layer. It is
used for amplifying or switching electronic signals. The Enhancement and Depletion mode MOS
transistors are further classified as N-type named NMOS (or N-channel MOS) and P-type named
PMOS (or P-channel MOS) devices. The depletion mode devices are doped so that a channel

F IGURE 1.3: (c) Enhancement P-type MOSFET (d) Depletion P-type MOSFET

exists even with zero voltage from gate to source during manufacturing of the device. Hence the
channel always appears in the device. To control the channel, a negative voltage is applied to the
gate (for an N-channel device), depleting the channel, which reduces the current flow through the
device. In essence, the depletion-mode device is equivalent to a closed (ON) switch, while the
enhancement-mode device does not have the built in channel and is equivalent to an open (OFF)
switch. Due to the difficulty of turning off the depletion mode devices, they are rarely used
Chapter 1. MOSFETS 9

1.5.3 Working of Enhancement Mode Transistor

The enhancement mode devices do not have the in-built channel. By applying the required po-
tentials, the channel can be formed. Also for the MOS devices, there is a threshold voltage (Vt),
below which not enough charges will be attracted for the channel to be formed. This threshold
voltage for a MOS transistor is a function of doping levels and thickness of the oxide layer.

1.5.4 Case 1: Vgs = 0V and Vgs < Vt

The device is non-conducting, when no gate voltage is applied (Vgs = 0V) or (Vgs ¡ Vt) and also
drain to source potential Vds = 0. With an insufficient voltage on the gate to establish the channel
region as N-type, there will be no conduction between the source and drain. Since there is no
conducting channel, there is no current drawn, i.e. Ids = 0, and the device is said to be in the
cut-off region.

F IGURE 1.4: Cut-off Region

1.5.5 Case 2:Vgs > Vt

When a minixmum voltage greater than the threshold voltage Vt (i.e. Vgs ¿ Vt) is applied, a high
concentration of negative charge carriers forms an inversion layer located by a thin layer next to
the interface between the semiconductor and the oxide insulator. This forms a channel between
the source and drain of the transistor. A positive Vds reverse biases the drain substrate junction,
hence the depletion region around the drain widens, and since the drain is adjacent to the gate edge,
the depletion region widens in the channel. This is shown in Figure 1.7 (c). This results in flow
Chapter 1. MOSFETS 10

F IGURE 1.5: formation of a channel

of electron from source to drain resulting in current Ids.. The device is said to operate in linear
region during this phase. Further increase in Vds, increases the reverse bias on the drain substrate
junction in contact with the inversion layer which causes inversion layer density to decrease. This
is shown in Figure 1.7 (d). The point at which the inversion layer density becomes very small
(nearly zero) at the drain end is termed pinch- off. The value of Vds at pinch-off is denoted as
Vds,sat. This is termed as saturation region for the MOS device. Diffusion current completes the
path from source to drain in this case, causing the channel to exhibit a high resistance and behaves
as a constant current source. The MOSFET ID versus VDS characteristics (V-I Characteristics) is

F IGURE 1.6: (c) Linear Region. (d) Saturation Region

shown in the Figure 1.8. For VGS ¡ Vt, ID = 0 and device is in cut-off region. As VDS increases at
a fixed VGS, ID increases in the linear region due to the increased lateral field, but at a decreasing
rate since the inversion layer density is decreasing. Once pinch-off is reached, further increase in
VDS results in increase in ID; due to the formation of the high field region which is very small.
The device starts in linear region, and moves into saturation region at higher VDS.
Chapter 1. MOSFETS 11

F IGURE 1.7: MOS V-I Characteristics

1.5.6 NMOS FABRICATION

The following description explains the basic steps used in the process of fabrication. (a) The fab-
rication process starts with the oxidation of the silicon substrate.
(b) A relatively thick silicon dioxide layer, also called field oxide, is created on the surface of the
substrate.
(c) Then, the field oxide is selectively etched to expose the silicon surface on which the MOS
transistor will be created.
(d) This is followed by covering the surface of substrate with a thin, high-quality oxide layer,
which will eventually form the gate oxide of the MOS transistor as illustrated
(e) On top of the thin oxide, a layer of polysilicon (polycrystalline silicon) is deposited .
Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect
medium in silicon integrated circuits. Undoped polysilicon has relatively high resistivity. The
resistivity of polysilicon can be reduced, however, by doping it with impurity atoms.
(f) After deposition, the polysilicon layer is patterned and etched to form the interconnects and the
MOS transistor gates.
(g) The thin gate oxide not covered by polysilicon is also etched along, which exposes the bare sil-
icon surface on which the source and drain junctions are to be formed (h) The entire silicon surface
is then doped with high concentration of impurities, either through diffusion or ion implantation
(in this case with donor atoms to produce n-type doping).
Diffusion is achieved by heating the wafer to a high temperature and passing the gas containing
desired impurities over the surface. shows that the doping penetrates the exposed areas on the
Chapter 1. MOSFETS 12

silicon surface, ultimately creating two n-type regions (source and drain junctions) in the p-type
substrate.
The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity.
(i) Once the source and drain regions are completed, the entire surface is again covered with an
insulating layer of silicon dioxide,
(j) The insulating oxide layer is then patterned in order to provide contact windows for the drain
and source junctions.

F IGURE 1.8: Fabrication Process of NMOS Device

Chapter 1. MOSFETS 13

1.6 CMOS FABRICATION:

CMOS fabrication can be accomplished using either of the three technologies:

• N-well technologies/P-well technologies

• Twin well technology
• Silicon On Insulator (SOI)
The fabrication of CMOS can be done by following the below shown twenty steps, by which
CMOS can be obtained by integrating both the NMOS and PMOS transistors on the same chip
substrate. For integrating these NMOS and PMOS devices on the same chip, special regions called
as wells or tubs are required in which semiconductor type and substrate type are opposite to each
other. A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate.
In this article, the fabrication of CMOS is described using the P-substrate, in which the NMOS
transistor is fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.

1.6.1 N-Well Process

Step1: Substrate
Primarily, start the process with a P-substrate.

F IGURE 1.9

Step2:Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in
an oxidation furnace approximately at 1000 degree centigrade. Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as Photoresist layer.It is
formed.
Step4:Masking
The photoresist is exposed to UV rays through the N-well mask
Chapter 1. MOSFETS 14

F IGURE 1.10

F IGURE 1.11

Step5:Photoresist Removal
A part of the photoresist layer is removed by treating the wafer with the basic or acidic solutio n.
Step6: Removal of SiO2 using acid etching
The SiO2 oxidation layer is removed through the open area made by the removal of photoresist
using hydrofluoric acid.
Step7: Removal of photoresist
The entire photoresist layer is stripped off.
Step8: Formation of the N-well
By using ion implantation or diffusion process N-well is formed.
Step9: Removal of SiO2
Using the hydrofluoric acid, the remaining SiO2 is removed.
Step10:Deposition of Polysilicon
Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate oxide.
Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and PMOS, the remaining
layer is stripped off.
Step12: Oxidation process
Next, an oxidation layer is formed on this layer with two small regions for the formation of the
gate terminals of NMOS and PMOS.
Step13: Masking and N-diffusion
By using the masking process small gaps are made for the purpose of N -diffusion.
The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the forma-
tion of the terminals of NMOS.
Step14: Oxide Stripping
Chapter 1. MOSFETS 15

The remaining oxidation layer is stripped off.

Step15: P-Diffusion
Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the terminals
of the PMOS.
Step16: Thick Field Oxide
A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.
Step17: Metalisation
Aluminium is sputtered on the whole wafer
Step18: Removal of excess metal
The excess metal is removed from the wafer layer.
Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps
Step20: Assigning the names of terminals of the NMOS AND PMOS
Fabrication of CMOS using P-well process:
Among all the fabrication processes of the CMOS, N-well process is mostly used for the fabrica-
tion of the CMOS. P-well process is almost similar to the N-well. But the only difference in p-well
process is that it consists of a main N-substrate and, thus, P-wells itself acts as substrate for the N-
devices.
Twin-Tub fabrication process: In this process, separate optimization of the n-type and p-type

F IGURE 1.12

transistors will be provided. The independent optimization of Vt, body effect and gain of the P-
devices, N-devices can be made possible with this process. Different steps of the fabrication of the
CMOS using the twintub process are as follows:
Chapter 1. MOSFETS 16

• Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is used.
• The high-purity controlled thickness of the layers of silicon are grown with exact dopant concen-
trations.
• The dopant and its concentration in Silicon are used to determine electrical properties.
• Formation of the tub
• Thin oxide construction
• Implantation of the source and drain
• Cuts for making contacts
• Metallization
By using the above steps we can fabricate CMOS using twin tub process method
Silicon-on-Insulator (SOI) CMOS Process Rather than using silicon as the substrate material,
technologists have sought to use an insulating substrate to improve process characteristics such as
speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent,
completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
The main advantages of this technology are the higher integration density (because of the absence
of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances
compared to the conventional p n-well or twin- tub CMOS processes. A cross-section of nMOS
and pMOS devicesusing SOI process is shown below. The SOI CMOS process is considerably

F IGURE 1.13

more costly than the standard p n-well CMOS process. Yet the improvements of device perfor-
mance and the absence of latch-up problems can justify its use, especially for deep-sub-micron
devices.
Chapter 1. MOSFETS 17

1.7 Basic Electrical Properties of MOS and Bi CMOS circuits

1.7.1 ID −VDS Characteristics of MOS Transistor :

The graph below shows the ID −VDS characteristics of an n- MOS transistor for several values of
Vgs .It is clear that there are two conduction states when the device is ON. The saturated state and
the non-saturated state. The saturated curve is the flat portion and defines the saturation region.
.For Vgs ¡ VDS + Vt h , the nMOS device is conducting and ID is independent of VDS . .For Vgs ¿
VDS + Vt h , the transistor is in the non-saturation region and the curve is a half parabola. .When the
transistor is OFF (Vgs < Vt h ), then ID is zero for any VDS value. The boundary of the saturation/non-

F IGURE 1.14: Depletion mode device

saturation bias states is a point seen for each curve in the graph as the intersection of the straight
line of the saturated region with the quadratic curve of the non- saturated region. This intersection
point occurs at the channel pinch off voltage called VDSAT . The diamond symbol marks the pinch-
off voltage VDSAT for each value of VGS . VDSAT is defined as the minimum drain-source voltage that
is required to keep the transistor in saturation for a given VGS . In the non-saturated state, the drain
current initially increases almost linearly from the origin before bending in a parabolic response.
Thus the name ohmic or linear for the non- saturated region.The drain current in saturation is
virtually independent of VDS and the transistor acts as a current source. This is because there is no
carrier inversion at the drain region of the channel. Carriers are pulled into the high electric field
of the drain/substrate pn junction and ejected out of the drain terminal.
Chapter 1. MOSFETS 18

F IGURE 1.15: Enhancement device

1.7.2 Drain-to-Source Current IDS Versus Voltage VDS Relationships:

The working of a MOS transistor is based on the principle that the use of a voltage on the gate
induce a charge in the channel between source and drain, which may then be caused to move from
source to drain under the influence of an electric field created by voltage Vd s applied between drain
and source. Since the charge induced is dependent on the gate to source voltage Vgs then Id s is de-
pendent on both Vgs and Vd s .
Let us consider the diagram below in which electrons will flow source to drain .So,the drain cur-
rent is given by Charge induced in channel =Qc Id s = −Isd Electron transit time=τ Length of the
channel=L transit time is given by (τsd ) = Lengtho f thechannel(L)/Velocity(v)

F IGURE 1.16: nMos structure

But velocity V=µEds Where µ =electron or hole mobility Ed s = Electric field also Ed s = Vd s /L
Chapter 1. MOSFETS 19

so,v = µ.Vd s /L and ds = L2 /.V ds The typical values of µ at room temperature are given below.
µn = 650cm2 /V sec µn = 240cm2 /V sec

1.7.3 Non-saturated Region :

Let us consider the Id vs Vd relationships in the non-saturated region .The charge induced in the
channel due to due to the voltage difference between the gate and the channel, Vgs (assuming sub-
strate connected to source). The voltage along the channel varies linearly with distance X from
the source due to the IR drop in the channel .In the non-saturated state the average value is Vds/2.
Also the effective gate voltage Vg = Vgs – Vt where Vt, is the threshold voltage needed to invert
the charge under the gate and establish the channel.

Hence the induced charge is QC =Eg εins ε0 W.L

Where Eg = average electric field gate to channel
epsilonins = relative permittivity of insulation between gate and channel epsilono =permittivity of
free space Eg =(Vgs −Vt )- V2ds D
Here D is the thickness of the oxide layer. Thus
Qc = W LεDins ε0 (Vgs −Vt )−Vds 2
So, by combining the above two equations ,we get
Ids = εinsD∈0 WL ((Vgs −Vt )- V2ds )Vds
2
Vds
or the above equation can be written as Ids = εinsD∈0 WL ((Vgs −Vt )Vds -
In the non-saturated or resistive region where Vds < Vgs −Vt and
K = εins .ε0 .µ/D
Generally ,a constant β is defined as So that ,the e β = K ∗W /L So that ,the expression for drain
–source current will become
2
Ids =β ((Vgs −Vt )Vds − Vd2s )
The gate /channel capacitance is
Cg = εins .ε0 .W.L/D
Hence we can write another alternative form for the drain current as
2
Ids =(Cg /µ)/L2 ∗ ((Vgs −Vt )Vds − Vd2s )
Some time it is also convenient to use gate –capacitance per unit area ,Cg So,the drain current is
Chapter 1. MOSFETS 20

2
Ids =(Co /µ)W /L ∗ ((Vgs −Vt )Vds − Vd2s )

This is the relation between drain current and drain-source voltage in non-saturated region.
Saturated Region
Saturation begins when V ds = V gs − V , since at this point the IR drop in the channel equals the
effective gate to channel voltage at the drain and we may assume that the current remains fairly
constant as Vds increases further. Thus Ids =(KW /L) ∗ ((Vgs −Vt )2 /2
or we can also write that
Ids =(β /2) ∗ ((Vgs −Vt )2
Ids =(Cg ∗ µ ∗W /2 ∗ L) ∗ ((Vgs −Vt )2
The expressions derived above for Ids hold for both enhancement and depletion mode devices.
Here the threshold voltage for the nMOS depletion mode device (denoted as Vtd ) is negative.
MOS Transistor Threshold Voltage Vt :
The gate structure of a MOS transistor consists, of charges stored in the dielectric layers and in
the surface to surface interfaces as well as in the substrate itself. Switching an enhancement mode
MOS transistor from the off to the on state consists in applying sufficient gate voltage to neutralize
these charges and enable the underlying silicon to undergo an inversion due to the electric field
from the gate. Switching a depletion mode nMOS transistor from the on to the off state consists in
applying enough voltage to the gate to add to the stored charge and invert the ’n’ implant region to
’p’.
The threshold voltage Vt may be expressed as:
Vt =φms ∗ (QB − Qs s)/Co +2φ f N
where QD = the charge per unit area in the depletion layer below the oxide Qss = chargedensityatSi:
SiO2inter f ace
Co =Capacitance per unit area.
φms = work function difference between gate and Si
φ f N = Fermi level potential between inverted surface and bulk Si
For polynomial gate and silicon substrate, the value of ns is negative but negligible and the magni-
tude and sign of Vt are thus determined by balancing the other terms in the equation. To evaluate
the Vt the other terms are determined as below.

Body Effect :
Chapter 1. MOSFETS 21

F IGURE 1.17

Generally while studying the MOS transistors it is treated as a three terminal device. But, the body
of the transistor is also an implicit terminal which helps to understand the characteristics of the
transistor. Considering the body of the MOS transistor as a terminal is known as the body effect.
The potential difference between the source and the body (Vsb) affects the thresholdvoltage of
the transistor. In many situations, this Body Effect is relatively insignificant, so we can (unless
otherwise stated) ignore the Body Effect. But it is not always insignificant, in some cases it can
have a tremendous impact on MOSFET circuit performance.

F IGURE 1.18

Body effect - nMOS device

Increasing Vsb causes the channel to be depleted of charge carriers and thus the threshold voltage
is raised. Change in Vt is given by Vt = .(Vsb)1/2 where is a constant which depends on substrate
doping so that the more lightly doped the substrate, the smaller will be the body effect The thresh-
old voltage can be written as
1
△Vt =γ.(Vs b) 2
Chapter 1. MOSFETS 22

F IGURE 1.19

where is a constant which depends on substrate doping so that the more lightly doped the sub-
strate, the smaller will be the body effect The threshold voltage can be written as
1/2
Vt =Vt (0)+( εinsDε0 ) 2ε0 εs f QN.Vsb
p

Where Vt(0) is the threshold voltage for Vsd = 0 For n-MOS depletion mode transistors ,the body
voltage values at different VDD voltages are given below. VSB = 0 V ; Vsd = -0.7VDD (= - 3.5 V
for VDD =+5V ) VSB = 5 V ; Vsd = -0.6;VDD (= - 3.0 V for VDD =+5V )
nMOS INVERTER :
An inverter circuit is a very important circuit for producing a complete range of logic circuits.
This is needed for restoring logic levels, for Nand and Nor gates, and for sequential and memory
circuits of various forms . A simple inverter circuit can be constructed using a transistor with
source connected to ground and a load resistor of connected from the drain to the positive supply
rail VDD· The output is taken from the drain and the input applied between gate and ground . But,
during the fabrication resistors are not conveniently produced on the silicon substrate and even
small values of resistors occupy excessively large areas .Hence some other form of load resistance
is used. A more convenient way to solve this problem is to use a depletion mode transistor as the
load, as shown in Fig. below.

F IGURE 1.20

The salient features of the n-MOS inverter are

• For the depletion mode transistor, the gate is connected to the source so it is always on .
Chapter 1. MOSFETS 23

• In this configuration the depletion mode device is called the pull-up (P.U) and the enhancement
mode device the pull-down (P.D) transistor.
• With no current drawn from the output, the currents Ids for both transistors must be equal.
nMOS Inverter transfer characteristic.
The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-axis for both enhance-
ment and depletion mode transistors. So,to obtain the inverter transfer characteristic forVgs = 0
depletion mode characteristic curve is superimposed on the family of curves for the enhancement
mode device and from the graph it can be seen that , maximum voltage across the enhancement
mode device corresponds to minimum voltage across the depletion mode transistor.

F IGURE 1.21

From the graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown threshold voltage
current begins to flow. The output voltage Vout thus decreases and the subsequent increases in Vin
will cause the Pull down transistor to come out of saturation and become resistive.
CMOS Inverter:
The inverter is the very important part of all digital designs. Once its operation and properties
are clearly understood, Complex structures like NAND gates, adders, multipliers, and micropro-
cessors can also be easily done. The electrical behavior of these complex circuits can be almost
completely derived by extrapolating the results obtained for inverters. As shown in the diagram
below the CMOS transistor is designed using p-MOS and n-MOS transistors.
Chapter 1. MOSFETS 24

F IGURE 1.22

In the inverter circuit ,if the input is high .the lower n-MOS device closes to discharge the ca-
pacitive load .Similarly ,if the input is low,the top p-MOS device is turned on to charge the ca-
pacitive load .At no time both the devices are on ,which prevents the DC current flowing from
positive power supply to ground. Qualitatively this circuit acts like the switching circuit, since
the p-channel transistor has exactly the opposite characteristics of the n-channel transistor. In the
transition region both transistors are saturated and the circuit operates with a large voltage gain.
The C-MOS transfer characteristic is shown in the below graph. Considering the static conditions
first, it may be Seen that in region 1 for which Vi,. = logic 0, we have the p-transistor fully turned
on while the n-transistor is fully turned off. Thus no current flows through the inverter and the
output is directly connected to VDD through the p-transistor.

F IGURE 1.23

Hence the output voltage is logic 1 . In region 5 , Vin = logic 1 and the n-transistor is fully on
Chapter 1. MOSFETS 25

while the p-transistor is fully off. So, no current flows and logic 0 appears at the output. In re-
gion 2 the input voltage has increased to a level which just exceeds the threshold voltage of the
n-transistor. The n-transistor conducts and has a large voltage between source and drain; so it is in
saturation. The p-transistor is also conducting but with only a small voltage across it, it operates in
the unsaturated resistive region. A small current now flows through the inverter from VDD to VSS.
If we wish to analyze the behavior in this region, we equate the p-device resistive region current
with the n-device saturation current and thus obtain the voltage and current relationships. Region
4 is similar to region 2 but with the roles of the p- and n-transistors reversed.However, the current
magnitudes in regions 2 and 4 are small and most of the energy consumed in switching from one
state to the other is due to the larger current which flows in region 3. Region 3 is the region in
which the inverter exhibits gain and in which both transistors are in saturation. The currents in
each device must be the same ,since the transistors are in series. So,we can write that

F IGURE 1.24

Since both transistors are in saturation, they act as current sources so that the equivalent circuit in
this region is two current sources in series between VDD and Vss with the output voltage coming
from their common point. The region is inherently unstable in consequence and the changeover
from one logic level to the other is rapid.
Determination of Pull-up to Pull –Down Ratio (Zp.uZp.d.)for an nMOS Inverter driven by an-
other nMOS Inverter :
Let us consider the arrangement shown in Fig.(a). in which an inverter is driven from the output
of another similar inverter. Consider the depletion mode transistor for which Vgs = 0 under all
conditions, and also assume that in order to cascade inverters without degradation the condition
Fig.(a).Inverter driven by another inverter. For equal margins around the inverter threshold, we set
Vinv = 0.5VDD · At this point both transistors are in saturation and we can write that
Chapter 1. MOSFETS 26

F IGURE 1.25

F IGURE 1.26

F IGURE 1.27

F IGURE 1.28

F IGURE 1.29

where Wp.d , Lp.d , Wp.u. and Lp.u are the widths and lengths of the pull-down and pull-up
transistors respectively. So,we can write that

The typical, values for Vt ,Vinv and Vtd are

Chapter 1. MOSFETS 27

F IGURE 1.30

F IGURE 1.31

F IGURE 1.32

F IGURE 1.33

ubstituting these values in the above equation ,we get

F IGURE 1.34

Here

This is the ratio for pull-up to pull down ratio for an inverter directly driven by another inverter.
Chapter 1. MOSFETS 28

F IGURE 1.35

F IGURE 1.36

Pull -Up to Pull-Down ratio for an nMOS Inverter driven through one or more Pass Tran-
sistors
Let us consider an arrangement in which the input to inverter 2 comes from the output of inverter
1 but passes through one or more nMOS transistors as shown in Fig. below (These transistors are
called pass transistors).

F IGURE 1.37

The connection of pass transistors in series will degrade the logic 1 level / into inverter 2 so that
the output will not be a proper logic 0 level. The critical condition is , when point A is at 0 volts
and B is thus at VDD. but the voltage into inverter 2at point C is now reduced from VDD by the
threshold voltage of the series pass transistor. With all pass transistor gates connected to VDD
there is a loss of Vtp, however many are connected in series, since no static current flows through
them and there can be no voltage drop in the channels. Therefore, the input voltage to inverter 2 is
Vin2 = VDD- Vtp where Vtp = threshold voltage for a pass transistor. Let us consider the inverter
1 shown in Fig.(a) with input = VDD· If the input is at VDD , then the pull-down transistor T2 is
conducting but with a low voltage across it; therefore, it is in its resistive region represented by
R1 in Fig.(a) below. Meanwhile, the pull up transistor T1 is in saturation and is represented as a
current source. For the pull down transistor
Chapter 1. MOSFETS 29

F IGURE 1.38

F IGURE 1.39

Now, for depletion mode pull-up transistor in saturation with Vgs = 0

F IGURE 1.40

The product 1R1 = Vout1So,

Chapter 1. MOSFETS 30

F IGURE 1.41

F IGURE 1.42

Whence,

F IGURE 1.43

If inverter 2 is to have the same output voltage under these conditions then Vout1 = Vout2. That is
I1R1=I2R2 , therefore

F IGURE 1.44

Considering the typical values

F IGURE 1.45

Therefore
Chapter 1. MOSFETS 31

F IGURE 1.46

F IGURE 1.47

From the above theory it is clear that, for an n-MOS transistor

(i). An inverter driven directly from the output of another should have a Zp.u/ Zpd. ratio of 4/1.
(ii).An inverter driven through one or more pass transistors should have a Zp.u./Zp.d ratio of 8/1
ALTERMTIVE FORMS OF PULL –UP
Generally the inverter circuit will have a depletion mode pull-up transistor as its load. But there
are also other configurations .Let us consider four such arrangements.

1.7.4 (i).Load resistance RL :

This arrangement consists of a load resistor as apull-up as shown in the diagram below.But it is not
widely used because of the large space requirements of resistors produced in a silicon substrate.

1.7.5 nMOS depletion mode transistor pull-up :

This arrangement consists of a depletion mode transistor as pull-up. The arrangement and the
transfer characteristic are shown below.In this type of arrangement we observe
(a) Dissipation is high , since rail to rail current flows when Vin = logical 1.
(b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.
Chapter 1. MOSFETS 32

F IGURE 1.48

F IGURE 1.49

nMOS depletion mode transistor pull-up and transfer characteristic

(c) When switching the output from 1 to 0, the pull-up device is non-saturated initially and this
presents lower resistance through which to charge capacitive loads .
(ii) nMOS enhancement mode pull-up :This arrangement consists of a n-MOS enhancement
mode transistor as pull-up. The arrangement and the transfer characteristic are shown below.

nMOS enhancement mode pull-up and transfer characteristic The important features of this
arrangement are (a) Dissipation is high since current flows when Vin =logical 1 (VGG is returned
to VDD) .
(b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the case.
Chapter 1. MOSFETS 33

F IGURE 1.50

(c) VGG may be derived from a switching source, for example, one phase of a clock, so thatdissi-
pation can be greatly reduced.
(d) If VGG is higher than VDD then an extra supply rail is required.
(iii)Complementary transistor pull-up (CMOS) : This arrangement consists of a C-MOS ar-
rangement as pull-up. The arrangement and the transfer characteristic are shown below

F IGURE 1.51

The salient features of this arrangement are

(a) No current flows either for logical 0 or for logical 1 inputs.
Chapter 1. MOSFETS 34

(b) Full logical 1 and 0 levels are presented at the output.

(c) For devices of similar dimensions the p-channel is slower than the n-channel device.

1.8 BiCMOS INVERTER:

A BiCMOS inverter, consists of a PMOS and NMOS transistor ( M2 and M1), two NPN bipolar
junction transistors,( Q2 and Q1), and two impedances which act as loads( Z2 and Z1) as shown
in the circuit below.

F IGURE 1.52

When input, Vin, is high (VDD), the NMOS transistor ( M1), turns on, causing Q1 to con-
duct,while M2 and Q2 are off, as shown in figure (b) . Hence , a low (GND) voltage is translated to
the output Vout. On the other hand, when the input is low, the M2 and Q2 turns on, while M1and
Q1 turns off, resulting to a high output level at the output as shown in Fig.(b). In steady-state op-
eration, Q1 and Q2 never turns on or off simultaneously, resulting to a lower power consumption.
This leads to a push-pull bipolar output stage. Transistors M1and M2, on the other hand, works as
a phase-splitter, which results to a higher input impedance.

The impedances Z2 and Z1 are used to bias the base-emitter junction of the bipolar transistor and
Chapter 1. MOSFETS 35

F IGURE 1.53

to ensure that base charge is removed when the transistors turn off. For example when the input
voltage makes a high-to-low transition, M1 turns off first. To turn off Q1, the base charge must
be removed, which can be achieved by Z1.With this effect, transition time reduces. However,there
exists a short time when both Q1 and Q2 are on, making a direct path from the supply (VDD) to
the ground. This results to a current spike that is large and has a detrimental effect on both the
noise and power consumption, which makes the turning off of the bipolar transistor fast .

1.8.1 Comparison of BiCMOS and C-MOS technologies

The BiCMOS gates perform in the same manner as the CMOS inverter in terms of power consump-
tion, because both gates display almost no static power consumption. When comparing BiCMOS
and CMOS in driving small capacitive loads, their performance are comparable, however, making
BiCMOS consume more power than CMOS. On the other hand, driving larger capacitive loads
makes BiCMOS in the advantage of consuming less power than CMOS, because the construc-
tion of CMOS inverter chains are needed to drive large capacitance loads, which is not needed
in BiCMOS. The BiCMOS inverter exhibits a substantial speed advantage over CMOS inverters,
especially when driving large capacitive loads. This is due to the bipolar transistor’s capability of
effectively multiplying its current. For very low capacitive loads, the CMOS gate is faster than its
BiCMOS counterpart due to small values of Cint. This makes BiCMOS ineffective when it comes
to the implementation of internal gates for logic structures such as ALUs, where associated load
Chapter 1. MOSFETS 36

capacitances are small. BiCMOS devices have speed degradation in the low supply voltage region
and also BiCMOS is having greater manufacturing complexity than CMOS.
Chapter 2

VLSI DESIGN STYLES

Course Outcomes
After successful completion of this module, students should be able to:
CO 1 Describe the MOSFET fundamentals latest trends in the technology in Understand
line with forecast made by Moore for computing the parameters with
constant or combined scaling models.
CO 4 Build different design concepts implemented in chemical rocket engine Apply
using lambda, absolute and Euler physical design rules.
CO 5 Summarize the reliability issues in interconnects, latching and electro Understand
migration for formulating remedial measurements to increase lifetime.

2.1 VLSI DESIGN FLOW

A design flow is a sequence of operations that transform the IC designers’ intention (usually rep-
resented in RTL format) into layout GDSII data. A well-tuned design flow can help designers
go through the chip-creation process relatively smoothly and with a decent chance of error-free
implementation. And, a skilful IC implementation

37
Chapter 2. VLSI DESIGN STYLES 38

F IGURE 2.1: VLSI DESIGN FLOW

2.1.1 Front-end design (Logical design):

1. Design entry – Enter the design in to an ASIC design system using a hardware description
language (HDL) or schematic entry.

2. Logic synthesis – Generation of net list (logic cells and their connections) from HDL code.
Logic synthesis consists of following steps: (i) Technology independent Logic optimization
(ii) Translation: Converting Behavioral description to structural domain (iii) Technology
mapping or Library binding.

3. System partitioning - Divide a large system into ASIC-sized pieces.

4. Pre-layout simulation - Check to see if the design functions correctly. Gate level function-
ality and timing details can be verified.
Chapter 2. VLSI DESIGN STYLES 39

2.1.2 Back-end design (Physical design):

1. Floor planning - Arrange the blocks of the netlist on the chip

2. Placement - Decide the locations of cells in a block

3. Routing - Make the connections between cells and blocks

4. Circuit Extraction - Determine the resistance and capacitance of the interconnect.

5. Post-layout simulation - Check to see the design still works with the added loads of the
interconnect.

2.2 MOS LAYERS

MOS design is aimed at turning a specification into masks for processing silicon to meet the spec-
ification. We have seen that MOS circuits are formed on four basic layers.
• N-diffusion
• P-diffusion
• Poly Si
• Metal which are isolated from one another by thick or thin (thinox) silicon silicon dioxide insu-
lating layers. The thin oxide (thinox) mask region includes n-diffusion, p-diffusion, and transistor
channels. Polysilicon and thinox regions interact so that a transistor is formed where they cross
one another.

2.3 STICK DIAGRAMS

A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a model
for design of full layout from traditional transistor schematic. Stick diagrams are used to convey
the layer information with the help of a color code. “A stick diagram is a cartoon of a layout.”
Chapter 2. VLSI DESIGN STYLES 40

2.4 NMOS and CMOS Design Style :

To understand the design rules for nMOS design style , let us consider a single metal, single
polysilicon nMOS technology. The layout of nMOS is based on the following important features.
• n-diffusion [n-diff.] and other thin oxide regions [thinox] (green) ;
• polysilicon 1 [poly.]-since there is only one polysilicon layer here (red);
• metal 1 [metal]-since we use only one metal layer here (blue);
• implant (yellow);
• contacts (black or brown [buried]). A transistor is formed wherever poly. crosses n-diff. (red
over green) and all diffusion wires (interconnections) are n-type (green).When starting a layout,
the first step normally taken is to draw the metal (blue) VDD and GND rails in parallel allowing
enough space between them for the other circuit elements which will be required. Next, thinox
(green) paths may be drawn between the rails for inverters and inverter based logic as shown in Fig.
below. Inverters and inverter- based logic comprise a pull-up structure, usually a depletion mode
transistor, connected from the output point to VDD and a pull down structure of enhancement
mode transistors suitably interconnected between the output point and GND. This is illustrated in
the Fig.(b). remembering that poly. (red) crosses thinox (green)wherever transistors are required.
One should consider the implants (yellow) for depletion mode transistors and also consider the
length to width (L:W) ratio for each transistor. These ratios are important particularly in nMOS
and nMOS- like circuits.
Figure shows the way of representing different layers in stick diagram notation and mask layout
using nmos style. Figure1 shows when a n-transistor is formed: a transistor is formed when a
green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion
mode transistor is represented in the stick format. Figure CMOS ENCODING shows when a n-
transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly)
completely. Figure CMOS ENCODING also shows when a p-transistor is formed: a transistor is
formed when a yellow line(p+ diffusion) crosses a red line (poly) completely. There are several
layers in an nMOS chip:

1. a p-type substrate

2. paths of n-type diffusion

3. a thin layer of silicon dioxide

Chapter 2. VLSI DESIGN STYLES 41

F IGURE 2.2: nMOS ENCODING

4. paths of polycrystalline silicon

5. a thick layer of silicon dioxide

paths of metal (usually aluminium) a further thick layer of silicon dioxide with contact cuts through
the silicon dioxide where connections are required. The three layers carrying paths can be con-
sidered as independent conductors that only interact where polysilicon crosses diffusion to form a
transistor. These tracks can be drawn as stick diagrams with diffusion in green polysilicon in red
metal in blue using black to indicate contacts between layers and yellow to mark regions of im-
plant in the channels of depletion mode transistors. With CMOS there are two types of diffusion:
n- type is drawn in green and p-type in brown. These are on the same layers in the chip and must
not meet. In fact, the method of fabrication required that they be kept relatively far apart. Modern
CMOS processes usually support more than one layer of metal. Two are common and three or
more are often available. Actually, these conventions for colors are not universal; in particular,
industrial (rather than academic) systems tend to use red for diffusion and green for polysilicon.
Chapter 2. VLSI DESIGN STYLES 42

Moreover, a shortage of colored pens normally means that both types of diffusion in CMOS are
colored green and the polarity indicated by drawinga circle round p-type transistors or simply in-
ferred from the context. Colorings for multiple layers of metal are even less standard. The CMOS
design rules are almost similar and extensions of n-MOS design rules except the Implant (yellow)
and the buried contact (brown). In CMOS design Yellow is used to identify p transistors and wires,
as depletion mode devices are not utilized. The two types of transistors ’n’ and ’p’, are separated
by the demarcation line (representing the p-well boundary) above which all p-type devices are
placed (transistors and wires (yellow). The n-devices (green) are consequently placed below the
demarcation line and are thus located in the p-well as shown in the diagram below.

F IGURE 2.3: nMOS depletion mode inverter

The above fig shows schematic, stick diagram and corresponding layout of nMOS depletion load
inverter

F IGURE 2.4: NMOS DEPLETION NAND NOR

Figure below shows the stick diagram nMOS implementation of the function f = [(xy) + z]′
Chapter 2. VLSI DESIGN STYLES 43

F IGURE 2.5: NMOS DEPLETION example for function F

F IGURE 2.6: CMOS INVERTER

F IGURE 2.7: CMOS NAND1

2.5 Stick Diagrams – Some Rules

• Rule 1: When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

• Rule 2: When two or more “sticks” of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection explicitly).
Chapter 2. VLSI DESIGN STYLES 44

F IGURE 2.8: Rule 2

• Rule 3: When a poly crosses diffusion it represents a transistor.

F IGURE 2.9: Rule 3

• Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All
PMOS must lie on one side of the line and all NMOS will have to be on the other side.

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires must not
join. The ’n’ and ’p’ features are normally joined by metal where a connection is needed. Their
geometry will appear when the stick diagram is translated to a mask layout. However, one must
not forget to place crosses on VDD and Vss rails to represent the substrate and p-well connection
Chapter 2. VLSI DESIGN STYLES 45

F IGURE 2.10: Rule 4 Demarcation line

F IGURE 2.11: CMOS transistor

respectively. The design style is explained by taking the example the design of a single bit shift
register. The design begins with the drawing of the VDD and Vss rails in parallel and in metal
and the creation of an (imaginary) demarcation line in-between, as shown in Fig.below. The n-
transistors are then placed below this line and thus close to Vss, while p-transistors are placed
above the line and below VDD In both cases, the transistors are conveniently placed with their
diffusion paths parallel to the rails (horizontal in the diagram) as shown in Fig.(b). A similar
approach can be taken with transistors in symbolic form.

2.6 Design Rules and Layout :

In VLSI design, as processes become more and more complex, need for the designer to under-
stand the intricacies of the fabrication process and interpret the relations between the different
photo masks is really troublesome. Therefore, a set of layout rules, also called design rules, has
been defined. They act as an interface or communication link between the circuit designer and the
process engineer during the manufacturing phase. The objective associated with layout rules is to
Chapter 2. VLSI DESIGN STYLES 46

F IGURE 2.12: CMOS stick layout design style

obtain a circuit with optimum yield (functional circuits versus non-functional circuits) in as small
as area possible without compromising reliability of the circuit. In addition, Design rules can be
conservative or aggressive, depending on whether yield or performance is desired. Generally, they
are a compromise between the two. Manufacturing processes have their inherent limitations in
accuracy. So the need of design rules arises due to manufacturing problems like –
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.
• Impurities.
• Variations across a wafer. These lead to various problems like
• Transistor problems:
Variations in threshold voltage: This may occur due to variations in oxide thickness, ion- implan-
tation and poly layer. Changes in source/drain diffusion overlap. Variations in substrate.
• Wiring problems:
Diffusion: There is variation in doping which results in variations in resistance, capacitance. Poly,
metal: Variations in height, width resulting in variations in resistance, capacitance. Shorts and
opens.
Chapter 2. VLSI DESIGN STYLES 47

• Oxide problems: Variations in height. Lack of planarity.

• Via problems:Via may not be cut all the way through.
Undersize via has too much resistance.
Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain geometric constraints
on the layout artwork so that the patterns on the processed wafers will preserve the topology and
geometry of the designs. This consists of minimum-width and minimum-spacing constraints and
requirements between objects on the same or different layers. Apart from following a definite set
of rules, design rules also come by experience.

2.7 Why we use design rules?:

• Interface between designer and process engineer

• Historically, the process technology referred to the length of the silicon channel between the
source and drain terminals in field effect transistors.

• The sizes of other features are generally derived as a ratio of the channel length, where some
may be larger than the channel size and some smaller. For example, in a 90 nm process, the
length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

F IGURE 2.13: semiconductor manufacturing technology

Chapter 2. VLSI DESIGN STYLES 48

Design rules define ranges for features Examples:

• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
• Required for resolution/tolerances of masks Fabrication processes defined by minimum channel
width
• Also minimum width of poly traces defines “how fast” a fabrication process is.

2.8 Types of Design Rules:

The design rules primary address two issues:

1. The geometrical reproduction of features that can be reproduced by the maskmaking and litho-
graphical process, and
2. The interaction between different layers. There are primarily two approaches in describing the
design rules.

• Linear scaling is possible only over a limited range of dimensions.

• Scalable design rules are conservative .This results in over dimensioned and less dense de-
sign.

• This rule is not used in real life.

2.9 Scalable Design Rules :e.g. SCMOS, λ -based design rules

In this approach, all rules are defined in terms of a single parameter λ x.The rules are so chosen
that a design can be easily ported over a cross section of industrial process making the layout
portable .Scaling can be easily done by simply changing the value of.

2.10 Absolute Design Rules:e.g. µ -based design rules

In this approach, the design rules are expressed in absolute dimensions (e.g. 0.75 µm ) and there-
fore can exploit the features of a given process to a maximum degree. Here, scaling and porting is
Chapter 2. VLSI DESIGN STYLES 49

more demanding, and has to be performed either manually or using CAD tools .Also, these rules
tend to be more complex especially for deep submicron. The fundamental unity in the definition
of a set of design rules is the minimum line width .It stands for the minimum mask dimension that
can be safely transferred to the semiconductor material .Even for the same minimum dimension,
design rules tend to differ from company to company, and from process to process. Now, CAD
tools allow designs to migrate between compatible processes.

2.11 LAMBDA BASED DESIGN RULES

• Lambda-based (scalable CMOS) design rules define scalable rules based on λ x(which is half of
the minimum channel length)
• classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON
Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and
layout.Circuit designer in general want tighter, smaller layouts for improved performance and de-
creased silicon area.On the other hand, the process engineer wants design rules that result in a
controllable and reproducible process.Generally we find there has to be a compromise for a com-
petitive circuit to be produced at a reasonable cost. All widths, spacing, and distances are written
in the form λ x = 0.5 X minimum drawn transistor length.Design rules based on single parameter,
λx
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2λ x.
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted
Chapter 2. VLSI DESIGN STYLES 50

F IGURE 2.14: LAMBDA BASED DESIGN RULES

F IGURE 2.15: Layout1

2.12 CONTACT CUTS

When making contacts between poly-silicon and diffusion in nMOS circuits it should be remem-
bered that there are three possible approaches–poly. to metal then metal to diff., or aburied contact
poly. to diff. , or a butting contact (poly. to diff. using metal). Among the three the latter two,
the buried contact is the most widely used, because of advantage in space and a reliable contact.
At one time butting contacts were widely used , but now a days they are superseded by buried
contacts. In CMOS designs, poly. to diff. contacts are always made via metal. A simple process
is followed for making connections between metal and either of the other two layers (as in Fig.a),
Chapter 2. VLSI DESIGN STYLES 51

F IGURE 2.16: Layout 2

F IGURE 2.17: MOS Layout

F IGURE 2.18: Layout 3

The 2λ x 2λ . contact cut indicates an area in which the oxide is to be removed down to the under-
lying polysilicon or diffusion surface. When deposition of the metal layer takes place the metal is
deposited through the contact cut areas onto the underlying area so that contact is made between
the layers. The process is more complex for connecting diffusion to poly-silicon using the butting
contact approach (Fig.b), In effect, a 2λ x 2λ contact cut is made down to each of the layers to be
Chapter 2. VLSI DESIGN STYLES 52

F IGURE 2.19: Layout 4

joined. The layers are butted together in such a way that these two contact cuts become contigu-
ous. Since the poly-silicon and diffusion outlines overlap and thin oxide under poly silicon acts as
a mask in the diffusion process, the poly-silicon and diffusion layers are also butted together. The
contact between the two butting layers is then made by a metal overlay as shown in the Fig.

F IGURE 2.20: nMOS CMOS Contacts

Chapter 2. VLSI DESIGN STYLES 53

F IGURE 2.21: contact to polysilicon diffusion

2.13 Other design rules

• Double Metal MOS process Rules

• CMOS fabrication is much more complex than nMOS fabrication
• 2 um Double metal, Double poly. CMOS/BiCMOS Rules
• 1.2um Double Metal single poly.CMOS rules

2.14 CMOS λ x-based Design Rules

: The CMOS fabrication process is more complex than nMOS fabrication. In a CMOS process,
there are nearly 100 actual set of industrial design rules. The additional rules are concerned with
those features unique to p-well CMOS, such as the p-well and p+ mask and the special ’substrate
Chapter 2. VLSI DESIGN STYLES 54

contacts. The p-well rules are shown in the diagram below

F IGURE 2.22: pwell rules

In the diagram above each of the arrangements can be merged into single split contacts.

F IGURE 2.23: fig1

From the above diagram it is also clear that split contacts may also be made with separate cuts.

The CMOS rules are designed based on the extensions of the Mead and Conway concepts and also
by excluding the butting and buried contacts the new rules for CMOS design are formed. These
rules for CMOS design are implemented in the above diagrams.
Chapter 2. VLSI DESIGN STYLES 55

2.15 µm CMOS Design rules

:
Chapter 2. VLSI DESIGN STYLES 56

2.16 2µm CMOS Design rules

F IGURE 2.24: 2µm design rules

Chapter 2. VLSI DESIGN STYLES 57

2.17 Scaling of MOS circuits:

1. What is Scaling? Proportional adjustment of the dimensions of an electronic device while

maintaining the electrical properties of the device, results in a device either larger or smallerthan
the un-scaled device. Then Which way do we scale the devices for VLSI? BIG and SLOW . . . or
SMALLand FAST? What do we gain? 2. Why Scaling? Scale the devices and wires down, Make
Chapter 2. VLSI DESIGN STYLES 58

the chips ‘fatter’ – functionality, intelligence, memory – and – faster, Make more chips per wafer
– increased yield, Make the end user Happy by giving more for less and therefore, make MORE
MONEY!! 3. FoM for Scaling Impact of scaling is characterized in terms of several indicators:
Minimum feature size Number of gates on one chip Power dissipation Maximum operational fre-
quency Die size Production cost Many of the FoMs can be improved by shrinking the dimensions
of transistors and interconnections. Shrinking the separation between features – transistors and
wires Adjusting doping levels and supply voltages. Technology Scaling : Goals of scaling the
dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double
transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in
frequency) Die size used to increase by 14% per generation Technology generation spans 2-3 years
Figure1 to Figure 5 illustrates the technology scaling in terms of minimum feature size, transis-
tor count, prapogation delay, power dissipation and density and technology generations. Scaling
Models: Full Scaling (Constant Electrical Field)

• Ideal model – dimensions and voltage scale together by the same scale factor Fixed Voltage
Scaling

• Most common model until recently – only the dimensions scale, voltages remain constant
General Scaling

• Most realistic for today’s situation – voltages and dimensions scale with different factors

Scaling Factors for Device Parameters Device scaling modeled in terms of generic scaling
factors:1/α and 1/β . • 1/β : scaling factor for supply voltage VDD , and gate oxide thickness
Chapter 2. VLSI DESIGN STYLES 59

D • 1/α: linear dimensions both horizontal and vertical dimensions Why is the scaling factor for
gate oxide thickness different from other linear horizontal and vertical dimensions?
Consider the cross section of the device as in Figure 6,various parameters derived are as follows.

F IGURE 2.25: scaling of MOS transistor

Implications of Scaling : Improved Performance Improved Cost Interconnect Woes Power Woes
Productivity Challenges Physical Limits
Physical Limits : .Will Moore’s Law run out of steam? Can’t build transistors smaller than an
atom. . . .Many reasons have been predicted for end of scaling

• Dynamic power

• Sub-threshold leakage

• tunneling

• Short channel effects

• Fabrication costs

• Electro-migration

• Interconnect delay

Limitations of Scaling Effects, as a result of scaling down- which eventually become severe
enough to prevent further miniaturization.

• Substrate doping

• Depletion width
Chapter 2. VLSI DESIGN STYLES 60

• Limits of miniaturization

• Limits of interconnect and contact resistance

• Limits due to sub threshold currents

• Limits on logic levels and supply voltage due to noise

• Limits due to current density.

Chapter 2. VLSI DESIGN STYLES 61

F IGURE 2.26: scaling of MOS electrical parameters1

Chapter 2. VLSI DESIGN STYLES 62

F IGURE 2.27: scaling of MOS electrical parameters2

Chapter 2. VLSI DESIGN STYLES 63

F IGURE 2.28: scaling of MOS electrical parameters

Chapter 3

BASIC CIRCUIT CONCEPTS AND

GATE LEVEL DESIGN

Course Outcomes
After successful completion of this module, students should be able to:
CO 6 Compare static and dynamic CMOS logic circuits in terms of power Analyze
consumption and speed of operation.

3.1 BASIC CIRCUIT CONCEPTS

In VLSI design the wiring up (interconnection) of circuits takes place through the various conduc-
tive layers which are produced by the MOS processing. So, it is necessary to know the resistive
and capacitive characteristics of each layer. Concepts such as
.Resistance RS and a standard unit of capacitance cg which helps in evaluating the effects of wiring
and input and output capacitances.
.The delays associated with wiring with inverters and with other circuitry evaluated interms of a
delay unit .

64
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 65

3.1.1 Sheet Resistance RS

The sheet resistance is a measure of resistance of thin films that have a uniform thickness.
It is commonly used to characterize materials made by semiconductor doping, metal deposition,
resistive paste printing and glass coating. Ex: doped semiconductor regions (silicon or polysilicon)
and resistors.
Sheet resistance is applicable to two-dimensional systems where the thin film is considered to be
a two- dimensional entity.

Consider a uniform slab of conducting material of resistivity of width W, thickness t and length
between faces A& B is L. as shown in figure.

F IGURE 3.1: conducting material

Consider the resistance RAB betweentwoopposite f aces

From the below equation RS isindependento f theareao f square., f orexamplea1mpersidesquareslabo f thematerialh

T hethicknesso f themetaland polysilicondepositedisknownbymeasuringusing f ourprobemethod.
T heresistivityo f thedi f f usionlayersismeasuredbymeasuringthepenetrationdeptho f thedi f f usionregions.

3.2 Sheet resistance concept applied to MOS Transistors and Invert-

erts:

Consider the transistor structures by distinguish the actual diffusion (active) regions from the chan-
nel regions. The simple n-type pass transistor has a channel length L = 2λ andachannelwidthW =
2λ .Hencethechannelissquareandthechannelresistanceis
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 66

Here the length to width ratio denotes the impedance (Z) and is equal to 1:1. Consider another
transistor has a channel length L = 8λ andwidthW = 2λ .

Typical sheet resistances of MOS layers are tabulated

3.3 Sheet resistance for Inverters

Consider an nMOS inverter has the channel length 8λ andwidth2λ f orpulluptransistorasshownin f igure.
L = 8λ ;W = 2λ
Z = L/W = 4
SheetresistanceR = Z.RS = 4X104 = 40KW
Forpulldowntransistorthechannellength2λ andwidth2λ ,thenthesheetresistanceisR = Z.RS = 1X104 =
10KW
HenceZ p.utoZ p.d = 4 : 1hencetheONresistancebetweenVD DandVS Sisthetotalseriesresistancei.e.,
RON = 40KW + 10KW = 50KW
ConsiderthesimpleCMOSinverter.Herethepulluptransistoriso f p−typedevicewithchannellength2λ andwidth2λ .
L/W = 1
T henSheetresistanceRS P = Z.RS = 1X2.5X104 = 25KW
T hepulldowntransistoriso f n − typewithchannellength2λ andwidth2λ .
Z = L/W = 1
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 67

Hence, SheetresistanceRS N = Z.RS = 1X104 = 10KW.

Inthiscase,thereisnostaticresistancebetweenVD DandVS S.Sinceatanypointo f timeonlyonetransistorisON, butnotbo
W henVin = 1,theONresistanceis10KW
Vin = 0,theONresistanceis25KW

3.4 Area capacitance of layers

From the concept of the transistors, it is apparent that as gate is separated from the channel by gate
oxide an insulating layer, it has capacitance. Similarly different interconnects run on the chip and
each layer is separated by silicon dioxide . For any layer by knowing the dielectric thickness, we
can calculate the area capacitance as follows

Where, A is area of the plates , D is the thickness of Sio2, 0 isthepermittivityo f the f reespaceandi nsistherelativeperm

3.5 Standard unit of capacitance □cg

It is defined as the gate – to – channel capacitance of a MOS transistor having W = L . i.e., standard
square as shown in figure. The unit is denoted by □ cg.
□cgmaybecalculated f oranyMOSprocessas f ollows
For5mMOScircuits

Area/standard square = 5µmX5µm = 25µm2

Capacitancevalue = 4X10− 4pF/µm2
T hus, standardvalue□ cg = 25 µm2 X4X10− 4pF/µm2 = 0.01pF
For2µmMOScircuits
Area/standardsquare = 2µmX2µm = 4µm2
Capacitancevalue = 8X10 − 4pF/µm2
T hus, standardvalue□cg = 4µm2 X8X10− 4pF/µm2 = 0.01pF
For1.2µmMOScircuits
Area/standardsquare = 1.2µmX1.2µm = 1.44µm2
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 68

Capacitancevalue = 16X10− 4pF/µm2

T hus, standardvalue□cg = 1.44pF/µm2 X16X10− 4pF/pF/µm2 = 0.0023pF.

3.6 Calculation for capacitance value

The calculation of capacitance value is established by the ration between the area of interest and
the area of standard gate and multiplying this ration by the appropriate relative C value from tabular
form. The product will give the required capacitance in □cgunits.

Consider the area defined as shown in figure of length 20λ and width 3λ

Area relative to the standard gate

1) consider the area in metal 1 capacitance to substrate = relative area X relative C value (from
table)

= 15 X 0.075 □cg

= 1.125 □cg

2) consider the same area in polysilicon capacitance to substrate = 15 X 0.1 □cg

= 1.5□cg

3) consider the same area in n- type diffusion capacitance to substrate = 15 X 0.25 □cg
= 3.75□cg

Consider the following structure which occupies more than one layer as shown in figure and cal-
culate the area capacitance value
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 69

While calculating the area value in the above figure neglect the contact region where the metal is
connected to polysilicon and shielded from the substrate.

( i)consider the metal area

Similarly the transition point of an inverter or gate is 0.5 VD Dwhichisapproximatelyequalto0.63VD D(timeconstant)

0.3nsec.

for 2µmMOStechnologyτ = 0.2nsec.

for 1.2µmMOStechnologyτ = 0.1nsec.

3.7 INVERTER DELAYS

Consider the basic nMOS inverter has the channel length 8λ and width 2λ for pull-up transistor
and channel length of 2λ and width 2λ for pull down transistor.
Hence the sheet resistance for pull-up transistor is R p .u = 4RS = 40k
andsheetresistance f orpull − uptransistorisR p .d = 1RS = 10k.
Since(τ = RC)dependsuponthevalueso f R&C,thedelayassociateswiththeinverterdependuponwhetheritisbeingtur
Now, considerapairo f cascadedinvertersasshownin f igure,thenthedelayoverthepairwillbeconstantirrespectiveo f
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 70

Ingeneral,thedelaythroughapairo f similarnMOSinvertersis
Td = (1 + Z p .u/Z p.d)τ

Assume that τ = 0.3nsec.

Then ,Td = (1 + 4)0.3

= 5 τT hus,theinverterpairdelay f orinvertershaving4 : 1rationis5τ.

Hence, a single 4:1 inverter exhibits undesirable asymmetric delays, Since the delay in turning ON
is τanddelayinturningOFFis4τ.

3.8 CMOS inverter pair delay

When we consider CMOS inverters, the rules for nMOS inverters are not applicable. But we need
to consider the natural (RS )unevenvalues f orequalsizepullupp−transistorandthen−typepulldowntransistors.

Figure shows the theoretical delay associated with a pair of both n and p transistors lambda based
inverters. Here the gate capacitance is double comparable to nMOS inverter since the input to
a CMOS inverter is connected to both transistor gate. NOTE: Here the asymmetry (uneven) of
resistance. values can be eliminated by increasing the width of the p-device channel by a factor of
two or three at the same time the gate capacitance of p-transistor also increased by the same factor.

3.9 Formal estimation of CMOS inverter delay

In CMOS inverter by the charging and discharging of a capacitive load CL , wecanestimatetheRisetimeand f alltime f
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 71

In this analysis we assume that the p-device stays in saturation for the entire charging period of the
load capacitor CL .Considerthecircuitas f ollows

Saturation current for the p-transistor is given by

Assume that t = τwhenVo ut = VD Dthen

Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 72

3.10 Fall time estimation

Consider the circuit for discharge of CLthroughn − transistoras f ollows

So that the rise time is slower by a factor of 2.5 when using minimum size devices for both n & p.

In order to achieve symmetrical operation using minimum channel length we need to make W p =
2.5Wn .

For minimum size lambda based geometries this would result in the inverter having an input ca-
pacitance of
1□cg(n − device) + 2.5□cg (p − device) = 3.5□cg
Fromtheaboveequationswecanconcludethat
1.τr andτ f areproportionalto1/VD D
2.τr andτ f areproportionaltoCL
3.τr = 2.5τ f f orequalnand p − transistorgeometries.DrivingLargecapacitiveloads

when signals are propagated from the chip to off chip destinations we can face problems to drive
large capacitive loads. Generally off chip capacitances may be several orders higher than on chip
cg values. CL 104 □cgW hereCL denoteso f f chipload.T hecapacitanceswhicho f thisordermustbedriventhroughlowr

3.11 Cascaded Inverters as drivers

Inverters to drive large capacitive loads must be present low pull-up and pull down resistance. For
MOS circuits low resistance values imply low L:W ratio.Since length L cannot be reduced below
the minimum feature size, the channels must be made very wide to reduce resistance value.
Consider N cascaded inverters as on increasing the width factor of ‘f’ than the previous stage as
shown in
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 73

As the width factor increases, the capacitive load presented at the inverter input increases and the
area occupied increases also. It is observed that as the width increases, the number N of stages are
decreased to drive a particular value of CL .T huswithlarge f (width), Ndecreasesbutdelayperstageincreases f or4 :
1nMOSinverters.

Delay per stage = fτ f orVi n = 4 f τ f orVi n

Where Vi nindicateslogic0to1transitionand −Vi nindicateslogic1to0transitiono fVi nToaldelaypernMOSpair =

4 f τ.SimilarlydelayperCMOSpair = 7 f τ.

Calculation for time delay Let us assume y = CL/□cg = f NDeterminethevalueo f f whichwillminimizetheoveralldel

Apply logarithms on both sides in the above equation

ln(y) = ln(f N)
ln (y) = N ln (f)

N= ln(y)/ln(f)

For N even,Total delay = N/2 5fτ = 2.5N f τ(nMOS)

(Or) toal delay = N/2 x 7fτ = 3.5N f τ(CMOS)

From above relations, we can write

Delay Nfτ = ln(y)/ln( f ). f τ

It can be shown that total delay is minimized if f assumes the value of e for both CMOS and nMOS
inverters. Assume f = e , N = ln(y)/ln(e)

N = ln(y)

Overall delay td Neventd = 2.5eNτ(nMOS)

(or) td = 3.5eNτ(CMOS)

N odd td = [2.5(N − 1) + 1]eτ(nMOS)

Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 74

td = [3.5(N − 1) + 2]eτ(CMOS)( f orlogicaltransition0to1)(or)td = [2.5(N − 1) + 4]eτ(nMOS)

td = [3.5(N − 1) + 5]eτ(CMOS)( f orlogicaltransition1to0)

3.12 Super buffers

Generally the pull-up and the pull down transistors are not equally capable to drive capacitive
loads. This asymmetry is avoided in super buffers. Basically, a super buffer is a symmetric invert-
ing or non inverting driver that can supply (or) remove large currents and is nearly symmetrical
in its ability to drive capacitive load. It can switch large capacitive loads than an inverter. An
inverting type nMOS super buffer as shown in figure.

Consider a positive going (0 to 1) transition at input Vin turns ON the inverter formed by T1 and
T2.
With a small delay, the gate of T3 is pulled down to 0 volts. Thus, device T3 is cut off. Since gate
of T4 is connected to Vin, it is turned ON and the output is pulled down very fast.

For the opposite transition of Vin (1 to 0), Vin drops to 0 volts. The gate of transistor T3 is allowed
to rise to VDD quickly.
Simultaneously the low Vin turns off T4 very fast. This makes T3 to conduct with its gate voltage
approximately equal to VDD.
This gate voltage is twice the average voltage that would appear if the gate was connected to the
source as in the conventional nMOS inverter.
Now as Ids Vg s, doublingthee f f ectiveVg sincreasesthecurrentandtherebyreducesthedelayinchargingattheloadcap

Figure shows the non-inverting nMOS super buffer where the structures fabricated in 5µmtechnologyarecapableo f
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 75

3.13 BiCMOS drivers

1. In BiCMOS technology we use bipolar transistor drivers as the output stage of inverter and
logic gate circuits.
2. In bipolar transistors, there is an exponential dependence of the collector (output) current on the
base to emitter (input) voltage Vbe .
3. Hence, the bipolar transistors can be operated with much smaller input voltage swings than
MOS transistors and still switch large current.
4. Another consideration in bipolar devices is that the temperature effect on input voltage Vbe.
5. In bipolar transistor, Vbe is logarithmically dependent on collector current IC and also other
parameters such as base width, doping level, electron mobility.
6. Now, the temperature differences across an IC are not very high. Thus the Vbe values of the
bipolar devices spread over the chip remain same and do not differ by more than a few milli volts.

The switching performance of a bipolar transistor driving a capacitive load can be analyzed to
begin with the help of equivalent circuit as shown in figure.

The time t required to change the output voltage Vo utbyanamountequaltotheinputvoltageis

t = CL /gmW here,CL istheloadcapacitance

gm isthetransconductanceo f thebipolartransistor.

The value of ∆tissmallbecausethetransconductanceo f thebipolartransistorsisrelativelyhigh.T herearetwomaincom

Ti nisthetimerequiredto f irstchargethebaseemitter junctiono f thebipolar(npn)transistor.
T histimeistypically2ns f ortheBiCMOStransistorbasedriver.
FortheCMOSdriverthetimerequiredtochargetheinputgatecapacitanceis1ns.
TL isthetimerequiredtochargetheout putloadcapacitance.
T hecombinede f f ecto f Ti nandTL isrepresentedasshownin f igure.

In Bipolar transistors while considering delay another significant parameter is collector resistance
Rcthroughwhichthechargingcurrent f orCL f lows.
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 76

Forahighvalueo f RC,thereisalongpropagationdelaythroughthetransistorwhenchargingacapacitiveload.
Figureshowsthetypicaldelayvaluesattwovalueso fCL as f ollows.

The devices thus have high , high gm, high h f eandlowRC .T hepresenceo f suche f f icientandadvantageousdeviceson

3.14 Propagation delays

Propagation delay is the delay in the propagation of the signal created by the change of logical sta-
tus at the input to create same change at the output. subsection{(i)Cascaded pass transistors Figure
shows a chain of four pass transistors driving a capacitive load CL .AllthegatesaresuppliedbyVD Dsothatasignalcanp
to−channelcapacitanceandstraycapacitances.T hemminimumvalueo f RistheturnedONresistanceo f eachenhance

The current through the capacitance at the node with voltage V2 isC(dV 2/dt)C.V 2/t
T hecurrententeringatthisnodeisI1 = (V 1–V 2)/R
andthecurrentleaving f romthisnodeisI2 = (V 2–V 3)/R.
ByapplyingKCLatthisnodeIC = I1–I2

C . V2/ t = I1 – I2 = ((V1 – V2)- (V2 – V3)) / R

As the number of sections in the network increases, the circuit parameters become distributed. As-
sume that R and C as the resistance per unit length and the capacitance per unit length respectively.
C* .V2/ t = (V2)/R.X
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 77

Where x is the distance along the network from the input. RC dv/dt = d/dx. (dv/dx) = d2V /dx2
T hepropagationtimeτ p f romasignaltopropagateadistancexisτ p proptoX 2
Bysimpli f yingtheanalysisi f allsheetresistance, gate − to − channelcapacitanceRSand□cgare

lumped together

R total = nr Rs
Ctotal = nc□cg

Where r gives relative resistance per section interms of RS andcgivesrelativecapacitancepersectionintermso f cg.T h

n2 ∗ rc(τ)
ItcanbeshownthatthesignaldelayinasectioncontainingNidentical passtransistorsdrivingamatchedload(CL =
Cg)isτ p = 0.7∗N(N +1)/2∗RCL Forlargevalueo f N,thequantity(N +1)canbereplacedbyN.Sincethedelayincrease

3.15 Design of long polysilicon wires

Long polysilicon wires also contribute distributed series R and C as was the case for cascaded pass
transistors and inconsequence signal propagation is slowed down. This would also be the case
for wires in diffusion where the value of C may be quite high, and for this reason the designer is
discouraged from running signals in diffusion except over very short distances.

For long polysilicon runs, the use of buffers is recommended. In general, the use of buffers to
drive long polysilicon runs has two desirable effects. First, the signal propagation is speeded up
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 78

and second there is a reduction in sensitivity to noise. In the diagram the slow rise-time of the
signal at the input of the inverter means that the input voltage spends a relatively long time in the
vicinity of Vinv so that small disturbances due to noise will switch the inverter state between ‘0’
and’1’ as shown at the output point.
Thus , it is essential that long polysilicon wires be driven by suitable buffers to guard against the
effects of noise and to speed up the rise-time of propagated signal edges.

3.16 Wiring capacitances

The significant sources of capacitance which contribute to the overall wiring capacitance are as
follows

3.16.1 (i) Fringing fields

Capacitance due to fringing field effects can be a major component of the overall capacitance of in-
terconnect wires. For fine line metallization, the value of fringing field capacitance (C f f )canbeo f thesameorderasth

Where l = wire length

t = thickness of wire

d = wire to substrate separation.

Then, total wire capacitance

Cw = Carea + Cff
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 79

3.16.2 (ii) Interlayer capacitances

From the definition of capacitance itself, it can be said that there exists a capacitance between
the layers due to parallel plate effects. This capacitance will depend upon the layout i.e., where
the layers cross or whether one layer underlies another etc., by the knowledge of these capaci-
tances, the accuracy of circuit modeling and delay calculations will be improved. It can be readily
calculated for regular structures.

3.16.3 (iii)peripheral capacitance

1. The source and drain p-diffusion regions forms junctions with the n-substrate (or n-well) at well
defined and uniform depths.
2. Similarly, the source and drain n-diffusion regions forms junctions with p-substrate (or p-well)
at well defined and uniform depths.
3. Hence, for diffusion regions, each diode thus formed has associated a peripheral (side wall)
capacitance with it.
4. As a whole the peripheral capacitance,Cp will be the order of pF/unit length. So its value will
be greater than Carea of the diffusion region to substrate. Cp increases with reduction in source or
drain area. Total diffusion capacitance is

Cd i f f = Ca rea +Cp

However, as the n and p-active regions are formed by impure implants at the surface of the silicon
incase of orbit processes, they have negligible depth. Hence Cp is quite negligible in them. Typical
values are given in tabular form
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 80

3.17 Fan – in and Fan-out

Fan-in: The number of inputs to a gate is called as fan - in.

Fan-out: The maximum number of similar gates that a gate can drive while remaining within the
guaranteed specifications is called as fan-out.

textbfEffects of Fan-in and Fan-out on propagation delay:

An additional input to a CMOS logic gate requires an additional nMOS and pMOS i.e., two addi-
tional transistors, while incase of other MOS logic gates, it requires one additional transistor.
In CMOS logic gates, due to these additional transistors, not only the chip area but also the total
effective capacitance per gate also increased and hence propagation delay increases.
Some of the increase in propagation delay time can be compensated by the size-scaling method.

By increasing the size of the device, its current driving capability can be preserved.
Due to increase in both of inputs and devices size, the capacitance increases, Hence propagation
delay will still increase with fan-in.

An increase in the number of outputs of a logic gate directly adds to its load capacitances. Hence,
the propagation delay increases with fan-out.

3.18 Choice of layers

The following are the constraints which must be considered for the proper choice of layers.
1. Since the polysilicon layer has relatively high specific resistance (RS ), itshouldnotbeused f orroutingVD DandVS S(
2.VD DandGND(VS S)mustbedistributedonlyonmetallayers, duetotheconsiderationo f Rsvalue.
3.T hecapacitivee f f ectswillalso
imposecertainrestrictionsinthechoiceo f layersas f ollows

(i) where fast signal lines are required, and in relation to signals on wiring which has relatively
higher values of RS.
(ii) The diffusion areas have higher values of capacitance to substrate and are harder to drive.

4. Over small equipotential regions, the signal on a wire can be treated as being identical at all
points.
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 81

5. Within each region the propagation delay of the signal will comparably smaller than the gate
delays and signal delays caused in a system connected by wires.
Thus the wires in a MOS system can be modeled as simple capacitors. This concept leads to the
establishment of electrical rules (guidelines) for communication paths(wires) as given in tabular
form.

3.19 Complex gates

3.19.1 CMOS Logic Gates

The inverter and NAND gates are examples of static CMOS logic gates, also called complemen-
tary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to connect
the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD), as shown in
Figure . The networks are arranged such that one is ON and the other OFF for any input pattern
The pull-up and pull-down networks in the inverter each consist of a single transistor. The NAND
gate uses a series pull-down network and a parallel pullup network. More elaborate networks are
used for more complex gates. Two or more transistors in series are ON only if all of the series
transistors are ON. Two or more transistors in parallel are ON if any of the parallel transistors are
ON. This is illustrated in Figure for nMOS and pMOS transistor pairs. By using combinations of
these constructions, CMOS combinational gates can be constructed. In general, when we join a
pull-up network to a pull-down network to form a logic gate as shown in Figure , they both will
attempt to exert a logic level at the output. The possible levels at the output are shown in Table .
From this table it can be seen that the output of a CMOS logic gate can be in four states.
The 1 and 0 levels have been encountered with the inverter and NAND gates, where either the
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 82

pull-up or pull-down is OFF and the other structure is ON. When both pull-up and pull-down are
OFF, the highimpedance or floating Z output state results. This is of importance in multiplexers,
memory elements, and tristate bus drivers. The crowbarred (or contention) X level exists when
both pull-up and pull-down are simultaneously turned ON. Contention between the two networks
results in an indeterminate output level and dissipates static power. It is usually an unwanted con-
dition

F IGURE 3.2: General logic gate using pull-up and pull-down networks

The NOR Gate A 2-input NOR gate is shown in Figure . The nMOS transistors are in parallel
to pull the output low when either input is high. The pMOS transistors are in series to pull the
output high when both inputs are low, as indicated in Table . The output is never crowbarred or
left floating.

Example Sketch a 3-input CMOS NOR gate. SOLUTION: Figure shows such a gate. If any input
is high, the output is pulled low through the parallel nMOS transistors. If all inputs are low, the
output is pulled high through the series pMOS transistors

Complex Gates A compound gate performing a more complex logic function in a single stage of
logic is formed by using a combination of series and parallel switch structures. For example, the
derivation of the circuit for the function Y (A · B) (C · D) is shown in Figure . This function
is sometimes called AND-OR-INVERT-22, or AOI22 because it performs the NOR of a pair of
2-input ANDs. For the nMOS pull-down network, take the uninverted expression ((A · B) (C · D))
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 83

F IGURE 3.3: 2-input NOR

indicating when the output should be pulled to ‘0.’ The AND expressions (A · B) and (C · D) may
be implemented by series connections of switches, as shown in Figure . Now ORing the result
requires the parallel connection of these two structures, which is shown in Figure . For the pMOS
pull-up network, we must compute the complementary expression using switches that turn on with
inverted polarity. By DeMorgan’s Law, this is equivalent to interchanging AND and OR opera-
tions. Hence, transistors that appear in series in the pull-down network must appear in parallel in
the pull-up network. Transistors that appear in parallel in the pulldown network must appear in se-
ries in the pull-up network. This principle is called conduction complements and has already been
used in the design of the NAND and NOR gates. In the pull-up network, the parallel combination
of A and B is placed in series with the parallel combination of C and D. This progression is ev-
ident in Figure and Figure 4.4(d). Putting the networks together yields the full schematic (Figure ).

Example Sketch a static CMOS gate computing Y (A B C) · D. SOLUTION: Below figure shows
such an OR-AND-INVERT-3-1 (OAI31) gate. The nMOS pull-down network pulls the output low
if D is 1 and either A or B or C are 1, so D is in series with the parallel combination of A, B, and
C. The pMOS pull-up network is the conduction complement, so D must be in parallel with the
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 84

F IGURE 3.4: input NOR

series combination of A, B, and C.

3.19.2 Complex Gates

A compound gate performing a more complex logic function in a single stage of logic is formed
by using a combination of series and parallel switch structures. For example, the derivation of the
circuit for the function Y (A · B) (C · D) is shown in Figure . This function is sometimes called
AND-OR-INVERT-22, or AOI22 because it performs the NOR of a pair of 2-input ANDs. For the
nMOS pull-down network, take the uninverted expression ((A · B) (C · D)) indicating when the
output should be pulled to ‘0.’ The AND expressions (A · B) and (C · D) may be implemented by
series connections of switches, as shown in Figure . Now ORing the result requires the parallel
connection of these two structures, which is shown in Figure . For the pMOS pull-up network, we
must compute the complementary expression using switches that turn on with inverted polarity. By
DeMorgan’s Law, this is equivalent to interchanging AND and OR operations. Hence, transistors
that appear in series in the pull-down network must appear in parallel in the pull-up network.
Transistors that appear in parallel in the pulldown network must appear in series in the pull-up
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 85

F IGURE 3.5: CMOS

network. This principle is called conduction complements and has already been used in the design
of the NAND and NOR gates. In the pull-up network, the parallel combination of A and B is
placed in series with the parallel combination of C and D. This progression is evident in Figure
and Figure 4.4(d). Putting the networks together yields the full schematic (Figure ). The symbol
is shown in Figure
.

Example : Sketch a static CMOS gate computing Y (A B C) · D. SOLUTION: Below figure shows
such an OR-AND-INVERT-3-1 (OAI31) gate. The nMOS pull-down network pulls the output low
if D is 1 and either A or B or C are 1, so D is in series with the parallel combination of A, B, and
C. The pMOS pull-up network is the conduction complement, so D must be in parallel with the
series combination of A, B, and C.
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 86

F IGURE 3.6: CMOS compound gate for function Y (A B C) ·

3.19.3 Pass Transistors and Transmission Gates

The strength of a signal is measured by how closely it approximates an ideal voltage source. In
general, the stronger a signal, the more current it can source or sink. The power supplies, or rails,
(VDD and GND) are the source of the strongest 1s and 0s. An nMOS transistor is an almost per-
fect switch when passing a 0 and thus we say it passes a strong 0. However, the nMOS transistor
is imperfect at passing a 1. The high voltage level is somewhat less than VDD. We say it passes
a degraded or weak 1. A pMOS transistor again has the opposite behavior, passing strong 1s but
degraded 0s. The transistor symbols and behaviors are summarized in Figure with g, s, and d
indicating gate, source, and drain. When an nMOS or pMOS is used alone as an imperfect switch,
we sometimes call it a pass transistor. By combining an nMOS and a pMOS transistor in parallel,
we obtain a switch that turns on when a 1 is applied to g in which 0s and 1s are both passed in an
acceptable fashion. We term this a transmission gate or pass gate. In a circuit where only a 0 or a
1 has to be passed, the appropriate transistor (n or p) can be deleted, reverting to a single nMOS
or pMOS device.
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 87

F IGURE 3.7: CMOS compound gate for function Y (A · B) (C · D)

Note that both the control input and its complement are required by the transmission gate. This is
called double rail logic. Some circuit symbols for the transmission gate are shown in Figure. None
are easier to draw than the simple schematic, so we will use the schematic version to represent a
transmission gate.

3.19.4 Dynamic CMOS design

Dynamic Circuits Ratioed circuits reduce the input capacitance by replacing the pMOS transis-
tors connected to the inputs with a single resistive pullup. The drawbacks of ratioed circuits
include slow rising transitions, contention on the falling transitions, static power dissipation, and a
nonzero VOL. Dynamic circuits circumvent these drawbacks by using a clocked pullup transistor
rather than a pMOS that is always ON. Figure compares (a) static CMOS, (b) pseudo-nMOS, and
(c) dynamic inverters. Dynamic circuit operation is divided into two modes, as shown in Figure.
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 88

F IGURE 3.8: CMOS compound gate for function Y (A · B) (C · D)

During precharge, the clock is 0, so the clocked pMOS is ON and initializes the output Y high.
During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output may remain high or
may be discharged low through the pulldown network. Dynamic circuits are the fastest commonly
used circuit family because they have lower input capacitance and no contention during switching.
They also have zero static power dissipation. However, they require careful clocking, consume
significant dynamic power, and are sensitive to noise during evaluation.. In Figure , if the input
A is 1 during precharge, contention will take place because both the pMOS and nMOS transis-
tors will be ON. When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid contention as shown
in Figure . The extra transistor is sometimes called a foot. Figure 9.24 shows generic footed and
unfooted gates. Figure estimates the falling logical effort of both footed and unfooted dynamic
gates. As usual, the pulldown transistors’ widths are chosen to give unit resistance. Precharge
occurs while the gate is idle and often may take place more slowly. Therefore, the precharge
transistor width is chosen for twice unit resistance. This reduces the capacitive load on the clock
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 89

F IGURE 3.9: Pass transistor strong and degraded outputs

and the parasitic capacitance at the expense of greater rising delays. We see that the logical ef-
forts are very low. Footed gates have higher logical effort than their unfooted counterparts but are
still an improvement over static logic. In practice, the logical effort of footed gates is better than
predicted because velocity saturation means series nMOS transistors have less resistance than we
have estimated. Moreover, logical efforts are also slightly better than predicted because there is
no contention between nMOS and pMOS transistors during the input transition. The size of the
foot can be increased relative to the other nMOS transistors to reduce logical effort of the other
inputs at the expense of greater clock loading. Like pseudo-nMOS gates, dynamic gates are partic-
ularly well suited to wide NOR functions or multiplexers because the logical effort is independent
of the number of inputs. Of course, the parasitic delay does increase with the number of inputs
because there is more diffusion capacitance on the output node. Characterizing the logical effort
and parasitic delay of dynamic gates is tricky because the output tends to fall much faster than the
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 90

F IGURE 3.10: Transmission gate

input rises, leading to potentially misleading dependence of propagation delay on fanout [Suther-
land99]. A fundamental difficulty with dynamic circuits is the monotonicity requirement. While
a dynamic gate is in evaluation, the inputs must be monotonically rising. That is, the input can
start LOW and remain LOW, start LOW and rise HIGH, start HIGH and remain HIGH, but not
start HIGH and fall LOW. Figure shows waveforms for a footed dynamic inverter in which the
input violates monotonicity. During precharge, the output is pulled HIGH. When the clock rises,
the input is HIGH so the output is discharged LOW through the pulldown network, as you would
want to have happen in an inverter. The input later falls LOW, turning off the pulldown network.
However, the precharge transistor is also OFF so the output floats, staying LOW rather than rising
as it would in a normal inverter. The output will remain low until the next precharge step. In sum-
mary, the inputs must be monotonically rising for the dynamic gate to compute the correct function
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 91

F IGURE 3.11: foot dynamic invertar

F IGURE 3.12: generalized footed and unfooted dynamic gates

Domino Logic The monotonicity problem can be solved by placing a static CMOS inverter be-
tween dynamic gates, as shown in Figure . This converts the monotonically falling output into a
monotonically rising signal suitable for the next gate, as shown in Figure . The dynamic-static pair
together is called a domino gate [Krambeck82] because precharge resembles setting up a chain
of dominos and evaluation causes the gates to fire like dominos tipping over, each triggering the
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 92

F IGURE 3.13: incorrect connection of dynamic gates

next. A single clock can be used to precharge and evaluate all the logic gates within the chain. The
dynamic output is monotonically falling during evaluation, so the static inverter output is mono-
tonically rising. Therefore, the static inverter is usually a HI-skew gate to favor this rising output.
Observe that precharge occurs in parallel, but evaluation occurs sequentially. This explains why
precharge is usually less critical. The symbols for the dynamic NAND, HI-skew inverter, and
domino AND are shown in Figure 9.28(c). In general, more complex inverting static CMOS
gates such as NANDs or NORs can be used in place of the inverter [Sutherland99]. This mixture
of dynamic and static logic is called compound domino. For example, Figure shows an 8-input
domino multiplexer built from two 4-input dynamic multiplexers and a HI-skew NAND gate. This
is often faster than an 8-input dynamic mux and HI-skew inverter because the dynamic stage has
less diffusion capacitance and parasitic delay. Domino gates are inherently noninverting, while
some functions like XOR gates necessarily require inversion. Three methods of addressing this
problem include pushing inversions into static logic, delaying clocks, and using dual-rail domino
logic. In many circuits including arithmetic logic units (ALUs), the necessary XOR gate at the
end of the path can be built with a conventional static CMOS XOR gate driven by the last domino
circuit. However, the XOR output no longer is monotonically rising and thus Domino Logic The
monotonicity problem can be solved by placing a static CMOS inverter between dynamic gates,
Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 93

as shown in Figure . This converts the monotonically falling output into a monotonically rising
signal suitable for the next gate, as shown in Figure . The dynamic-static pair together is called a
domino gate [Krambeck82] because precharge resembles setting up a chain of dominos and eval-
uation causes the gates to fire like dominos tipping over, each triggering the next. A single clock
can be used to precharge and evaluate all the logic gates within the chain. The dynamic output
is monotonically falling during evaluation, so the static inverter output is monotonically rising.
Therefore, the static inverter is usually a HI-skew gate to favor this rising output. Observe that
precharge occurs in parallel, but evaluation occurs sequentially. This explains why precharge is
usually less critical. The symbols for the dynamic NAND, HI-skew inverter, and domino AND are
shown in Figure 9.28(c). In general, more complex inverting static CMOS gates such as NANDs
or NORs can be used in place of the inverter [Sutherland99]. This mixture of dynamic and static
logic is called compound domino. For example, Figure shows an 8-input domino multiplexer built
from two 4-input dynamic multiplexers and a HI-skew NAND gate. This is often faster than an 8-
input dynamic mux and HI-skew inverter because the dynamic stage has less diffusion capacitance
and parasitic delay. Domino gates are inherently noninverting, while some functions like XOR
gates necessarily require inversion. Three methods of addressing this problem include pushing
inversions into static logic, delaying clocks, and using dual-rail domino logic. In many circuits
including arithmetic logic units (ALUs), the necessary XOR gate at the end of the path can be
built with a conventional static CMOS XOR gate driven by the last domino circuit. However, the
XOR output no longer is monotonically rising and thus

F IGURE 3.14: figure a

Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 94

F IGURE 3.15: figure b

Chapter 3. BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN 95

F IGURE 3.16: figure c

Chapter 4

Data Path Subsystems

Course Outcomes
After successful completion of this module, students should be able to:
CO 9 Develop data path subsystems such as shifters, adders, multipliers, Apply
ALUs, parity generators, counters and comparators using stick dia-
grams and layouts
CO 10 Summarize working principle of memory units and its peripheral cir- Understand
cuitry using different models.

CMOS system design consists of partitioning the system into subsystems of the types listed above.
Many options exist that make trade-offs between speed, density, programmability, ease of design,
and other variables. This chapter addresses design options for common datapath operators. The
next chapter addresses arrays, especially those used for memory. Control structures are most com-
monly coded in a hardware description language and synthesized.
Datapath operators benefit from the structured design principles of hierarchy, regularity, modular-
ity, and locality. They may use N identical circuits to process N-bit data. Related data operators
are placed physically adjacent to each other to reduce wire length and delay. Generally, data is
arranged to flow in one direction, while control signals are introduced in a direction orthogonal to
the dataflow.
Common datapath operators considered in this chapter include adders, one/zero detectors, com-
parators, counters, shifters, ALUs, and multipliers.
96
Chapter 4. Data path subsystems 97

4.1 Shifters

Consider a direct MOS switch implementation of a 4X4 crossbar switch as shown in Fig. The
arrangement is quit general and may be readily expanded to accommodate n-bit inputs/outputs. In
fact, this arrangement is an overkill in that any input line can be connected to any or all output
lines-if all switches are closed, then all inputs are connected to all outputs in one glorious short
circuit. Furthermore, 16 control signals (sw00-sw15), one for each transistor switch, must be
provided to drive the crossbar switch, and such complexity is highly undesirable. An adaption of
this arrangement) Recognizes the fact that we can couple the switch gates together in groups of
four (in this case) and also form four separate groups corresponding to shifts of zero, one, two, and
three bits. The arrangement is readily adapted so that the inlines also run horizontally (to confirm
the required strategy). The resulting arrangement is known as barrel shifter and a 4X4-bit barrel
shifter circuit diagram is given in Fig. 5.2. The interbus switches have their gate inputs connected
in staircase fashion in group of four and there are now four shift control inputs which must be
mutually exclusive in active state. CMOS transmission gates may be used in place of the simple
pass transistor switches if appropriate.

F IGURE 4.1: 4 x 4 crossbar switch

4.2 Adders

Addition is one of the basic operation perform in various processing like counting, multiplication
and filtering. Adders can be implemented in various forms to suit different speed and density
Chapter 4. Data path subsystems 98

F IGURE 4.2: Barrel shifter

requirements. The truth table of a binary full adder is shown in Figure 5.3, along with some func-
tions that will be of use during the discussion of adders. Adder inputs: A, B

F IGURE 4.3: Full adder truth table

Carry input: SUM Carry

output:CARRY
Generate signal: G(A • B); occurs when CARRY is internally generated within adder Propagate
signal: P (A + B); when it is 1, C is passed to CARRY. In some adders A ExOR B is used as the P
term because it may be reused to generate the sum term.

4.2.1 Single-Bit Adders

Probably the simplest approach to designing an adder is to implement gates to yield the required
majority logic functions as shown below.
Chapter 4. Data path subsystems 99

F IGURE 4.4: Logic gate implementation of 1-Bit adder

4.2.2 n-Bit Parallel Adder or Ripple Carry Adder

A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It can be constructed with full adders connected in cascaded, with the carry output from each
full adder connected to the carry input of the next full adder in the chain. Figure 5.7 shows the
interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder. Notice from
Figure 5.7 that the input is from the right side because the first cell traditionally represents the least
significant bit (LSB). Bits a0 and b0 in the figure represent the least significant bits of the numbers
to be added. The sum output is represented by the bits S0-S3.

4.2.3 Carry lookahead adder (CLA)

The carry lookahead adder (CLA) solves the carry delay problem by calculating the carry signals
in advance, based on the input signals. It is based on the fact that a carry signal will be generated
in two cases: (1) when both bits ai and bi are 1, or (2) when one of the two bits is 1 and the carry-in
is 1 . Thus, one can write,

ci+1 = ai.bi + (ai bi).ci si = (ai bi) ci

The above two equations can be written in terms of two new signals Pi and Gi, which are shown
in Figure 5.8: Where ci+1 = Gi + Pi.ci si = Pi ci ‘ Gi = ai.bi Pi = (ai bi) Pi and Gi are called carry
propagate and carry generate terms, respectively. Notice that the generate and propagate terms
only depend on the input bits and thus will be valid after one and two gate delay, respectively. If
one uses the above expression to calculate the carry signals, one does not need to wait for the carry
to ripple through all the previous stages to find its proper value. Let’s apply this to a 4-bit adder to
Chapter 4. Data path subsystems 100

make it clear. Putting i = 0, 1, 2, 3 in ci+1 = Gi + Pi.ci we get c1 = G0 + P0.c0 c2 = G1 + P1.G0 +

P1.P0.c0 c3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.c0 c4 = G3 + P3.G2 + P3.P2.G1 + P3..P2.P1.G0
+ P3.P2.P1.P0.c0 Notice that the carry-out bit, ci+1, of the last stage will be available after four
delays: two gate delays to calculate the propagate signals and two delays as a result of the gates
required to implement Equation c4. Figure 5.9 shows that a 4-bit CLA is built using gates to
generate the Pi and Gi and signals and a logic block to generate the carry out signals according to
Equations c1 to c4.

F IGURE 4.5: 4-bit ripple carry adder

F IGURE 4.6: Full adder stage at i with Pi and Gi shown

F IGURE 4.7: 4-Bit carry lookahead adder implementation in detail

Chapter 4. Data path subsystems 101

4.2.4 Manchester carry chain

This implementation can be very performant (20 transistors) depending on the way the XOR func-
tion is built. The carry propagation of the carry is controlled by the output of the XOR gate. The
generation of the carry is directly made by the function at the bottom. When both input signals are
1, then the inverse output carry is 0. In the schematic of Figure 5.11, the carry passes through a
completetransmission gate. If the carry path is precharged to VDD, the transmission gate is then
reduced to a simple NMOS transistor. In the same way the PMOS transistors of the carry gener-
ation is removed. One gets a Manchester cell.The Manchester cell is very fast, but a large set of
such cascaded cells would be slow. This is due to the distributed RC effect and the body effect
making the propagation time grow with the square of the number of cells. Practically, an inverter
is added every four cells, like in Figure 5.13.

F IGURE 4.8: An adder element based on the pass/generate concept

F IGURE 4.9: Manchester cell

4.3 Multipliers

In many digital signal processing operations - such as correlations, convolution, filtering, and
frequency analysis - one needs to perform multiplication. The most basic form of multiplication
Chapter 4. Data path subsystems 102

F IGURE 4.10: Cascaded Manchester carry-chain elements with buffering

consists of forming the product of two positive binary numbers. This may be accomplished through
the traditional technique of successive additions and shifts, in which each addition is conditional
on one of the multiplier bits. Here is an example.The multiplication process may be viewed to
consist of the following two steps:

ˆ Evaluation of partial products.

ˆ Accumulation of the shifted partial products.

It should be noted that binary multiplication is equivalent to a logical AND op- eration. Thus
evaluation of partial products consists of the logical ANDing of the multiplicand and the relevant
multiplier bit. Each column of partial products must then be added and, if necessary, any carry
values passed to the next column. There are a number of techniques that may be used to perform
multiplication. In general, the choice is based on factors such as speed, throughput, numerical
accuracy, and area. As a rule, multipliers may be classified by the format in which data words are
accessed, namely:- Serial form, Serial/parallel form, Parallel form Array Multiplication A parallel
multiplier is based on the observation that partial products in the multi- plication process may be
independently computed in parallel. For example, consider the unsigned binary integers X and Y.

Thus Pk are the partial product terms called summands. There are mn summands, which are
produced in parallel by a set of mn AND gates. For 4-bit numbers, the expression above may be
expanded as in the table below.

An nxn multiplier requires

(n-1)2full adders
n-1 half adders, and
n2 AND gates.
Chapter 4. Data path subsystems 103

F IGURE 4.11: bit multiplication

The worst-case delay associated with such a multiplier is (2n + l)tg, where tg is the worst-case
adder delay. Cell shown in Figure 5.16 is a cell that may be used to construct a parallel multiplier.
The Xi term is propagated diagonally from top right to bottom left, while the yj term is propagated
horizontally. Incoming partial products enter at the top. Incoming CARRY IN values enter at
the top right of the cell. The bit-wise AND is performed in the cell, and the SUM is passed
to the next cell below. The CARRY 0UT is passed to the bottom left of the cell. Figure 5.17
depicts the multiplier array with the partial products enumerated. The Multiplier can be drawn
as a square array, as shown here, Figure 5.18 is the most convenient for implementation. In this
version the degeneration of the first two rows of the multiplier are shown. The first row of the
Chapter 4. Data path subsystems 104

F IGURE 4.12: table

multiplier adders has been replaced with AND gates while the second row employs half-adders
rather than full adders. This optimization might not be done if a completely regular multiplier
were required (i.e. one array cell). In this case the appropriate inputs to the first and second row
would be connected to ground, as shown in the previous slide. An adder with equal carry and sum
propagation times is advantageous, because the worst-case multiply time depends on both paths.

F IGURE 4.13: Basic cell to construct a parallel multiplier

4.4 Parity generator

1. Parity is a very useful tool in information processing in digital computers to indicate any pres-
ence of error in bit information. 2. External noise and loss of signal strength cause loss of data bit
information while transporting data from one device to other device, located inside thecomputer
or externally 3. To indicate any occurrence of error, an extra bit is included with the message
according to the total number of 1s in a set of data, which is called parity 4. If the extra bit is
considered 0 if the total number of 1s is even and 1 for odd quantities of 1s in a set of data, then it
is called even parity. 5. On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for
Chapter 4. Data path subsystems 105

F IGURE 4.14: Array multiplier

an odd number of 1s, then it is called odd parityA parity generator is a combination logic system
to generate the parity bit at the transmitting sideIf the message bit combination is designated as,
D3D2D1D0 and Pe, Po are the even and odd parity respectively, then it is obvious from the table
that the Boolean expressions of even parity and odd parity are

Pe=D3D2D1D0

Po =(D3D2D1D0)
Chapter 4. Data path subsystems 106

The above illustration is given for a message with four bits of information. However, the logic
diagrams can be expanded with more XOR gates for any number of bits.

F IGURE 4.15: Even parity generator using logic gates

F IGURE 4.16: Odd parity generator logic gates

4.5 Zero-One detector

Detecting all ones or zeros on wide N-bit words requires large fan-in AND or NOR gates. Recall
that by DeMorgan’s law, AND, OR, NAND, and NOR are funda- mentally the same operation
except for possible inversions of the inputs and/or outputs. You can build a tree of AND gates, as
shown in Figure 4.26(b). Here, alternate NAND and NOR gates have been used. The path has log
N stages.outputs. You can build a tree of AND gates, as shown in Figure 4.26(b). Here, alternate
NAND and NOR gates have been used. The path has log N stages.
Chapter 4. Data path subsystems 107

F IGURE 4.17: One-zero detectors

4.6 Comparators

Another common and very useful combinational logic circuit is that of the Digital Comparator
circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates
that compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs. For example, along with being able to add and subtract binary
numbers we need to be able to compare them and determine whether the value of input A is greater
than, smaller than or equal to the value at input B etc. The digital comparator accomplishes this
using several logic gates that operate on the principles of Boolean Algebra. There are two main
types of Digital Comparator available and these are.

Identity Comparator an Identity Comparator is a digital comparator that has only one output ter-
minal for when A = B either “HIGH” A = B = 1or “LOW” A = B = 0 Magnitude Comparator a
Magnitude Comparator is a type of digital com- parator that has three output terminals, one each
for equality, A = B greater than,A ¿ B and less than A ¡ B

The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3, . An, etc) against that of a constant or unknown value such as B (B1, B2,
B3, . Bn, etc) and produce an output condition or flag depending upon the result of the comparison.
For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the following
three output conditions when compared to each other. A ¿ B, A + B, A ¡ B
Chapter 4. Data path subsystems 108

Which means: A is greater than B, A is equal to B, and A is less than B This is useful if we want to
compare two variables and want to produce an output when any of the above three conditions are
achieved. For example, produce an output from a counter when a certain count number is reached.
Consider the simple 1-bit comparator below. Then the operation of a 1-bit digital comparator is
given in the following Truth Table.

Inputs Outputs B A A ¿ B A=B A ¡ B 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 1 0 0 0

From the above table the obtained expressions for magnitude comparator using K-map are as
follows

For A ¡ B : C = AB For A = B : D = AB + AB

F IGURE 4.18: bit Digital Comparator

4.7 Counters

Counters can be implemented using the adder/subtractor circuits and registers (or equivalently, D
flip- flops) The simplest counter circuits can be built using T flip-flops because the tog- gle feature
is naturally suited for the implementation of the counting operation. Counters are available in two
categories
Chapter 4. Data path subsystems 109

4.7.1 Asynchronous(Ripple counters)

Asynchronous counters, also known as ripple counters, are not clocked by a common pulse and
hence every flip-flop in the counter changes at different times. The flip-flops in an asynchronous
counter is usually clocked by the output pulse of the preceding flip-flop. The first flip-flop is
clocked by an external event. The flip-flop output transition serves as a source for triggering other
flip-flops i.e the C input (clock input) of some or all flip-flops are triggered NOT by the common
clock pulses Eg:- Binary ripple counters, BCD ripple counters

4.7.2 Synchronous counters

A synchronous counter however, has an internal clock, and the external event is used to produce a
pulse which is synchronized with this internal clock. C input (clock input) of all flip-flops receive
the common clock pulses

E.g.:- Binary counter, Up-down Binary counter, BCD Binary counter, Ring counter, Johnson
counter,

4.7.3 Latches

There are many approaches for constructing latches. One very common technique involves the
use of transmission gate multiplexers. Multiplexer based latches can provide similar functionality
to the SR latch, but has the important added advantage that the sizing of devices only affects
performance and is not critical to the functionality.
Figure 4.19 shows an implementation of static positive and negative latches based on multiplexers.
For a negative latch, when the clock signal is low, the input 0 of the multiplexer is selected, and
the D input is passed to the output. When the clock signal is high,the input 1 of the multiplexer,
which connects to the output of the latch, is selected. The feedback holds the output stable while
the clock signal is high. Similarly in the positive latch, the D input is selected when clock is high,
and the output is held (using feedback) when clock is low.
A transistor level implementation of a positive latch based on multiplexers is shown in Figure
7.12. When CLK is high, the bottom transmission gate is on and the latch is transparent - that is,
the D input is copied to the Q output. During this phase, the feedback loop is open since the top
Chapter 4. Data path subsystems 110

transmission gate is off. Unlike the SR FF, the feedback does not have to be overridden to write
the memory and hence sizing of transistors is not critical for realizing correct functionality.
The number of transistors that the clock touches is important since it has an activity factor of 1.
This particular latch implementation is not particularly efficient from this metric as it It is possible
to reduce the clock load to two transistors by using implement multiplexers using NMOS only
pass transistor as shown in Figure 7.13. The advantage of this approach is the reduced clock load
of only two NMOS devices. When CLK is high, the latch samples the D input, while a low clock-
signal enables the feedback-loop, and puts the latch in the hold mode. While attractive for its
simplicity, the use of NMOS only pass transistors results in the passing of a degraded high voltage
of VDD-VTn to the input of the first inverter. This impacts both noise margin and the switching
performance, especially in the case of low values of VDD and high values of VTn. It also causes
static power dissipation in first inverter, as already pointed out in Chapter 6. Since the maximum
input-voltage to the inverter equals VDD-VTn, the PMOS device of the inverter is never turned
off, resulting is a static current flow.

F IGURE 4.19: latch

F IGURE 4.20: transmission gates

Chapter 4. Data path subsystems 111

4.8 MEMORY ELEMENTS

4.8.1 SRAM

An SRAM (Static Random Access Memory) is designed to fill two needs; to provide a dect inter-
face with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systems that re-
quire very low power consumption. In the first role, the SRAM serves as cache memory,interfacing
between DRAMs and the CPU. Figure 7.29 shows a typical PC microprocessor memory configu-
ration.
The second driving force for SRAM technology is low power applications. In this case, SRAMs
are used in most portable equipment because the DRAM refresh cirent is several orders of mag-
nitude more than the low-power SRAM standby ciurent. For low-power SRAMs, access time is
comparable to a standard DRAM

How the Device Works

The textbf SRAM cell consists of a bi-stable flip-flop connected to the internal ccuitry by two
access ansistors. When the cell is not addressed, the two access transistors are closed and the data
is kept to a stable state, latched within the flip-flop (Fig. 7.30).
The flip-flop needs the power supply to keep the information. The data in an SRAM cell is volatile
(i.e., the data is lost when the power is removed). However, the data does not “leak away” like in
a DRAM, so theSRAM does not require a refresh cycle.

Read -write
Figure 7.31 shows the read/write operations of an SRAM. To select a cell, the two access transistors
must be “on” so the elementary cell (the flip-flop) can be connected to the internal

SRAM circuitry. These two access ansistors of a cell are connected to ie word line (a called row
or X address). The selected row will be set at v c c . The two flip-flop sides are 1 connected to a
pair of lines, B and B. The bit lines are also called colunus or Y addresses.
During ã read operation these two bit lines are connected to the sense amplifier that recognizes if
a logic data “1” or “0” is stored in the selected elementary cell. This sense amplifierthen transfers
the logic state to the output buffer, which is connected to the output pad. There are as many sense
Chapter 4. Data path subsystems 112

F IGURE 4.21: Memories in a microprocessor.

F IGURE 4.22: SRAM cell

amplifiers as there are output pads.

During a write operation, data comes from the input pad. It then moves to the write c- cuitry. Since
the write ccuitry drivers are stronger than the cell flip-flop transistors, the data will be forced onto
the cell.
When the read/write operation is completed, the word line (row) is set to ov, the cell (flip-flop)
either keeps its original data for a read cycle or stores the new data, which was loaded during the
write cycle

textbf Data Retention To work properly and to ensure that the data m the elementary cell will not
be altered, the SRAM must be supplied by a Vcc (power supply) that will not fluctuate beyond
plus or minus five or ten per cent of the Vcc-
If the elementary cell is not disturbed, a lower voltage (2 volts) is acceptable to ensure that the
Chapter 4. Data path subsystems 113

F IGURE 4.23: Read-Write operations

cell will coectly keep the data. In that case, the SRAM is set to a retention mode where the power
supply is lowered, and the part is no longer accessible. Figure 7.32 shows an example of how the
Vcc power supply must be lowered to ensure good data retention

F IGURE 4.24: SRAM data retention waveform

Chapter 5

LOGIC DESIGN AND TESTING

STRATEGIES

5.1 Programmable logic devices

A programmable logic device or PLD is an electronic component used to build reconfigurable

digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function
at the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that
is, reconfigured.

5.1.1 PLA s

Combinational circuit elements are an important part of any digital design. Three common meth-
ods of implementing a combinational block are random logic, read-only memory (ROM), and
programmable logic array (PLA). In random-logic designs, the logic description of the circuit is
directly translated into hardware structures such as AND and OR gates. The difficulty in this
method is that the placement and interconnection cost is high. In a large system, this cost could
be prohibitive. The ROM is useful for tabular data that has little regularity, but it is very wasteful
of space for data that could be algorithmically derived. The PLA combines features of both other
methods by allowing the designer to realize combinational design with programming taps on a
logic array

114
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 115

The PLA is made up of an AND plane and an OR plane. The AND plane produces product terms
of input variables selected by the programming taps and the OR plane produces the sums of these
product terms selected by a different set of programming taps. The symbolic representation of
the places where the programming taps are placed is known as the personality matrix of the PLA.
Figure shows the generic structure of a PLA that programs these logic functions

F IGURE 5.1: Barrel shifter

PLA s are popular because their generation can be automated, which frees the designer from
spending valuable time creating random-logic gates. Since the PLA generator fixes the physical
structure of the PLA, there arises the problem of accommodating the designer’s special require-
ments, if any. The first requirement would be to reduce the area occupied by the PLA. Usually
the personality matrix is so sparse that a straightforward mapping of the matrix to the silicon will
result in wasted silicon area. Instead, the PLA is folded to reduce the area required for the physical
implementation. Instead of having one AND plane and one OR plane, the PLA can be split into
many more AND and OR planes. Also, the input and output columns can be moved and folded
such that there are two to a column instead of the usual one. The rows can be similarly moved and
folded

5.1.2 Programming Array Logic

PALs were introduced in late 1970 to address speed problem shown by PLA devices. A PAL is
opposite to PROM, where AND array is programmable but OR array is fixed. This led PAL faster
than PLA devices. PAL s usually contain flip-flops connected to the OR-gate outputs to implement
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 116

F IGURE 5.2: PLA structure

sequential circuits. Registered or combinational output functions are modeled in a sum of product
form. Each output is a sum (logical or) of a fixed number of products (logical and) of the input
signals. PAL architecture has feedback terms. The outputs of the fixed ”or” array are fed back to
some of the inputs of the ”and” array.

F IGURE 5.3: PAL IC

Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 117

5.1.3 Field Programmable Gate Array

Fully fabricated FPGA chips containing thousands or even more, of logic gates with programmable
interconnects, are available to users for their custom hardware programming to realize desired
functionality. This design style provides a means for fast prototyping and also for cost-effective
chip design, especially for low-volume applications. A typical field programmable gate array
(FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and pro-
grammable interconnect structures. The programming of the interconnects is accomplished by
programming of RAM cells whose output terminals are connected to the gates of MOS pass tran-
sistors. Thus, the signal routing between the CLBs and the I/O blocks is accomplished by setting
the configurable switch matrices accordingly. The general architecture of an FPGA chip from Xil-
inx . showing the locations of switch matrices used for interconnect routing

F IGURE 5.4: FPGA Block diagram

Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 118

5.1.4 Gate Array Design

In terms of fast prototyping capability, the gate array (GA) ranks second after the FPGA with
a typical turn-around time of a few days. While user programming is central to the design im-
plementation of the FPGA chip, metal mask design and processing is used for GA. Gate array
implementation requires a two-step manufacturing process: The first phase, which is based on
generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These
uncommitted chips can be stored for later customization, which is completed by defining the metal
interconnects between the transistors of the array. Since the patterning of metallic interconnects is
done at the end of the chip fabrication process, the turn-around time can still be short, a few days
to a few weeks. A corner of a gate array chip which contains bonding pads on its left and bottom
edges, diodes for 1O protection, nMOS transistors and pMOS transistors for chip output driver
circuits adjacent to bonding pads, arrays of nMOS transistors and pMOS transistors, underpass
wire segments, and power and ground buses along with contact windows. The availability of these
routing channels simplifies the interconnections, even using one metal layer only. Interconnection
patterns that perform basic logic gates can be stored in a library, which can then be used to cus-
tomize rows of uncommitted transistors according to the netlist

Standard-Cells Based Design

The standard-cells based design is one of the most prevalent full custom design styles which re-
quire development of a full custom mask set. The standard cell is also called the polycell. In this
design style, all of the commonly used logic cells are developed, characterized, and stored in a
standard cell library. A typical library may contain a few hundred cells including inverters, NAND
gates, NOR gates, complex AOI, OAI gates, D latches, and flip-flops. Each gate type can be im-
plemented in several versions to provide adequate driving capability for different fan-outs. For
instance, the inverter gate can have standard size, double size, and quadruple size so that the chip
designer can choose the proper size to achieve high circuit speed and layout density. Each cell is
characterized according to several different characterization categories, including: Delay time ver-
sus load capacitance, Circuit simulation model, Timing simulation model, Fault simulation model,
Cell data for place-androute, Mask data. To enable automated placement of the cells and routing
of inter-cell connections, each cell layout is designed with a fixed height, so that a number of
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 119

cells can be abutted side-by-side to form rows. The power and ground rails typically run paral-
lel to the upper and lower boundaries of the cell, thus, neighboring cells share a common power
and ground bus. The input and output pins are located on the upper and lower boundaries of the cel

F IGURE 5.5: Standard-Cells Based Design

Based Design2.png

F IGURE 5.6: Based Design 2

5.1.5 Full Custom Design

Although the standard-cells based design style is sometimes called full custom design, in a strict
sense, it is somewhat less than fully customized since the cells are pre-designed for general use
and the same cells are utilized in many different chip designs. In a truly full-custom design, the
entire mask design is done anew without use of any library. However, the development cost of
such a design style is becoming prohibitively high. Thus, the concept of design reuse is becoming
popular in order to reduce design cycle time and development cost. The most rigorous full custom
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 120

design can be the design of a memory cell, be it static or dynamic. Since the same layout design
is replicated, there would not be any alternative to high density memory chip design. For logic
chip design, a good compromise can be achieved by using a combination of different design styles
on the same chip, such as standard cells, data-path cells and programmable logic arrays (PLAs).
In real full-custom layout in which the geometry, orientation and placement of every transistor is
done individually by the designer, design productivity is usually very low - typically a few tens of
transistors per day, per designer. In digital CMOS VLSI, full-custom design is rarely used due to
the high labor cost. Exceptions to this include the design of high-volume products such as memory
chips, high-performance microprocessors and FPGA masters. Figure 14.23 shows the full layout
of the Intel 486 microprocessor chip, which is a good example of a hybrid fullcustom design. Here,
one can identify four different design styles on one chip: memory banks (RAM cache), data-path
units consisting of bit-slice cells, control circuitry mainly consisting of standard cells and PLA
blocks.
CMOS TESING

5.1.6 NEED FOR TESTING MOTIVATION

Following the so-called Moore’s law [Moore 1965], the scale of ICs has doubled every 18 months.
A simple example of this trend is the progression from SSI to VLSI devices. In the 1980s, the
term “VLSI” was used for chips having more than 100,000 transistors and has continued to be
used over time to refer to chips with millions and now hundreds of millions of transistors. In 1986,
the first megabit random access memory (RAM) contained more than 1 million transistors. Micro-
processors produced in 1994 contained more than 3 million transistors. VLSI devices with many
millions of transistors are commonly used in today’s computers and electronic appliances. This is
a direct result of the steadily decreasing dimensions, referred to as feature size, of the transistors
and interconnecting wires from tens of microns to tens of nanometres, with current submicron
technologies based on a feature size of less than 100 nanometres (100 nm).

The reduction in feature size has also resulted in increased operating frequencies and dock speeds;
for exanq)le, in 971, ie first microprocessor ran at a clock frequency of 108 kHz, while current
commercially available microprocessors commonly run at several gigahertz. The reduction in fea-
ture size increases the probability that a manufacturing defect in the IC will result in a faulty chip.
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 121

A very small defect can easily result in a faulty transistor when the feature size is less than 100 nm.
Furthermore, it takes only one transistor or wire to make the entire chip fail to function properly
or at ie required operating frequency. Yet, defects created during the manufacturing process are
unavoidable, and, as a result, some number of ICs is expected to be faulty; therefore, testing is
required to guarantee fault free products, regardless of whether the product is a VLSI device or
an electronic system composed of many VLSI devices. It is also necessary to test components at
various stages the manufacturing process. For example, in order to produce an electronic system,
we must produce ICs, use these ICs to assemble printed circuit boards (PCBs), and then use the
PCBs to assemble the system. There is general agreement with the rule of ten, which says that the
cost of detecting a faulty IC increases by an order of magnitude as we move through each stage
of manufacturing, from device level to board level to system level and finally to system operation
in the field. Electronic testing includes IC testing, PCB testing, and system testing at the various
manufacturing stages and, m some cases, during system operation. Testing is used not only to
find the fault-free devices, PCBs, and systems but also to improve production yield at the various
stages o f manufacturing by analyzing the cause o f defects when faults are encountered. In some
systems, periodic testing is performed to ensure fault-free system operation and to initiate repair
procedures when faults are detected. Hence, VLSI testing is important to designers, product engi-
neers, test engineers, managers, manufacturers, and end-users.

5.1.7 Challenges in VLSI Testing

The physical implementation of a VLSI device is very complicated. Any small piece of dust
or abnormality of geometrical shape can result in a defect. Defects are caused by process vari-
ations or random localized manufacturing imperfections. Process variations affecting transistor
channel length, transistor threshold voltage, metal interconnect width and thickness, and inter
metal layer dielectric thickness will impact logical and timing performance. Random localized
imperfections can result in resistive bridging between metal lines, resistive opens in metal lines,
improper via formation, etc. Recent advances in physics, chemistry, and materials science have
allowed production of nanometre-scale structures using sophisticated fabrication techniques. It is
widely recognized that nanometre-scale devices will have much higher manufacturing defect rates
compared to conventional complementary metal oxide semiconductor (CMOS) devices. They will
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 122

have much lower current drive capabilities and will be much more sensitive to noise-induced er-
rors such as crosstalk. They will be more susceptible to failures of transistors and wires due to soft
(cosmic) errors, process variations, electro migration, and material aging. As the integration scale
increases, more transistors can be fabricated on a single chip, thus reducing the cost per transistor;
however, the difficulty of testing each transistor increases due to the increased complexity of the
VLSI device and increased potential for defects, as well as the difficulty of detecting the faults
produced by those defects.

Manufacturing tests fall into a number of categories

5.1.8 TEST PRINCIPLES

A fault is a representation of a defect reflecting a physical condition that causes a circuit to fail to
perform in a required manner. A failure is a deviation in the performance of a circuit or system
from its specified behavior and represents an reversible state of a component such that it must be
repaired in order for it to provide its intended design function. A circuit error is a wrong output
signal produced by a defective circuit. A circuit defect may lead to a fault, a fault can cause a
circuit error, and a circuit error can result in a system failure

5.1.9 Exhaustive Testing

To test a circuit with n inputs and m outputs, a set of input patterns is applied to the circuit under
test (CUT), and its responses are compared to the known good responses of a fault-free circuit.
Each input pattern is called a test vector. In order to completely test a circuit many test patterns are
required however, it is difficult to know how many test vectors are needed to guarantee a satisfac-
tory reject rate. If the CUT is an n input combinational logic circuit we can apply all 2n possible
input patterns for testing stuck-at faults; this approach is called exhaustive testing.
If a circuit passes exhaustive testing, we might assume that the circuit does not contain functional
faults, regardless of its internal structure. Unfortunately, exhaustive testing is not practical when n
is large. Furthermore, applying all 2n possible input patterns to an n-input sequential logic circuit
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 123

will not guarantee that all possible states have been visited. However, this method of applying all
possible input test patterns to an n-input combinational logic circuit also illustrates the basic idea
of functional testing.

subsection Functional Testing

In this testing every entry in the truth table for the combinational logic circuit is tested to determine
whether it produces the correct response. In practice, functional testing is considered by many de-
signers and test engineers to be testing the CUT as thoroughly as possible in a system-like mode
of operation. In either case, one problem is the lack of a quantitative measure of the defects that
will be detected by the set of functional test vectors.

subsection Structural Testing

The approach of structural testing is to select specific test patterns based on circuit structural infor-
mation and a set of fault models. Structural testing saves time and improves test efficiency, as the
total number of test patterns is decreased because the test vectors target specific faults that would
result from defects in the manufactured circuit. Structural testing cannot guarantee detection of all
possible manufacturing defects, as the test vectors are generated based on specific fault models;
however, the use of fault models does provide a quantitative measure of the fault-detection capa-
bility of a given set of test vectors for a targeted fault model. This measure is called fault coverage
and is defined as

Fault coverage is linked to the yield and the defect level by the following expression

From this equation, we can show that a PCB with 40 chips, each having 90

5.1.10 Stuck at Faults

The most commonly used model in VLSI circuit testing is the stuck at fault (SAF) model. The
SAF model assumes that any node (a net in a netlist) within a silicon chip has the potential risk of
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 124

F IGURE 5.7: fault coverage

F IGURE 5.8: fault detection effeciency

F IGURE 5.9: defect level

being permanently tied to power (stuck at one, SAl) or ground (stuck at zero, SAO) due to vari-
ous manufacturing defects. Either SAl or SAO makes the affected node non-functional since that
node cannot be switched by the circuit for logic operation any longer. Consequently, the chips that
contain such nodes are regarded as bad chips and cannot be delivered to the customer. Design for
test is the art of inserting some extra testing circuitry inside the chip to search for such SAF nodes
An SAF is a particular fault model used by fault simulators and automatic test pattern generation
(ATPG) tools to mimic a manufacturing defect within an integrated circuit. It is not the only model
for DFT but it is the simplest and most widely used, especially for digital designs since 0 and 1 are
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 125

the only concerns in these circuits. However, although very powerful, the SAF model is not a true
description of how a node is mal manufactured or damaged. It does not provide physical manifes-
tations of the defect (defect mechanism) but only the behavior or effect caused by the defect. For
example, metal shorting through a foreign material between a node and ground node or the failure
of an internal transistor could both cause an SAO.

5.1.11 CONTROLLABILITY AND OBSERVABILITY

The most common approach to testing a digital circuit is to toggle every node inside the circuit and
observe the corresponding effect. The foundation of this approach is the SAF model. However,
in practice, this is not always easily achieved. In a circuit of combinational logic, (he logic states
of the internal nodes can be determined if the circuit’s inputs are all known. But for a circuit that
includes sequential elements, such as flip-flops and latches, this is not true. Some of the node’s
logic states depend on these sequential cell’s previous states. This leads to controllability and ob-
servability issues
In the design for testability regime, for any node in a circuit, controllability is defined as the capa-
bility of a node being driven to 1 or 0 through a circuit’s inputs. If this node can be driven faithfully
to 1 and 0, it is regarded as controllable. Observability is defined as the capability of the logic state
of this node being observed at the circuit’s outputs. If the logic state of this node can reliably be
observed, this node is regarded as observable. Whether a circuit node is stuck at 1 (or 0) is only
testable if that node is both controllable and observable.

5.1.12 DESIGN FOR TESTABILITY

Test engineers usually have to construct test vectors after the design is completed. This invariably
requires a substantial amount of time and effort that could be avoided if testing is considered early
in the design flow to make the design more testable. As a result, integration of design and test,
referred to as design for testability (DFT), was proposed in the 1970s
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 126

DFT techniques generally fall into one of the following three categories: Ad hoc DFT techniques
Level-sensitive scan design (LSSD) or scan design Built-in self-test (BIST)

5.1.13 Built in Self-Test

Built-in Self-Test, or BIST, is the technique of designing additional hardware and software features
into integrated circuits to allow them to perform self-testing, i.e., testing of their own operation
(functionally, parametrically, or both) using their own circuits, thereby reducing dependence on an
external automated test equipment (ATE).

BIST is a design-for-testability technique that places the testing functions physically with the cir-
cuit under test (CUT), as illustrated in Figure. The basic BIST architecture requires the addition
of three hardware blocks to a digital circuit: a test pattern generator, a response analyzer, and a
test controller. The test pattern generator generates the test patterns for the CUT. Examples of
pattern generators are a ROM with stored patterns, a counter, and a linear feedback shift register
(LFSR). A typical response analyzer is a comparator with stored responses or an LFSR used as
a signature analyzer. It compacts and analyzes the test responses to determine correctness of the
CUT. A test control block is necessary to activate the test and analyze the responses. However, in
general, several test-related functions can be executed through a test controller circuit.

As shown in Figure, the wires from primary inputs (PIs) to MUX and wires from circuit output to
primary outputs (POs) cannot be tested by BIST. In normal operation, the CUT receives its inputs
from other modules and performs the function for which it was designed. During test mode, a
test pattern generator circuit applies a sequence of test patterns to the CUT, and the test responses
are evaluated by a output response compactor. In the most common type of BIST, test responses
are compacted in output response compactor to form (fault) signatures. The response signatures
are compared with reference golden signatures generated or stored on- chip, and the error signal
indicates whether chip is good or faulty.
Four primary parameters must be considered in developing a BIST methodology for embedded
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 127

systems; these correspond with the design parameters for on-line testing techniques. Fault cover-
age: This is the fraction of faults of interest that can be exposed by the test patterns produced by
pattern generator and detected by output response monitor. In presence of input bit stream errors
there is a chance that the computed signature matches the golden signature, and the circuit is re-
ported as fault free. This undesirable property is called masking or aliasing

Test set size: This is the number of test patterns produced by the test generator, and is closely
linked to fault coverage: generally, large test sets imply high fault coverage.

Hardware overhead: The extra hardware required for BIST is considered to be overhead. In most
embedded systems, high hardware overhead is not acceptable.

Performance overhead: This refers to the impact of BIST hardware on normal circuit performance
such as its worst-case (critical) path delays. Overhead of this type is sometimes more important
than hardware overhead.

Area Overhead: Additional active area due to test controller, pattern generator, response evaluator
and testing of BIST hardware

Pin Overhead: At least 1 additional pin is needed to activate BIST operation. Input MUX adds
extra pin overheads

Performance overhead: Extra path delays are added due to BIST.

Yield loss increases due to increased chip area.
It reduces testing and maintenance cost, as it requires simpler and less expensive ATE. Design
effort and time increases due to design BIST.

The BIST hardware complexity increases when the BIST hardware is made testable.
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 128

It reduces testing and maintenance cost, as it requires simpler and less expensive ATE.

BIST significantly reduces cost of automatic test pattern generation (ATPG

It reduces storage and maintenance of test patterns

It can test many units in parallel
It takes shorter test application times
It can test at functional system speed.

BIST can be used for non-concurrent, on-line testing of the logic and memory parts of a system .
It can readily be configured for event-triggered testing, in which case, the BIST control can be tied
to the system reset so that testing occurs during system start-up or shutdown. BIST can also be
designed for periodic testing with low fault latency. This requires incorporating a testing process
into the CUT that guarantees the detection of all target faults within a fixed time.
On-line BIST is usually implemented with the twin goals of complete fault coverage and low
fault latency. Hence, the test generation (TG) and response monitor (RM) are generally designed
to guarantee coverage of specific fault models, minimum hardware overhead, and reasonable set
size. These goals are met by different techniques in different parts of the system.

TG and RM are often implemented by simple, counter-like circuits, especially linear-feedback

shift registers (LFSRs). The LFSR is simply a shift register formed from standard flip-flops, with
the outputs of selected flip-flops being fed back (modulo-2) to the shift register’s inputs. When
used as a TG, an LFSR is set to cycle rapidly through a large number of its states. These states,
whose choice and order depend on the design parameters of the LFSR, define the test patterns. In
this mode of operation, an LFSR is seen as a source of (pseudo) random tests that are, in principle,
applicable to any fault and circuit types. An LFSR can also serve as an RM by counting (in a
special sense) the responses produced by the tests. An LFSR RM’s final contents after applying a
sequence of test responses forms a fault signature, which can be compared to a known or generated
good signature, to see if a fault is present. Ensuring that the fault coverage is sufficiently high and
the number of tests is sufficiently low are the main problems with random BIST methods. Two
general approaches have been proposed to preserve the cost advantages of LFSRs while making
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 129

the generated test sequence much shorter. Test points can be inserted in the CUT to improve con-
trollability and observability; however, they can also result in performance loss. lternatively, some
determinism can be introduced into the generated test sequence, for example, by inserting specific
“seed” tests that are known to detect hard faults.

A typical BIST architecture using LFSR is shown in Figure . Since the output patterns of the
LFSR are time-shifted and repeated, they become correlated; this reduces the effectiveness of the
fault detection. Therefore a phase shifter (a network of XOR gates) is often used to decorrelate the
output patterns of the LFSR. The response of the CUT is usually compacted by a multiple input
shift register (MISR) to a small signature, which is compared with a known fault- free signature to
determine whether the CUT is faulty.

F IGURE 5.10: a phase shifter

A string of 0’s and 1’s is called a pseudo-random binary sequence when the bits appear to be
random in the local sense, but they are in someway repeatable. The linear feedback shift regis-
ter (LFSR) pattern generator is most commonly used for pseudo-random pattern generation. In
general, this requires more patterns than deterministic ATPG, but less than the exhaustive test. In
contrast with other methods, pseudo-random pattern BIST may require a long test time and neces-
sitate evaluation of fault coverage by fault simulation. This pattern type, however, has the potential
for lower hardware and performance overheads and less design effort than the preceding methods.
In pseudorandom test patterns, each bit has an approximately equal probability of being a 0 or a 1.
The number of patterns applied is typically of the order of 103 to 107 and is related to the circuit’s
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 130

testability and the fault coverage required.

Linear feedback shift register reseeding is an example of a BIST technique that is based on control-
ling the LFSR state. LFSR reseeding may be static, that is LFSR stops generating patterns while
loading seeds, or dynamic, that is, test generation and seed loading can proceed simultaneously.
The length of the seed can be either equal to the size of the LFSR (full reseeding) or less than the
LFSR (partial reseeding). In [5], a dynamic reseeding technique that allows partial reseeding is
proposed to encode test vectors. A set of linear equations is solved to obtain the seeds, and test
vectors are ordered to facilitate the solution of this set of linear equations.

Figure shows a standard, external exclusive-OR linear feedback shift register. There are n flip-flops
(Xn-1,. . . . . . X0) and this is called n-stage LFSR. It can be a near-exhaustive test pattern genera-
tor as it cycles through 2n-1 states excluding all 0 states. This is known as a maximal length LFSR.

In addition to an LFSR, a straightforward way to compress the test response data and produce a
fault signature is to use an FSM or an accumulator. However, the FSM hardware overhead and ac-
cumulator aliasing are difficult parameters to control. Keeping the hardware overhead acceptably
low and reducing aliasing are the main difficulty in RM design.

The number of ones in the CUT output response is counted. In this method the number of ones is
the signature. It requires a simple counter to accomplish the goal. Figure shows the test structure
of ones count for a single output CUT. For multiple output ones, a counter for each output or one
output at a time with the same input sequence can be used. Input test sequence can be permuted
without changing the count.

It is very similar to ones count technique. In this method the number of transitions in the CUT
response, zero to one and/or one to zero is counted. Figure 40.11 shows a test structure of transi-
tion counting. It has simple hardware DFF with EXOR to detect a transition and counter to count
number of transitions. It has less aliasing probability than ones counting. Test sequences cannot
be permuted. Permutation of input sequences will change the number of transitions. On the other
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 131

F IGURE 5.11: Standard Linear Feedback Shift Register

F IGURE 5.12: Ones count compression circuit structure

hand, one can reorder the test sequence to maximize or minimize the transitions, hence, minimize
the aliasing probability.

Syndrome is defined as the probability of ones of the CUT output response. The syndrome is 1/8
for a 3-input AND gate and 7/8 for a 3-input OR gate if the inputs has equal probability of ones
and zeros. Figure 40.12 shows a BIST circuit structure for the syndrome count. It is very similar
to ones count and transition count. The difference is that the final count is divided by the number
of patterns being applied. The most distinguished feature of syndrome testing is that the syndrome
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 132

F IGURE 5.13: Transition count compression circuit structure

is independent of the implementation. It is solely determined by its function of the circuit.

F IGURE 5.14: Syndrome testing circuit structure

The originally design of syndrome test applies exhaustive patterns. Hence, the syndrome is S K
/ 2n , where n is the number of inputs and K is the number of minterms. A circuit is syndrome
testable if all single stuck-at faults are syndrome detectable. The interesting part of syndrome test-
ing is that any function can be designed as being syndrome testable.
Built-in logic block observation is a well known approach for pipelined architecture. It adds some
extra hardware to the existing registers (D flip-flop, pattern generator, response compacter, scan
chain) to make them multifunctional. All FFs are reset to 0. The circuit diagram of a BILBO
module is shown in Figure 40.17. The BILBO has two control signals (B1 and B2).
Chapter 5. LOGIC DESIGN AND TESTING STRATEGIES 133

(a) Scan-in-Scan-out: shift register (b) Normal register mode: PIPO register (c) Pattern generator
mode: LFSR (d) Response compactor mode: MISR

F IGURE 5.15: BILBO Example

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