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Ec3561 Set2

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26 views3 pages

Ec3561 Set2

Uploaded by

sg.balachandran81
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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B.E / B.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2023


Fifth Semester

EC3561 - VLSI LABORATORY

(Regulations 2021)

Time : 3 Hours Answer any one Question Max. Marks 100

Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total


required/Procedure Program/Drawing & Results
20 30 30 10 10 100

1. Design and simulate an 8-bit adder and using suitable software package perform
comparison of pre synthesis and post synthesis simulation. Implement the topic using
FPGA.

2. Design and implement a 4-bit Multiplier using HDL and simulate it using Xilinx/Altera
Software and also implement the logic using a suitable FPGA.

3. Design half adder and half subtractor using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA.

4. Design full adder and full subtractor using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA.

5. Design an encoder and decoder using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA.

6. Design D flip-flop circuit and T flip-flop using HDL. Simulate it using suitable Software
and implement using FPGA.

7. Design a 4-bit Universal shift register, Simulate it using HDL and implement it in FPGA.

8. Design and simulate a CMOS RS Flip flop with Manual/Automatic Layout Generation
and Post Layout Extraction by performing Pre-Layout and Post Layout Simulations and
also analyze the Power, Area and Timing.

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9. Design and simulate a CMOS JK Flip flop with Manual/Automatic Layout Generation
and Post Layout Extraction by performing Pre-Layout and Post Layout Simulations and
also analyze the Power, Area and Timing.

10. Design and implement a SRAM using HDL and simulate it using Xilinx/Altera Software
and also implement the logic using a suitable FPGA.

11. Design and implement a DRAM using HDL and simulate it using Xilinx/Altera Software
and also implement the logic using a suitable FPGA.

12. Design and implement a ROM using HDL and simulate it using Xilinx/Altera Software
and also implement the logic using a suitable FPGA.

13. Design and simulate a Moore Finite State Machine logic using HDL and generate its
synthesis report, RTL logic and visualize its schematic view and perform functional
verification.

14. Design and implement a Mealy Finite State Machine logic using HDL and generate its
synthesis report, RTL logic and visualize its schematic view and perform functional
verification.

15. Design 3-bit synchronous up/down counter using HDL. Simulate it using Xilinx/Altera

Software and implement by Xilinx/Altera FPGA

16. Design and simulate inverting amplifier using CMOS logic and analyze its gain and
bandwidth parameter with schematic simulation of EDA tool.

17. Design and simulate a basic Common Drain Amplifier circuit using EDA tool and
analyze the input impedance, output impedance, gain and bandwidth by performing
Schematic Simulations.

18. Design and simulate a basic Common Gate Amplifier circuit using EDA tool and analyze
the input impedance, output impedance, gain and bandwidth by performing Schematic
Simulations.

19. Design and simulate a basic Common Source Amplifier circuit using EDA tool and
analyze the input impedance, output impedance, gain and bandwidth by performing
Schematic Simulations.

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20. Design and simulate a simple 5 transistor differential amplifier and analyze its gain,
bandwidth and CMRR by performing schematic simulations?

21. Design 4-bit Asynchronous up/down counter using HDL. Simulate it using Xilinx/Altera

Software and implement by Xilinx/Altera FPGA

22. Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate

Manual/Automatic Layout

23. Design a circuit for 2 input AND & OR gates using CMOS logic and simulate it for
logical verification and generate its layout by EDA tool.

24. Design a circuit for 3 input NAND & NOR gates using CMOS logic and verify the logic
and generate its layout using EDA tool.

25. Design and simulate D flip flop logic using CMOS logic and analyze its’ performances
by layout simulation using EDA tool.

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