UVM FIFO Project

Supervisor: Eng. Kareem Waseem

Mostafa Kamal Mohamed

Table of contents
I. Introduction to FIFO

II. FIFO Interface

III. Verification Plan

IV. RTL Bugs Report

V. UVM Structure and description

VI. Design and UVM codes

VII. Questa snippets

VIII. Do File and Source files

IX. Full wave of FIFO

X. FIFO Coverage report

XI. Assertions table

I. Introduction to FIFO
A First-In, First-Out (FIFO) buffer is a fundamental data structure used in both
hardware and software systems to manage data flow. As the name suggests, it
operates on a queueing principle where the first piece of data to enter the buffer is
also the first to leave, making it ideal for sequential data handling. FIFOs are widely
utilized in scenarios that require orderly data transmission and reception, especially
where data needs to be processed in the exact order it arrives.

In digital systems, FIFO buffers are essential for temporary data storage and are
often implemented in hardware as part of memory structures or as standalone
modules. In software, FIFOs can be used in algorithms or operating system-level
tasks, such as inter-process communication.

Key Applications of FIFO:

1. Data Communication: FIFOs are crucial in buffering data between systems
with different clock domains, such as between a processor and a peripheral
device, ensuring that data is not lost when speeds differ.

2. Networking: In network routers and switches, FIFOs are used to queue

packets before forwarding them, managing traffic flow and avoiding data
collisions or loss.

3. Audio/Video Streaming: FIFO buffers smooth out the streaming of audio and
video signals by temporarily holding the data before processing, preventing
interruptions due to uneven data transmission.

4. Digital Signal Processing (DSP): In signal processing systems, FIFOs manage

continuous data flow between different stages of a pipeline to avoid data
overwrites or underflows.

5. Microprocessor Systems: FIFOs are often used in CPU peripherals (such as

UARTs) to queue incoming and outgoing data, enabling efficient data
handling and processing.

6. Control Systems: In embedded systems, FIFOs help manage sensor data and
ensure that control loops receive and process input in the correct order.
 II. FIFO Interface
Port Direction Function

clk input Clock signal

rst_n Active low asynchronous reset

wr_en Write Enable: If the FIFO is not full, asserting this signal causes data (on
data_in) to be written into the FIFO

rd_en Read Enable: If the FIFO is not empty, asserting this signal causes data
(on data_out) to be read from the FIFO
data_in Write Data: The input data bus used when writing the FIFO.

data_out output Read Data: The sequential output data bus used when reading from the
FIFO.
full Full Flag: When asserted, this combinational output signal indicates that
the FIFO is full. Write requests are ignored when the FIFO is full, initiating
a write when the FIFO is full is not destructive to the contents of the
FIFO.
almostfull Almost Full: When asserted, this combinational output signal indicates
that only one more write can be performed before the FIFO is full.
empty Empty Flag: When asserted, this combinational output signal indicates
that the FIFO is empty. Read requests are ignored when the FIFO is
empty, initiating a read while empty is not destructive to the FIFO.
almostempty Almost Empty: When asserted, this output combinational signal
indicates that only one more read can be performed before the FIFO
goes to empty.
overflow Overflow: This sequential output signal indicates that a write request
(wr_en) was rejected because the FIFO is full. Overflowing the FIFO is
not destructive to the contents of the FIFO.
underflow Underflow: This sequential output signal Indicates that the read request
(rd_en) was rejected because the FIFO is empty. Under
wr_ack Write Acknowledge: This sequential output signal indicates that a write
request (wr_en) has succeeded.

Ports table
FIFO IF
III. Verification Plan

IV. RTL Bugs Report

1.
Original design

Modified design
2.
Original design

Modified design

3.
Original design

Modified design

4.
Original design

Modified design
 5.
Original design

Modified design

V. UVM Structure and description

 ➢ UVM flow of FIFO
1. FIFO_top: root of the hierarchy, instantiate the design, interface and bind
assertions, generate the clock, set the interface into the database and finally
run the test
2. Config. Database: a shared database between all components
3. Config. Object: an object that holds configuration settings and parameters
for components.
4. FIFO_test: here we build the environment, config, and different sequences
like reset sequence and other scenarios, get the virtual interface from the
database and put into container and set it into database again, in run phase
we raise objection and run all the different sequences then drop objection
5. FIFO_sequence: core stimulus of any verification plan, made up of several
sequence items, parametrized class by type, when sequence starts it tells
the sequencer it has data to produce then the sequencer waits for the driver
to pull data by telling get_next_item(); then sequencer take the data from the
sequence to driver when finish_item means sequence is ready to be sent.
In FIFO project I have created many sequences
➢ Reset sequence
➢ Write and read randomly
➢ Write only no read
➢ Read only no write
➢ Write to the FIFO until it is full, then start reading until the FIFO is
empty
➢ Full sequence: write to the FIFO and continue writing after it is fills up
to check overflow
➢ Empty sequence: read from the FIFO and continue reading after it is
empty to check underflow
6. FIFO_seq_item: data field to communicate with the design, randomized data
is generated, constraints is added to stimulus
7. FIFO_env: build agent, scoreboard, and coverage collector and connect
analysis port of agent to scoreboard an coverage collector exports
8. FIFO_agent: build sequencer, driver, and monitor, get the config. Object from
database, create agent analysis port connect driver virtual interface and
monitor interface to cofig. Object virtual interface, connect driver port to
sequencer export and mon analysis port to agent analysis port
9. FIFO_sequencer: generate transactions as class objects and sends it to the
driver (acting as fifo)
 10. FIFO_driver: pulls the data from the sequence by get_next_item(); as
mentioned above, drive the sequence item in the run phase task using the
virtual interface
11. FIFO_monitor: capture signal information from the design ports and translate
it into seq items then broadcasts those sequence items analysis
components like scoreboard and coverage collector
12. FIFO_scoreboard: receives seq items from the monitor, check them using
reference model and compare them with design outputs, build analysis port
and export and connect them, finally report phase to report correct and
wrong transactions
13. FIFO_coverage: receives seq items from the monitor, sample the data field
for functional coverage, buil analysis port and export and connect them

VI. Design and UVM codes

1. FIFO_top

2. FIFO_interface
3. Modified design
4. FIFO_config

5. FIFO_test
6. FIFO_sequences
➢ Reset sequence

➢ Write and read sequence

➢ Write only sequence

➢ Read only sequence

➢ Write then read sequence

➢ Full sequence

➢ Empty sequence
7. FIFO_seq_item

8. FIFO_env
9. FIFO_agent

10. FIFO_sequencer

11. FIFO_driver
12. FIFO_monitor

13. FIFO_scoreboard
14. FIFO_coverage
15. Assertions
VII. Questa snippets
1. Report of the results

2. Each UVM sequence waveform

➢ Write and read sequence

➢ Write only sequence

➢ Read only sequence

➢ Write then read sequence

➢ Full sequence
 ➢ Empty sequence

3. Coverage snippets
➢ Assertions passed

➢ Cover directives
➢ Covergroups

➢ If signals toggle

➢ Branch coverage
 ➢ Statement coverage

VIII. Do File and source files

IX. Full wave of FIFO

X. FIFO Coverage report

1. Code coverage
➢ Branch coverage

➢ Statement coverage

➢ Toggle coverage
2. Assertions coverage
➢ Assertions passed

➢ Cover directives
3. Functional coverage
XI. Assertions table

Feature Assertion

Whenever the reset asserted, count and if(!f_if.rst_n) begin

pointers reset to zero reset_assert: assert final(!DUT.wr_ptr
&& !DUT.rd_ptr && !DUT.count);

Whenever count is equal to fifo_depth, FIFO is if(f_if.rst_n && (DUT.count==

full f_if.FIFO_DEPTH)) begin
full_flag_assert: assert final(f_if.full &&
!f_if.empty && !f_if.almostempty &&
!f_if.almostfull);

Whenever count is equal to fifo_depth – 1, if(f_if.rst_n && (DUT.count==

FIFO is almost full f_if.FIFO_DEPTH-1)) begin
almostfull_flag_assert: assert
final(f_if.almostfull && !f_if.empty &&
!f_if.almostempty && !f_if.full);

Whenever count is equal to zero, FIFO is if(f_if.rst_n && (DUT.count== 0)) begin
empty empty_flag_assert: assert
final(f_if.empty && !f_if.almostempty
&& !f_if.full && !f_if.almostfull);

Whenever count is equal to 1, FIFO is almost if(f_if.rst_n && (DUT.count== 1)) begin
empty almostempty_flag_assert: assert
final(f_if.almostempty && !f_if.empty
&& !f_if.full && !f_if.almostfull);

Whenever FIFO is full and wr_en is high, @(posedge f_if.clk) disable

overflow occurs iff(!f_if.rst_n) (f_if.full && f_if.wr_en) |=>
f_if.overflow;

Whenever FIFO is empty and rd_en is high, @(posedge f_if.clk) disable

underflow occurs iff(!f_if.rst_n) (f_if.empty && f_if.rd_en)
|=> f_if.underflow;

Whenever FIFO is not full and wr_en is high, @(posedge f_if.clk) disable
wr_ack is high iff(!f_if.rst_n) (f_if.wr_en && DUT.count<
f_if.FIFO_DEPTH) |=> f_if.wr_ack;
Whenever FIFO is full and wr_en is high, @(posedge f_if.clk) disable
wr_ack is zero iff(!f_if.rst_n) (f_if.wr_en && f_if.full) |=>
!f_if.wr_ack;

Whenever wr_en is high, rd_en is low and @(posedge f_if.clk) disable

FIFO is not full, write operation occurs iff(!f_if.rst_n) (f_if.wr_en && !f_if.rd_en
&& !f_if.full) |=> $past(DUT.count+
1'b1);

Whenever wr_en is low, rd_en is high and @(posedge f_if.clk) disable

FIFO is not empty, read operation occurs iff(!f_if.rst_n) (!f_if.wr_en && f_if.rd_en
&& !f_if.empty) |=> (DUT.count+ 1'b1);

Whenever wr_en is high, rd_en is high and @(posedge f_if.clk) disable

FIFO is not empty, read operation takes place iff(!f_if.rst_n) (f_if.wr_en && f_if.rd_en
&& f_if.full) |=> (DUT.count+ 1'b1);

Whenever wr_en is high, rd_en is high and @(posedge f_if.clk) disable

FIFO is empty, write operation takes place iff(!f_if.rst_n) (f_if.wr_en && f_if.rd_en
&& f_if.empty) |=> $past(DUT.count+
1'b1);

Whenever rd_en is high and FIFO is not empty, @(posedge f_if.clk) disable iff
Read pointer increases (!f_if.rst_n) (f_if.rd_en && (DUT.count !=
0)) |=> (DUT.rd_ptr ==
($past(DUT.rd_ptr) + 1) %
f_if.FIFO_DEPTH);

Whenever wr_en is high and FIFO is not full, @(posedge f_if.clk) disable iff
Write pointer increases (!f_if.rst_n) (f_if.wr_en && (DUT.count <
f_if.FIFO_DEPTH)) |=> (DUT.wr_ptr ==
($past(DUT.wr_ptr) + 1) %
f_if.FIFO_DEPTH);