TPS7A02

SBVS277C – JULY 2019 – REVISED SEPTEMBER 2022

TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response

1 Features 3 Description
• Ultra-low IQ: 25 nA (typ), even in dropout The TPS7A02 is an ultra-small, ultra-low quiescent
• Shutdown IQ: 3 nA (typ) current low-dropout linear regulator (LDO) that can
• Excellent transient response (1 mA to 50 mA) source 200 mA with excellent transient performance.
– < 10-µs settling time The TPS7A02, with an ultra-low IQ of 25 nA, is
– 100-mV undershoot designed specifically for applications where very-low
• Packages: quiescent current is a critical parameter. This device
– 1.0-mm × 1.0-mm X2SON maintains low IQ consumption even in dropout mode
– SOT23-5 to further increase battery life. When in shutdown or
– 0.64-mm × 0.64-mm DSBGA disabled mode, the device consumes ultra-low,
• Input voltage range: 1.5 V to 6.0 V 3-nA IQ that helps increase the shelf life of the battery.
• Output voltage range: 0.8 V to 5.0 V (fixed) The TPS7A02 has an output range of 0.8 V to 5.0
• Output accuracy: 1.5% over temperature V available in 50-mV steps to support the lower core
• Smart enable pulldown voltages of modern microcontrollers (MCUs).
• Very low dropout:
– 270 mV (max) at 200 mA (VOUT = 3.3 V) The TPS7A02 features a smart enable circuit with an
• Stable with a 1-µF or larger capacitor internally controlled pulldown resistor that keeps the
LDO disabled even when the EN pin is left floating
2 Applications and helps minimize the external components used to
• Wearables electronics pulldown the EN pin. This circuit also helps minimize
• Thermostats, smoke and heat detectors the current drawn through the external pulldown
• Gas, heat, and water meters circuit when the device is enabled.
• Blood glucose monitors and pulse oximeters The TPS7A02 is fully specified for TJ = –40°C to
• Residential circuit breakers and fault indicators +125°C operation.
• Building security and video surveillance devices
• EPOS card readers Package Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DQN (X2SON, 4) 1.00 mm × 1.00 mm
TPS7A02 YCH (DSBGA, 4) 0.64 mm × 0.64 mm
DBV (SOT-23, 5) 2.90 mm × 1.60 mm

(1) For all available packages, see the package option

addendum at the end of the data sheet.

400 250 102

350 200
100
AC-Coupled Output Voltage (mV)

300 150
250 100 98
Current Efficiency (%)
Output Current (mA)

200 50 96
150 0
94
100 -50
50 -100 92
0 -150
90
-50 -200
-100 -250 88
VOUT TJ
-150 IOUT -300 86 -55°C 0°C 85°C 140°C
-200 -350 -40°C 25°C 125°C
-200 -100 0 100 200 300 400 500 600 700 800 84
Time (µs) 0.001 0.01 0.1 1 10 100
Output Current (mA)
Load Transient Response (VIN = VOUT + 1 V, COUT = Curr

1 µF, IOUT = 1 mA to 50 mA in 1 µs) Ground Current Efficiency vs Output Current

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................19
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................22
3 Description.......................................................................1 8 Application and Implementation.................................. 23
4 Revision History.............................................................. 2 8.1 Application Information............................................. 23
5 Pin Configuration and Functions...................................3 8.2 Typical Application.................................................... 26
6 Specifications.................................................................. 4 8.3 Power Supply Recommendations.............................27
6.1 Absolute Maximum Ratings........................................ 4 8.4 Layout....................................................................... 27
6.2 ESD Ratings............................................................... 4 9 Device and Documentation Support............................29
6.3 Recommended Operating Conditions.........................5 9.1 Device Support......................................................... 29
6.4 Thermal Information....................................................5 9.2 Receiving Notification of Documentation Updates....29
6.5 Electrical Characteristics.............................................6 9.3 Support Resources................................................... 29
6.6 Switching Characteristics............................................7 9.4 Trademarks............................................................... 29
6.7 Typical Characteristics................................................ 8 9.5 Electrostatic Discharge Caution................................29
7 Detailed Description......................................................18 9.6 Glossary....................................................................29
7.1 Overview................................................................... 18 10 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 18 Information.................................................................... 29

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2020) to Revision C (September 2022) Page

• Changed YCH (DGBGA) package from preview to production data.................................................................. 1

Changes from Revision A (December 2019) to Revision B (March 2020) Page

• Changed DBV (SOT23-5) package from preview to production data.................................................................1

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5 Pin Configuration and Functions

OUT 1 4 IN
IN 1 5 OUT

GND 2

Thermal Pad EN 3 4 NC
GND 2 3 EN

Not to scale
Not to scale
Figure 5-1. DQN Package, 1-mm × 1-mm, 4-Pin Figure 5-2. DBV Package, 5-Pin SOT-23 (Top View)
X2SON (Top View)

Table 5-1. Pin Functions: DQN, DBV

PIN
NAME DQN DBV I/O(1) DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
EN 3 3 Input or floating this pin disables the device. This pin features an internal pulldown resistor,
which is disconnected when EN is driven high externally and the device has started up.
GND 2 2 — Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger ceramic capacitor from IN to ground; see the
IN 4 1 Input
Recommended Operating Conditions table. Place the input capacitor as close to the
input of the device as possible.
NC — 4 — No connect pin. This pin is not internally connected. Connect to ground or leave floating.
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to
ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor
OUT 1 5 Output
from OUT to ground. Place the output capacitor as close to output of the device as
possible; see the Recommended Operating Conditions table.
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
Thermal pad –– —
connect to ground.

(1) NC = No internal connection.

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1 2 1 2

A IN OUT B EN GND

B EN GND A IN OUT

Not to scale Not to scale

Figure 5-3. YCH Package, 4-Pin DSBGA, 0.35-mm Figure 5-4. YCH Package, 4-Pin DSBGA, 0.35-mm
Pitch (Top View) Pitch (Bottom View)

Table 5-2. Pin Functions: YCH

PIN
YCH NAME I/O DESCRIPTION
Input pin. For best transient response and to minimize input impedance, use the recommended
A1 IN Input value or larger ceramic capacitor from IN to ground; see the Recommended Operating
Conditions table. Place the input capacitor as close to input of the device as possible.
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground
for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT
A2 OUT Output
to ground. Place the output capacitor as close to output of the device as possible; see the
Recommended Operating Conditions table.
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low or floating
B1 EN Input this pin disables the device. This pin features an internal pulldown resistor, which is disconnected
when EN is driven high externally and the device has started up.
B2 GND — Ground pin. This pin must be connected to ground and the thermal pad.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN –0.3 6.5
Voltage VEN –0.3 6.5 V
VOUT –0.3 VIN + 0.3 or 5.5(2)
Current Maximum output Internally limited A
Operating junction, TJ –40 150
Temperature °C
Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 1.5 6.0 V
VEN Enable voltage 0 6.0 V
VOUT Output voltage 0.8 5.0 V
IOUT Output current 0 200 mA
CIN Input capacitor 1 µF
COUT Output capacitor(1) (2) 1 1 22 µF
FEN EN toggle frequency 10 kHz
TJ Operating junction temperature –40 125 °C

(1) Effective output capacitance of 0.5 µF minimum required for stability.

(2) 22 µF is the maximum derated capacitance that can be used for stability.

6.4 Thermal Information

TPS7A02
THERMAL METRIC(1) DQN (X2SON) DBV (SOT-23-5) YCH (DSBGA) UNIT
4 PINS 5 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 179.1 181.9 201.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 137.6 53.0 2.3 °C/W
RθJB Junction-to-board thermal resistance 116.3 88.1 67.3 °C/W
ψJT Junction-to-top characterization parameter 6.1 27.1 1.1 °C/W
ψJB Junction-to-board characterization parameter 116.3 52.7 67.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 112.3 N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C, VOUT ≥ 1.5 V, 1 µA(3) ≤ IOUT ≤ 1 mA –1 1 %
Nominal accuracy
TJ = 25°C; VOUT < 1.5 V –15 15 mV

Accuracy over VOUT ≥ 1.5 V –1.5 1.5 %

TJ = –40°C to +125°C
temperature VOUT < 1.5 V –20 20 mV
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V(1)
ΔVOUT(ΔVIN) Line regulation TJ = –40°C to +125°C 5 mV

1 mA ≤ IOUT ≤ 200 mA, TJ = –40°C to +85°C 20 38

ΔVOUT(ΔIOUT) Load regulation(2) VIN = VOUT(nom) + 0.5 V(1) mV
TJ = –40°C to +125°C 50

TJ = 25°C 25 46
IGND Ground current IOUT = 0 mA nA
TJ = –40°C to +85°C 60
5 µA ≤ IOUT < 1 mA 1
Ground current vs
IGND/IOUT 1 mA ≤ IOUT < 100 mA TJ = 25°C 0.25 %
load current
IOUT ≥ 100 mA 0.15
Ground current in
IGND(DO) IOUT = 0 mA, VIN = 95% x VOUT (NOM) TJ = 25°C 25 nA
dropout(3)
ISHDN Shutdown current VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C 3 10 nA
VOUT < 2.5V,
VIN = VOUT(nom) + 240 450 750 mA
VDO(max) + 1.0 V
ICL Output current limit VOUT = 90% × VOUT(nom)
VOUT ≥ 2.5V,
VIN = VOUT(nom) + 240 450 750 mA
VDO(max) + 0.5 V
Short-circuit current
ISC VOUT = 0 V 65 mA
limit
0.8 V ≤ VOUT < 1.0 V 1050
1.0 V ≤ VOUT < 1.2 V 790
1.2 V ≤ VOUT < 1.5 V 650
TJ = –40°C to +85°C 1.5 V ≤ VOUT < 1.8 V 490
1.8 V ≤ VOUT < 2.5 V 400
2.5 V ≤ VOUT < 3.3 V 310
3.3 V ≤ VOUT ≤ 5.0 V 270
VDO Dropout voltage(4) mV
0.8 V ≤ VOUT < 1.0 V 1100
1.0 V ≤ VOUT < 1.2 V 850
1.2 V ≤ VOUT < 1.5 V 700
TJ = –40°C to +125°C 1.5 V ≤ VOUT < 1.8 V 560
1.8 V ≤ VOUT < 2.5 V 450
2.5 V ≤ VOUT < 3.3 V 360
3.3 V ≤ VOUT ≤ 5.0 V 310
Power-supply
PSRR f = 1 kHz, IOUT = 30 mA 55 dB
rejection ratio
Output voltage
VN BW = 10 Hz to 100 kHz, VOUT = 0.8 V, IOUT = 30 mA 130 µVRMS
noise
VIN rising 1.23 1.3 1.47
VUVLO UVLO threshold V
VIN falling 1.0 1.12 1.41
VUVLO(HYST) UVLO hysteresis VIN hysteresis 180 mV

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6.5 Electrical Characteristics (continued)

Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN pin logic high
VEN(HI) 1.1 V
voltage
EN pin logic low
VEN(LOW) 0.3 V
voltage
EN pin leakage
IEN VEN = VIN = 6.0 V 10 nA
current
Smart enable
REN(PULLDOWN) VEN = 0.3 V 500 KΩ
pulldown resistor
RPULLDOWN Pulldown resistor VIN = 3.3 V, device disabled 60 Ω
Thermal shutdown
TSD(shutdown) Shutdown, temperature increasing 170
temperature
°C
Thermal shutdown
TSD(reset) Reset, temperature decreasing 145
reset temperature

(1) VIN = 2.0 V for VOUT ≤ 1.5 V.

(2) Load Regulation is normalized to the output voltage at IOUT = 1 mA.
(3) Specified by design
(4) Dropout is measured by ramping VIN down until VOUT = VOUT (nom) x 95%, with IOUT = 200 mA.

6.6 Switching Characteristics

Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.8V ≤ VOUT ≤ 1.5 V 500 800
tSTR Start-up time From EN assertion to VOUT = 90% × VOUT(nom) 1.5V < VOUT ≤ 3.0 V 750 1200 µs
3.0V < VOUT ≤ 5.0 V 1200 1600

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6.7 Typical Characteristics

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

60 700
TJ 650 TJ
-55°C 0°C 85°C 600 125°C
50 -40°C 25°C 140°C
550

Quiescent Current (nA)

Quiescent Current (nA)

500
40 450
400
30 350
300
250
20
200
150
10 100
50
0 0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Input Voltage (V) Input Voltage (V)

IOUT = 0 mA, VEN = VIN IOUT = 0 mA, VEN = VIN

Figure 6-1. IQ vs VIN and Temperature Figure 6-2. IQ vs VIN and Temperature

500000 500
TJ TJ
-55°C 25°C 140°C 450 -55°C 0°C 85°C 140°C
100000
-40°C 85°C 400 -40°C 25°C 125°C
0°C 125°C
Ground Current (PA)
Ground Current (nA)

350
10000
300
250
1000 200
150
100 100
50

10 0
0.001 0.01 0.1 1 10 100200 0 20 40 60 80 100 120 140 160 180 200
Output Current (mA) Output Current (mA)

VOUT = 1.8 V, VIN = VEN = 2.3 V VOUT = 1.8 V, VIN = VEN = 2.3 V

Figure 6-3. IQ vs IOUT and Temperature up to 200 mA Figure 6-4. IQ vs IOUT and Temperature Up to 200 mA

5000 25
TJ TJ
-55°C 0°C 85°C 140°C -55°C 0°C 85°C 140°C
4000 -40°C 25°C 125°C 20 -40°C 25°C 125°C
Ground Current (nA)

Ground Current (PA)

3000 15

2000 10

1000 5

0 0
0 0.2 0.4 0.6 0.8 1 1 3 5 7 9 10
Output Current (mA) Output Current (mA)
VOUT = 1.8 V, VIN = VEN = 2.3 V VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 6-5. IQ vs IOUT and Temperature Up to 1 mA Figure 6-6. IQ vs IOUT and Temperature for 1 mA to 10 mA

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

60 300
TJ TJ
-55°C 0°C 85°C 125°C
50 -40°C 25°C 250 140°C

Quiescent Current (nA)

Quiescent Current (nA)

40 200

30 150

20 100

10 50

0 0
1.5 2 2.5 3 3.5 4 4.5 5 1.5 2 2.5 3 3.5 4 4.5 5
Input Voltage (V) Input Voltage (V)

VOUT = 5.0 V, VEN = VIN VOUT = 5.0 V, VEN = VIN

Figure 6-7. IQ in Dropout vs VIN and Temperature Figure 6-8. IQ in Dropout vs VIN and Temperature

4000 6
TJ TJ
-55°C 0°C 85°C 140°C -55°C 0°C
-40°C 25°C 125°C 5 -40°C 25°C
3000
Quiescent Current (nA)

Quiescent Current (nA)

2000 3

2
1000

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0
Input Voltage (V) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Input Voltage (V)
IOUT = 0 mA, VEN = 1.1 V
VEN = 0 V
Figure 6-9. IQ vs VIN and Temperature
Figure 6-10. ISHDN vs VIN and Temperature
400 400 250
TJ 350 200
350 85°C 140°C
AC-Coupled Output Voltage (mV)

125°C 300 150

300 250 100
Quiescent Current (nA)

Output Current (mA)

200 50
250
150 0
200 100 -50
50 -100
150
0 -150
100 -50 -200
-100 -250
50 VOUT
-150 IOUT -300
0 -200 -350
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 -200 -100 0 100 200 300 400 500 600 700 800
Input Voltage (V) Time (µs)

VEN = 0 V VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs

Figure 6-11. ISHDN vs VIN and Temperature Figure 6-12. IOUT Transient From 1 mA to 50 mA

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

400 250 400 250

350 200 350 200

AC-Coupled Output Voltage (mV)

AC-Coupled Output Voltage (mV)

300 150 300 150

250 100 250 100

Output Current (mA)

Output Current (mA)
200 50 200 50
150 0 150 0
100 -50 100 -50
50 -100 50 -100

0 -150 0 -150

-50 -200 -50 -200

-100 -250
-100 -250 VOUT
VOUT -150
-150 IOUT -300
IOUT -300 -200 -350
-200 -350 -200 -100 0 100 200 300 400 500 600 700 800
-200 -100 0 100 200 300 400 500 600 700 800 Time (µs)
Time (µs) Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-14. IOUT Transient From 1 mA to 200 mA
Figure 6-13. IOUT Transient From 1 mA to 100 mA
280 100 200 100
240 75 AC-Coupled Output Voltage (mV) 175 75
AC-Coupled Output Voltage (mV)

200 50 150 50

160 25 125 25

Output Current (mA)

Output Current (mA)

100 0
120 0
75 -25
80 -25
50 -50
40 -50
25 -75
0 -75
0 -100
-40 -100
-25 -125
-80 -125 -50 -150
-120 -150 VOUT
-75 IOUT -175
VOUT
-160 IOUT -175 -100 -200
-200 -200 80 90 100 110 120 130 140 150 160 170 180
-60 -40 -20 0 20 40 60 80 100 120 140 Time (ms) Load
Time (µs) Load VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-16. IOUT Transient From 50 mA to 0 mA
Figure 6-15. IOUT Transient From 0 mA to 50 mA
420 200 200 200
360 150 175 150
)AC-Coupled Output Voltage (mV)

AC-Coupled Output Voltage (mV)

300 100 150 100

240 50 125 50 Output Current (mA)
Output Current (mA

180 0 100 0
120 -50 75 -50
60 -100 50 -100
0 -150 25 -150
-60 -200 0 -200
-120 -250 -25 -250
-180 -300 -50 -300
IOUT VOUT
-240 VOUT -350 -75 IOUT -350
-300 -400 -100 -400
-80 -60 -40 -20 0 20 40 60 80 100 120 -10 0 10 20 30 40 50 60 70 80 90
Time (µs) Load
Time (ms) Load

VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-17. IOUT Transient From 0 mA to 100 mA Figure 6-18. IOUT Transient From 100 mA to 0 mA

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
420 300 400 400
360 250 350 300
AC-Coupled Output Voltage (mV)

)AC-Coupled Output Voltage (mV)

300 200 300 200
240 150
250 100

Output Current (mA)

Output Current (mA

180 100
200 0
120 50
150 -100
60 0
100 -200
0 -50
-60 -100
50 -300
-120 -150 0 -400
-180 -200 -50 -500
VOUT
-240 IOUT -250
-100 -600
VOUT
-300 -300 -150
-30 -20 -10 0 10 20 30 40 50 60 70
IOUT -700
Time (µs) -200 -800
Load -10 0 10 20 30 40 50 60 70 80
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs Time (ms)

Figure 6-19. IOUT Transient From 0 mA to 200 mA VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-20. IOUT Transient From 200 mA to 0 mA
150 6 400 10
350 7.5
125 4.5
AC-Coupled Output Voltage (mV)

AC-Coupled Output Voltage (mV)

300 5
100 3 250 2.5
Input Voltage (V)

Input Voltage (V)

200 0
75 1.5
150 -2.5
50 0 100 -5
50 -7.5
25 -1.5
0 -10
0 -3 -50 -12.5
-100 -15
-25 VOUT -4.5 VOUT
VIN -150 VIN -17.5
-50 -6 -200 -20
-40 0 40 80 120 160 200 240 280 320 360 -200 -100 0 100 200 300 400 500 600 700
Time (µs) Line
Time (µs) Line

VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs VOUT = 1.8 V, IOUT = 1 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 6-21. VIN Transient From 2.8 V to 4.8 V Figure 6-22. VIN Transient From 2.8 V to 6.0 V
150 10 5 5

125 7.5 4.5 4.5

AC-Coupled Output Voltage (mV)

4 4
100 5
3.5 3.5
Output Voltage (V)
Input Voltage (V)

Input Voltage (V)

75 2.5 3 3
50 0 2.5 2.5

25 -2.5 2 2
1.5 1.5
0 -5
1 1
-25 VOUT -7.5 0.5 VOUT 0.5
VIN VIN
-50 -10 0 0
-40 -20 0 20 40 60 80 100 120 140 160 -40 0 40 80 120 160 200 240 280 320 360
Time (µs) Line
Time (µs) Drop

VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 6-23. VIN Transient From 2.8 V to 6.0 V Figure 6-24. VIN Transient From 1.5 V to 4.5 V

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

10 0.3
TJ TJ
8 -55°C 0°C 85°C 140°C -55°C 0°C 85°C 140°C
Change in Output Voltage (mV)

-40°C 25°C 125°C -40°C 25°C 125°C

Output Voltage Accuracy (%)

6
0.1
4
2
0 -0.1

-2
-4
-0.3
-6
-8
-10 -0.5
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Input Voltage (V) Input Voltage (V)

VOUT = 1.8 V, IOUT = 1 mA VOUT = 1.8 V, IOUT = 1 mA

Figure 6-25. Line Regulation vs VIN and Temperature Figure 6-26. Output Accuracy vs VIN and Temperature
0.3 20
VOUT % TJ
15 -55°C 0°C 85°C 140°C
Change in Output Voltage (mV)
-40°C 25°C 125°C
Output Voltage Accuracy %)

0.1
10

5
-0.1
0

-0.3 -5

-10

-0.5
-15
-60 -40 -20 0 20 40 60 80 100 120 140150
5 5.2 5.4 5.6 5.8 6
Temperature (qC)
Input Voltage (V)
VOUT = 1.8 V, IOUT = 1 mA VOUT = 5.0 V, IOUT = 1 mA
Figure 6-27. Output Accuracy vs Temperature Figure 6-28. Line Regulation vs VIN and Temperature
0.5 0.5
TJ VOUT %
-55°C 0°C 85°C 140°C
-40°C 25°C 125°C
Output Voltage Accuracy (%)

Output Voltage Accuracy %)

0.3
0.3

0.1

0.1
-0.1

-0.1
-0.3

-0.3 -0.5
5 5.2 5.4 5.6 5.8 6 -60 -40 -20 0 20 40 60 80 100 120 140150
Input Voltage (V) Temperature (qC)

VOUT = 5.0 V, IOUT = 1 mA VOUT = 5.0 V, IOUT = 1 mA

Figure 6-29. Output Accuracy vs VIN and Temperature Figure 6-30. Output Accuracy vs Temperature

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

10 550
TJ TJ
500
-55°C 0°C 85°C 140°C -55°C 0°C 85°C 140°C
Change in Output Voltage (mV)

5 -40°C 25°C 125°C 450 -40°C 25°C 125°C

Dropout Voltage (mV)

400
0
350
300
-5
250

-10 200
150
-15 100
50
-20 0
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
Output Current (mA) Output Current (mA)
VOUT = 1.8 V VOUT = 1.8 V
Figure 6-31. Load Regulation vs VIN and Temperature Figure 6-32. Dropout vs IOUT and Temperature
300 600
280 TJ TJ
260 -55°C 0°C 85°C 140°C -55°C 0°C 85°C 140°C
240 -40°C 25°C 125°C -40°C 25°C 125°C
220
Dropout Voltage (mV)

Dropout Voltage (mV)

200
400
180
160
140
120
100
80 200
60
40
20
0
0 20 40 60 80 100 120 140 160 180 200
Output Current (mA) 0
2 2.5 3 3.5 4 4.5 5
VOUT = 5.0 V Input Voltage (V)

Figure 6-33. Dropout vs IOUT and Temperature IOUT = 200 mA

Figure 6-34. Dropout vs VIN and Temperature
300 1.2
TJ TJ
-55°C 0°C 85°C 140°C -55°C 0°C 85°C 140°C
250 -40°C 25°C 125°C 1 -40°C 25°C 125°C
Dropout Voltage (mV)

Output Voltage (V)

200 0.8

150 0.6

100 0.4

50 0.2

0 0
1.5 2 2.5 3 3.5 4 4.5 5 0 50 100 150 200 250 300 350 400 450 500 550 600
Input Voltage (V) Output Current (mA)

IOUT = 50 mA VOUT = 0.8 V

Figure 6-35. Dropout vs VIN and Temperature Figure 6-36. Foldback Current Limit vs IOUT and Temperature

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

2.5 0.9
TJ VEN(LOW)
-55°C 0°C 85°C VEN(HIGH)
-40°C 25°C 125°C 0.85
2

Enable Voltage (V)

Output Voltage (V)

0.8
1.5
0.75

1
0.7

0.5 0.65

0 0.6
0 50 100 150 200 250 300 350 400 450 500 550 600 -60 -40 -20 0 20 40 60 80 100 120 140150
Output Current (mA) Temperature (qC)

VOUT = 1.8 V VOUT = 0.8 V

Figure 6-37. Foldback Current Limit vs IOUT and Temperature Figure 6-38. EN High and Low Threshold vs Temperature

1.1 1.5
VEN(LOW) VUVLO(HIGH)
1.05 VEN(HIGH) 1.45 VUVLO(LOW)

1 1.4
Enable Voltage (V)

UVLO Voltage (V)

0.95
1.35
0.9
1.3
0.85
1.25
0.8
1.2
0.75
1.15
0.7
-60 -40 -20 0 20 40 60 80 100 120 140150 1.1
Temperature (qC) -60 -40 -20 0 20 40 60 80 100 120 140150
VOUT = 5.0 V Temperature (qC)
VOUT = 5.0 V, IOUT = 1 mA
Figure 6-39. EN High and Low Threshold vs Temperature
Figure 6-40. UVLO Rising and Falling Threshold vs Temperature
70 580
VOUT VOUT
570 0.8V 1.8V 5.0V
0.8V 1.8V 5.0V
65 560
Pulldown Resistor (ohm)
Pulldown Resistor (ohm)

550
60 540
530
55
520
510
50
500
490
45
480
-60 -40 -20 0 20 40 60 80 100 120 140 160
40 Temperature (qC)
-60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC)
Figure 6-42. Smart Enable Pulldown Resistor vs Temperature
and VOUT
Figure 6-41. Pulldown Resistor vs Temperature and VOUT

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

100 100
90 90

Power Supply Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

80 80

70 70

60 60

50 50

40 40

30 30

20 20 VIN
IOUT
0 mA 10 mA 100 mA 10 2.3 V 3.8 V 6.0 V
10
1 mA 20 mA 200 mA 2.8 V 4.8 V
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz) D001

VIN = 2.8 V, VOUT = 1.8 V, COUT = 1 µF VOUT = 1.8 V, IOUT = 20 mA, COUT = 1 µF
Figure 6-43. PSRR vs Frequency and IOUT Figure 6-44. PSRR vs Frequency and VIN
100 100
90 90
Power Supply Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

80 80
70 70
60 60
50 50
40 40
30 30
20 VIN 20 VIN
10 2.3 V 3.8 V 6.0 V 10 2.8 V 4.8 V
2.8 V 4.8 V 3.8 V 6.0 V
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D001
Frequency (Hz) D001

VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-45. PSRR vs Frequency and VIN Figure 6-46. PSRR vs Frequency and VIN
100 50
VOUT 30 IOUT
50
1.8 V, RMS Noise = 269.5 PV RMS 20 100 PA, RMS Noise = 117.5 PV RMS
Output Voltage Noise (PV —Hz)

Output Voltage Noise (PV —Hz)

5.0 V, RMS Noise = 710 PV RMS 1 mA, RMS Noise = 269.5 PV RMS
20 10
10
5
5 3
2
2
1
1
0.5
0.5
0.3
0.2 0.2

0.1 0.1
0.05 0.05
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

VIN = VOUT+ 1.0 V, IOUT = 1 mA, COUT = 1 µF VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF
Figure 6-47. Output Noise vs Frequency and VOUT Figure 6-48. Output Noise vs Frequency and IOUT

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

50 5
30 COUT VOUT
20 1 PF, RMS Noise = 269.5 PVRMS 4 VEN = VIN
Output Voltage Noise (PV —Hz)

22 PF, RMS Noise = 301.1 PVRMS

10
3
5

Voltage (V)
3 2
2
1 1

0.5
0
0.3
0.2
-1
0.1
-2
0.05
-450 -300 -150 0 150 300 450 600 750 900 1050
10 100 1k 10k 100k 1M 10M
Time (ms)
Frequency (Hz) Star

VOUT = 1.8 V, VIN = 2.8 V, IOUT = 1 mA VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF

Figure 6-49. Output Noise vs Frequency and COUT Figure 6-50. Startup With VEN = VIN

5 6
VOUT VOUT
4 VEN 5 VEN
VIN VIN

3 4
Voltage (V)

Voltage (V)

2 3

1 2

0 1

-1 0

-2 -1
-450 -300 -150 0 150 300 450 600 750 900 1050 -600 -400 -200 0 200 400 600 800 1000 1200 1400
Time (ms) Star
Time (ms) Star

VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-51. Startup With VEN Before VIN Figure 6-52. Startup With VEN After VIN
5.5 10
5 VOUT VOUT
9
VEN VEN
4.5 VIN 8 VIN
4 7
3.5
6
Voltage (V)

Voltage (V)

3
5
2.5
4
2
3
1.5
1 2

0.5 1
0 0
-0.5 -1
-450 -300 -150 0 150 300 450 600 750 900 1050 -800 -400 0 400 800 1200 1600 2000 2400 2800 3200
Time (Ps) Star
Time (ms) Star

VOUT = 1.8 V, IOUT = 0 mA, COUT = 1 µF VOUT = 5.0 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-53. Startup With VEN After VIN Figure 6-54. Startup With VEN After VIN

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6.7 Typical Characteristics (continued)

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
9 50 9 400
VIN VIN
8 VEN 40 8 VEN 300
7 VOUT 30 VOUT
7 200
IIN IIN
6 20 6 100

Current (mA)

Current (mA)
Voltage (V)

5 10

Voltage (V)
5 0
4 0 4 -100
3 -10 3 -200
2 -20 2 -300
1 -30
1 -400
0 -40
0 -500
-1 -50
-400 -200 0 200 400 600 800 1000 1200 -1 -600
Time (Ps) -400 -200 0 200 400 600 800 1000 1200
Star Time (Ps)
VOUT = 1.8 V, IOUT = 0 mA VOUT = 1.8 V, IOUT = 0 mA
Figure 6-55. Startup Inrush Current With COUT= 1 µF Figure 6-56. Startup Inrush Current With COUT= 22 µF

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7 Detailed Description
7.1 Overview
The TPS7A02 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the device ideal for most battery-powered applications.
This low-dropout linear regulator (LDO) offers active discharge, foldback current limit, shutdown, and thermal
protection capability.
7.2 Functional Block Diagram

Current
IN OUT
Limit
1.2-V
Bandgap +

Active Discharge
± P-Version Only

±
Error
Amp
+

UVLO

Internal
Thermal Controller
Shutdown

EN
Smart
Enable
Resistor

GND

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7.3 Feature Description

7.3.1 Excellent Transient Response
The TPS7A02 includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
output response time to transients.
Adaptive biasing increases the IQ as the DC load current increases, extending the bandwidth of the loop. The
response time across the output voltage range is constant because a buffered reference topology is used, which
keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensures excellent transient
response while maintaining low IQ in steady-state conditions.
7.3.2 Active Discharge (P-Version Only)
The device has an internal pulldown MOSFET that connects a RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by
the undervoltage lockout (UVLO).
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs. The TPS7A02 helps to reduce the battery discharge by detecting when the device is operating in
dropout conditions and maintaining a low IQ.
7.3.4 Smart Enable
The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input
is greater than VEN(HI) and disabled when the enable input voltage is less than VEN(LOW). If independent control
of the output voltage is not needed, connect EN to IN.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is
driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable
internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.

VDO
RDS(ON) =
IRATED (1)

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7.3.6 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall-foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.5 V.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 7-1 shows a diagram of the foldback current limit.

VOUT

Brickwall
VOUT(NOM)

VFOLDBACK

Foldback

0V IOUT

0 mA ISC IRATED ICL

Figure 7-1. Foldback Current Limit

7.3.7 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.8 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).

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The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN VEN IOUT TJ
Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Disabled
(any true condition VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown)
disables the device)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start-up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum
EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is
turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt tCt tDt tEt tGt tHt

B F

Figure 8-1. Load Transient Waveform

During transitions from a light load to a heavy load, the:

• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
• Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)

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During transitions from a heavy load to a light load, the:

• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
• Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before the input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure
8-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
• Region A: The device does not start until the input reaches the UVLO rising threshold.
• Region B: Normal operation, regulating device.
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
• Region D: Normal operation, regulating device.
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

VIN

VOUT C
tAt tBt tDt tEt tFt tGt

Figure 8-2. Typical UVLO Operation

8.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:

PD = (VIN – VOUT) × IOUT (2)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A02 allows for maximum efficiency across a wide range of output voltages.

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The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.

TJ = TA + (RθJA × PD) (3)

IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4)

Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.

ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD (5)

where:
• PD is the power dissipated as explained in Equation 2
• TT is the temperature at the center-top of the device package, and
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be
separated into the following parts:
• Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
• The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN –
VOUT increases the output current must decrease.
• The rated input voltage range governs both the minimum and maximum of VIN – VOUT.

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Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Thermal Information table.

Output current limited by Rated output

Output current limited by thermals
dropout current
Output Current (A)

Limited by Limited by
minimum VIN maximum VIN

VIN ± VOUT (V)

Figure 8-3. Region Description of Continuous Operation Regime

8.2 Typical Application

IN OUT
CIN
COUT
Device
VBAT Load
EN GND

Figure 8-4. Operation From a Battery Input Supply

8.2.1 Design Requirements

Table 8-1. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input voltage 1.8 V to 3.0 V (two 1.5-V batteries)
Output voltage 1.0 V, ±1%
Input current 200 mA, maximum
Output load 10-mA DC
Maximum ambient temperature 70°C

8.2.2 Detailed Design Procedure

For this design example, the 1.0-V, fixed-version TPS7A0210 is selected. A dual AA Alkaline battery was used,
thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the battery. A 1.0-µF
output capacitor is also recommended for excellent load transient response. The dropout voltage (VDO) is kept
within the TPS7A02 dropout voltage specification for the 1.0-V output voltage option to keep the device in
regulation under all load and temperature conditions for this design. Use the recommend 1-µF input and output
capacitor because the input source has a high equivalent series resistor (ESR) of 600 mΩ (typ). The very small
ground current consumed by the regulator maintains a high current efficiency as compared to the load current
consumed by the system, as shown in Figure 8-5 which allows for long battery life. Equation 6 can be used to
calculate the current efficiency (Iη) of this system.

Iη(%) = IOUT / (IOUT + IQ) × 100 (6)

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8.2.3 Application Curve

102

100

98

Current Efficiency (%)

96

94

92

90

88
TJ
86 -55°C 0°C 85°C 140°C
-40°C 25°C 125°C
84
0.001 0.01 0.1 1 10 100
Output Current (mA) Curr

Figure 8-5. Current Efficiency vs IOUT and Temperature

8.3 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.5 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI highly recommends using a 1-µF
or greater input capacitor to reduce the impedance of the input supply, especially during transients.
8.4 Layout
8.4.1 Layout Guidelines
• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
8.4.2 Layout Examples
VOUT VIN
1 4

COUT
CIN

2 3

GND PLANE

Represents via used for

application specific connections

Figure 8-6. Layout Example for the DQN Package

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VIN VOUT

1 5

CIN 2 COUT

3 4

GND PLANE

Represents via used for

application specific connections

Figure 8-7. Layout Example for the DBV Package

IN OUT
A1 A2

CIN COUT
Via

B1 B2
EN GND

Figure 8-8. Layout Example for the YCH Package

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Device Nomenclature
Table 9-1. Device Nomenclature(1) (2)
PRODUCT VOUT
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A02 family actively discharge
TPS7A02 xx(x)Pyyyz
the output when the device is disabled.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS7A0210PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GH Samples

TPS7A0212PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21GF Samples

TPS7A0212PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 A Samples

TPS7A0215DQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OS Samples

TPS7A0215PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21KF Samples

TPS7A0215PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F3 Samples

TPS7A02175PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 S Samples

TPS7A02185DQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OR Samples

TPS7A02185PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 HO Samples

TPS7A0218DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2CDT Samples

TPS7A0218PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21LF Samples

TPS7A0218PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F4 Samples

TPS7A0218PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 B Samples

TPS7A0220PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 22MT Samples

TPS7A0220PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F5 Samples

TPS7A0222DQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 IN Samples

TPS7A0222PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21HF Samples

TPS7A0222PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GI Samples

TPS7A0223PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21IF Samples

TPS7A0223PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F6 Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS7A0225PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21DF Samples

TPS7A0225PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F7 Samples

TPS7A0225PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 C Samples

TPS7A0228DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 29PT Samples

TPS7A0228DQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 IE Samples

TPS7A0228PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21EF Samples

TPS7A0228PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F8 Samples

TPS7A0228PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 D Samples

TPS7A0230PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21MF Samples

TPS7A0230PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 F9 Samples

TPS7A0230PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 F Samples

TPS7A0231PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GJ Samples

TPS7A0233DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 29QT Samples

TPS7A0233DQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 IF Samples

TPS7A0233PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 21FF Samples

TPS7A0233PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 FA Samples

TPS7A0233PYCHR ACTIVE DSBGA YCH 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 G Samples

TPS7A0236PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (21FF, 21JF) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

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OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0210PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0210PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0212PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0212PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0212PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0215DQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0215PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0215PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0215PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0215PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A02175PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A02185DQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A02185PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A02185PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0218DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0218PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

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Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0218PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0218PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0218PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0218PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0220PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0220PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0220PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0222DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0222PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0222PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0222PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0223PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0223PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0223PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0225PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0225PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0225PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0225PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0228DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0228DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0228DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0228PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0228PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0228PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0228PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0230PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0230PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0230PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0230PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0230PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0231PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0231PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0233DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0233DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0233PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0233PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A0233PDQNR X2SON DQN 4 3000 178.0 8.4 1.13 1.13 0.53 4.0 8.0 Q2
TPS7A0233PYCHR DSBGA YCH 4 12000 180.0 8.4 0.72 0.72 0.42 2.0 8.0 Q1
TPS7A0236PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A0236PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A0210PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0210PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0212PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0212PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0212PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0215DQNR X2SON DQN 4 3000 210.0 185.0 35.0
TPS7A0215PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0215PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0215PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0215PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A02175PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A02185DQNR X2SON DQN 4 3000 210.0 185.0 35.0
TPS7A02185PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A02185PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0218DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0218PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0218PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0218PDQNR X2SON DQN 4 3000 184.0 184.0 19.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A0218PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0218PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0220PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0220PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0220PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0222DQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0222PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0222PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0222PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0223PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0223PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0223PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0225PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0225PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0225PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0225PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0228DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0228DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0228DQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0228PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0228PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0228PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0228PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0230PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0230PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0230PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0230PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0230PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0231PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0231PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0233DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0233DQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0233PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0233PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TPS7A0233PDQNR X2SON DQN 4 3000 205.0 200.0 33.0
TPS7A0233PYCHR DSBGA YCH 4 12000 182.0 182.0 20.0
TPS7A0236PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A0236PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0

Pack Materials-Page 4
 PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

B 1.05 A
0.95

1.05
PIN 1 0.95
INDEX AREA

C
0.4 MAX

SEATING PLANE
0.08

NOTE 6

0.48+0.12
-0.1
0.05
(0.05) TYP 0.00

2 NOTE 6
3

EXPOSED
5 THERMAL PAD
2X 0.65
(0.07) TYP
NOTE 5
1 4

PIN 1 ID 4X 0.28
0.15
(OPTIONAL) (0.11)
NOTE 4 0.3 0.1 C A B
0.2
0.05 C
3X 0.30
0.15

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.86)

SYMM

4X (0.36) 4X SEE DETAIL

(0.03)

4
4X (0.21) 1

SYMM 5 (0.65)

4X (0.18)

( 0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE

LAND PATTERN EXAMPLE

SCALE: 40X

0.05 MIN
ALL AROUND
SOLDER MASK
EXPOSED METAL OPENING

METAL UNDER
SOLDER MASK

SOLDER MASK
DEFINED

SOLDER MASK DETAIL

4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

SYMM

4X (0.4)
4X (0.03)

4
4X (0.21) 1

5
SYMM
(0.65)

SOLDER MASK
EDGE 4X (0.22)

2
3

( 0.45)
4X (0.235)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X

4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
YCH0004 SCALE 15.000
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER
D

C
0.4 MAX

SEATING PLANE
0.16 BALL TYP 0.05 C
0.10

0.35
TYP

SYMM D: Max = 0.667 mm, Min =0.607 mm

0.35
TYP
E: Max = 0.667 mm, Min =0.607 mm
A

1 2
0.225 SYMM
4X
0.185
0.015 C A B

4224061/A 12/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YCH0004 DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY

(0.35) TYP
4X ( 0.2)
1 2

A
SYMM
(0.35) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 50X

0.0325 MAX 0.0325 MIN METAL UNDER

( 0.2) SOLDER MASK
METAL

SOLDER MASK EXPOSED EXPOSED ( 0.2)

OPENING METAL METAL SOLDER MASK
OPENING
SOLDER MASK
NON-SOLDER MASK DEFINED
DEFINED (PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4224061/A 12/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YCH0004 DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY

(0.35) TYP

4X ( 0.21) (R0.05) TYP

1 2

A
SYMM
(0.35) TYP

METAL
TYP SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL
SCALE: 50X

4224061/A 12/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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