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TPS7A02
SBVS277 – JULY 2019

TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response
1 Features 3 Description
•
1 Ultra-low IQ: 25 nA (typ), even in dropout The TPS7A02 is an ultra-small, ultra-low quiescent
current low-dropout linear regulator (LDO) that can
• Shutdown IQ: 3 nA (typ) source 200 mA with excellent transient performance.
• Excellent transient response (1 mA to 50 mA)
The TPS7A02, with an ultra-low IQ of 25 nA, is
– < 10-µs settling time designed specifically for applications where very-low
– 100-mV undershoot quiescent current is a critical parameter. This device
• Packages: maintains low IQ consumption even in dropout mode
to further increase the battery life. When in shutdown
– 1.0-mm × 1.0-mm X2SON
or disabled mode, the device consumes ultra-low,
– SOT23-5 (preview) 3-nA IQ that helps increase the shelf life of the
– 0.65-mm x 0.65-mm DSBGA (preview) battery. The TPS7A02 has an output range of 0.8 V
• Input voltage range: 1.5 V to 6.0 V to 5.0 V available in 50-mV steps to support the lower
core voltages of modern microcontrollers (MCUs).
• Output voltage range: 0.8 V to 5.0 V (fixed)

ADVANCE INFORMATION
The TPS7A02 features a smart enable circuit with an
• Output accuracy: 1.5% over temperature
internally controlled pulldown resistor that keeps the
• Smart enable pulldown LDO disabled even when the EN pin is left floating
• Very low dropout: and helps minimize the external components used to
– 205 mV (max) at 200 mA (VOUT = 3.3 V) pulldown the EN pin. This circuit also helps minimize
the current drawn through the external pulldown
• Stable with a 1-µF or larger capacitor circuit when the device is enabled.

2 Applications The TPS7A02 is fully specified for TJ = –40°C to

+125°C operation.
• Wearables electronics
• Thermostats, smoke and heat detectors Device Information(1)
• Smart meters PART NUMBER PACKAGE BODY SIZE (NOM)

• Wireless IOTs X2SON (4) 1.00 mm × 1.00 mm

• Portable medical devices TPS7A02 DSBGA (4)(2) 0.65 mm × 0.65 mm

(2)
SOT-23 (5) 2.90 mm × 1.60 mm
• Building security and surveillance systems
• Electronic point of sale (EPOS) (1) For all available packages, see the package option addendum
at the end of the data sheet.
(2) Preview package.
Load Transient Response Quiescent Current vs Input Voltage
(VIN = VOUT + 1 V, CIN = 0.47 µF, COUT = 1 µF, IOUT = (IOUT = 0 A, COUT = 1 µF)
1 mA to 50 mA in 1 µs) 240
150 400 220 TJ
IOUT 350 -55°C 0°C 85°C
100 200 -40°C 25°C 125°C
VOUT
AC-Coupled Output Voltage (mV)

50 300 180
Quiescent Current (nA)

0 250 160
Output Current (mA)

-50 200 140

-100 150 120
-150 100 100
-200 50 80
-250 0 60
-300 -50 40
-350 -100 20
-400 -150 0
-450 -200 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0 50 100 150 200 250 300 350 400 450 500 Input Voltage (V)
Time (µs) D002

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 1 8 Application and Implementation ........................ 14
3 Description ............................................................. 1 8.1 Application Information............................................ 14
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 17
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 17
6 Specifications......................................................... 5 10 Layout................................................................... 18
6.1 Absolute Maximum Ratings ...................................... 5 10.1 Layout Guidelines ................................................. 18
6.2 ESD Ratings.............................................................. 5 10.2 Layout Examples................................................... 18
6.3 Recommended Operating Conditions....................... 5 11 Device and Documentation Support ................. 19
6.4 Thermal Information .................................................. 5 11.1 Device Support .................................................... 19
6.5 Electrical Characteristics........................................... 6 11.2 Receiving Notification of Documentation Updates 19
6.6 Switching Characteristics .......................................... 7 11.3 Community Resources.......................................... 19
6.7 Typical Characteristics .............................................. 8 11.4 Trademarks ........................................................... 19
7 Detailed Description .............................................. 9 11.5 Electrostatic Discharge Caution ............................ 19
7.1 Overview ................................................................... 9 11.6 Glossary ................................................................ 19
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 10 Information ........................................................... 19
ADVANCE INFORMATION

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

July 2019 * Initial release.

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5 Pin Configuration and Functions

DBV Package (Preview) DQN Package

5-Pin SOT-23 1-mm × 1-mm X2SON-4
Top View Top View

OUT 1 4 IN
IN 1 5 OUT

GND 2

EN 3 4 NC Thermal Pad
GND 2 3 EN

Not to scale Not to scale

Pin Functions: DQN, DBV

PIN
NAME DQN DBV (2) I/O (1) DESCRIPTION

ADVANCE INFORMATION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
EN 3 3 Input disables the device. If enable functionality is not required, this pin must be connected to
IN. VEN must not exceed VIN.
GND 2 2 — Ground pin. This pin must be connected to ground and the thermal pad.
Input pin. A 0.1-µF or greater effective capacitance is required from IN to ground to
minimize input impedance. For best transient response, use a 1-µF or larger ceramic
IN 4 1 Input
capacitor from IN to ground. Place the input capacitor as close to input of the device as
possible.
NC — 4 — No connect pin. This pin is not internally connected. Connect to ground or leave floating.
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to
ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor
OUT 1 5 Output
from OUT to ground. Place the output capacitor as close to output of the device as
possible.
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
Thermal pad –– —
connect to ground.

(1) NC = No internal connection.

(2) Preview package.

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YKA Package (Preview)

4-Pin 0.65-mm x 0.65-mm, 0.35-mm Pitch DSBGA
Top View

EN VIN
2

GND VOUT
1

A B

Pin Functions: YKA

PIN
NAME YKA (1) I/O DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables
EN A2 Input the device. If enable functionality is not required, this pin must be connected to IN. VEN must not
exceed VIN.
GND A1 — Ground pin. This pin must be connected to ground and the thermal pad.
Input pin. A 0.1-µF or greater effective capacitance is required from IN to ground to minimize
IN B2 Input input impedance. For best transient response, use a 1-µF or larger ceramic capacitor from IN to
ADVANCE INFORMATION

ground. Place the input capacitor as close to input of the device as possible.
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground
OUT B1 Output for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT to
ground. Place the output capacitor as close to output of the device as possible.

(1) Preview package.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 6.5
Voltage VEN –0.3 6.5 V
VOUT –0.3 VIN + 0.3 or 5.5 (2)
Current Maximum output Internally limited A
Operating junction, TJ –40 150
Temperature °C
Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller.

6.2 ESD Ratings

VALUE UNIT

ADVANCE INFORMATION
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 1.5 6.0 V
VEN Enable voltage 0 VIN V
VOUT Output voltage 0.8 5.0 V
IOUT Output current 0 200 mA
CIN Input capacitor 1 µF
COUT Output capacitor (1) 1 1 22 µF
FEN EN toggle frequency 10 kHz
TJ Operating junction temperature –40 125 °C

(1) Effective output capacitance of 0.5 µF minimum required for stability.

6.4 Thermal Information

TPS7A02
THERMAL METRIC (1) DQN (X2SON) DBV (SOT23-5) YFF (DSBGA) UNIT
4 PINS 5 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 179.1 TBD TBD °C/W
RθJC(top) Junction-to-case(top) thermal resistance 137.6 TBD TBD °C/W
RθJB Junction-to-board thermal resistance 116.3 TBD TBD °C/W
ψJT Junction-to-top characterization parameter 6.1 TBD TBD °C/W
ψJB Junction-to-board characterization parameter 116.3 TBD TBD °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 112.3 TBD TBD °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C, VOUT ≥ 1.0 V, 1 µA ≤ IOUT ≤ 1 mA –1 1 %
Nominal accuracy
TJ = 25°C; VOUT < 1.0 V –10 10 mV
TJ = –40°C to +85°C –1.5 1.5
VOUT ≥ 1.0 V %
Accuracy over TJ = –40°C to +125°C –3 3
temperature TJ = –40°C to +85°C –15 15
VOUT < 1.0 V mV
TJ = –40°C to +125°C –30 30
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V (1) TJ = –40°C to +85°C 2.2 3
ΔVOUT/ΔVIN Line regulation mV/V
TJ = –40°C to +125°C 4
1 mA ≤ IOUT ≤ 200 mA, TJ = –40°C to +85°C 20 38
ΔVOUT(ΔIOUT) Load regulation (2) VIN = VOUT(nom) + 0.5 V (1) mV
TJ = –40°C to +125°C 50

TJ = 25°C 25 46
IGND Ground current IOUT = 0 mA nA
TJ = –40°C to +85°C 60
ADVANCE INFORMATION

5 µA ≤ IOUT < 1 mA 1
Ground current
IGND/IOUT efficiency vs load 1 mA ≤ IOUT ≤ 100 mA TJ = 25°C 0.25 %
current
IOUT > 100 mA 0.15
Ground current in IOUT = 0 mA,
IGND(DO) TJ = –40°C to +85°C 25 120 nA
dropout (3) 1.5 V ≤ VIN < 6.0 V,
ISHDN Shutdown current VEN = 0 V, 1.5 V ≤ VIN ≤ 6.0 V, TJ = 25°C 3 10 nA
ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.1 V 240 450 650 mA
Short-circuit current
ISC VOUT = 0 V 65 mA
limit
0.8 V ≤ VOUT < 1.0 V 1046
1.0 V ≤ VOUT < 1.2 V 876
1.2 V ≤ VOUT < 1.5 V 670
TJ = –40°C to +85°C 1.5 V ≤ VOUT < 1.8 V 446
1.8 V ≤ VOUT < 2.5 V 400
2.5 V ≤ VOUT < 3.3 V 250
3.3 V ≤ VOUT < 5.0 V 204
VDO Dropout voltage (4) mV
0.8 V ≤ VOUT < 1.0 V 1114
1.0 V ≤ VOUT < 1.2 V 953
1.2 V ≤ VOUT < 1.5 V 803
TJ = –40°C to +125°C 1.5 V ≤ VOUT < 1.8 V 535
1.8 V ≤ VOUT < 2.5 V 430
2.5 V ≤ VOUT < 3.3 V 299
3.3 V ≤ VOUT < 5.0 V 245
Power-supply
PSRR f = 1 kHz, IOUT = 30 mA 55 dB
rejection ratio
Output voltage
VN BW = 10 Hz to 100 kHz, VOUT = 0.8 V, IOUT = 30 mA 115 µVRMS
noise
VIN rising 1.23 1.3 1.47
VUVLO UVLO threshold V
VIN falling 1.17 1.12 1.26
VUVLO(HYST) UVLO hysteresis VIN hysteresis 180 mV

(1) VIN = 2.0 V for VOUT ≤ 0.9 V.

(2) Load Regulation is normalized to the output voltage at IOUT = 1 mA.
(3) VIN = 95% x VOUT(NOM).
(4) Dropout is measured by ramping VIN down until VOUT = VOUT(nom) x 95%, with IOUT = 200 mA.
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Electrical Characteristics (continued)

Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN pin logic high
VEN(HI) 1.1 V
voltage
EN pin logic low
VEN(LOW) 0.3 V
voltage
EN pin leakage
IEN VEN = VIN = 6.0 V 10 nA
current
Smart enable
REN(PULLDOWN) VEN = 0.3 V 500 KΩ
pulldown resistor
RPULLDOWN Pulldown resistor VIN = 3.3 V, device disabled 120 Ω
Thermal shutdown
TSD(shutdown) Shutdown, temperature increasing 175
temperature
°C
Thermal shutdown
TSD(reset) Reset, temperature decreasing 155
reset temperature

6.6 Switching Characteristics

ADVANCE INFORMATION
At VIN = VOUT +VDO(max) + 0.5 V, IOUT = 30 mA, andCIN = COUT = 1 µF (unless otherwise noted). Alltypical values are at TJ =
25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
From EN assertion to VOUT = 95% × VOUT(nom) , VOUT =
tSTR Start-up time 400 1500 µs
1.8 V

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6.7 Typical Characteristics

at operating temperature range (TJ = –40°C to 125°C), VIN = VOUTnom + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)

400 400
300 IOUT 350
VOUT

AC-Coupled Output Voltage (mV)

200 300
100 250

Output Current (mA)

0 200
-100 150
-200 100
-300 50
-400 0
-500 -50
-600 -100
-700 -150
-800 -200
0 50 100 150 200 250 300 350 400 450 500
Time (µs) D001
VIN = VOUT + 1 V, CIN = 0.47 µF, COUT = 1 µF, IOUT slew rate = 0.15 A/µs
ADVANCE INFORMATION

Figure 1. 0-mA to 150-mA Load Transient

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7 Detailed Description

7.1 Overview
The TPS7A02 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the device ideal for most battery-powered applications.
This low-dropout linear regulator (LDO) offers optional active discharge, foldback current limit, shutdown, and
thermal protection.

7.2 Functional Block Diagram

Current
IN OUT
Limit
1.2-V
Bandgap +

Active Discharge
± P-Version Only

ADVANCE INFORMATION
+
Error
Amp
±

UVLO
Internal
Controller

Thermal
Shutdown

EN

GND

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7.3 Feature Description

7.3.1 Excellent Transient Response
The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
device response time to transients.
Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the loop. The
device response time across the output voltage range is constant because a buffered reference topology is used,
which keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensures excellent transient response
while maintaining the device low IQ in steady-state conditions.

7.3.2 Active Discharge (P-Version Only)

The device has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by
the undervoltage lockout (UVLO).
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
ADVANCE INFORMATION

flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.

7.3.3 Low IQ in Dropout

In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs with adaptive biasing. The TPS7A02 detects when operating in dropout conditions and disables the
adaptive biasing, thus minimizing the IQ increase.

7.3.4 Smart Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven
above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal
pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.

7.3.5 Dropout Voltage

Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.
The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output
voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the
nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON) =
IRATED (1)

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Feature Description (continued)

7.3.6 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = TBD% × VOUT(nom).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.

ADVANCE INFORMATION
Figure 2 shows a diagram of the foldback current limit.

VOUT

Brickwall
VOUT(NOM)

VFOLDBACK

Foldback

0V IOUT

0 mA ISC IRATED ICL

Figure 2. Foldback Current Limit

7.3.7 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.8 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).

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Feature Description (continued)

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
ADVANCE INFORMATION

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER
OPERATING MODE
VIN VEN IOUT TJ
Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Disabled
(any true condition VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown)
disables the device)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)

ADVANCE INFORMATION
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
ADVANCE INFORMATION

and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in
Figure 3 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt tCt tDt tEt tGt tHt

B F

Figure 3. Load Transient Waveform

During transitions from a light load to a heavy load, the:

• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)

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Application Information (continued)

During transitions from a heavy load to a light load, the:
• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.

8.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational
voltage range, and ensures that the device shuts down when the input supply collapses. Figure 4 shows the
UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:
• Region A: The device does not start until the input reaches the UVLO rising threshold.
• Region B: Normal operation, regulating device.
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

ADVANCE INFORMATION
output may fall out of regulation but the device remains enabled.
• Region D: Normal operation, regulating device.
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

VIN

VOUT C
tAt tBt tDt tEt tFt tGt

Figure 4. Typical UVLO Operation

8.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT (2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A85 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.

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Application Information (continued)

The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD) (3)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4)

Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.5.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
ADVANCE INFORMATION

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
• PD is the power dissipated as explained in Equation 2
• TT is the temperature at the center-top of the device package, and
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge (5)

8.1.5.2 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 5 and can be
separated into the following parts:
• Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
• The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN –
VOUT increases the output current must decrease.
• The rated input voltage range governs both the minimum and maximum of VIN – VOUT.

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Application Information (continued)

Figure 5 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA = TBD°C/W, as given in the Thermal Information table.

Output current limited by Rated output

Output current limited by thermals
dropout current
Output Current (A)

Limited by Limited by
minimum VIN maximum VIN

VIN ± VOUT (V)

ADVANCE INFORMATION
Figure 5. Region Description of Continuous Operation Regime

8.2 Typical Application

IN OUT
CIN
COUT
Device
VBAT Load
EN GND

Figure 6. Capacitor-Free Operation From a Battery Input Supply

8.2.1 Design Requirements

Table 2. Design Parameters

PARAMETER DESIGN REQUIREMENT
Input voltage 3.0 V to 1.8 V (two 1.5-V batteries)
Output voltage 1.0 V, ±1%
Input current 200 mA, maximum
Output load 100-mA dc
Maximum ambient temperature 70°C

8.2.2 Detailed Design Procedure

Use the recommend 1-µF input and output capacitor because the input source has a high ESR of 600 mΩ (typ).

9 Power Supply Recommendations

TI highly recommends using a 1 µF or greater input capacitor to reduce the impedance of the input supply,
especially during transients.

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10 Layout

10.1 Layout Guidelines

• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.

10.2 Layout Examples

VOUT VIN
1 4

COUT
CIN

2 3
ADVANCE INFORMATION

GND PLANE

Represents via used for

application specific connections

Figure 7. Layout Example for the DQN Package

VIN VOUT

1 5

CIN 2 COUT

3 4

GND PLANE

Represents via used for

application specific connections

Figure 8. Layout Example for the DBV Package

IN OUT
A1 A2

CIN COUT
Via

B1 B2
EN GND

Figure 9. Layout Example for the YKA Package

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature (1) (2)

PRODUCT VOUT
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A02 family actively discharge
TPS7A02xx(x)Pyyyz
the output when the device is disabled.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.

11.2 Receiving Notification of Documentation Updates

ADVANCE INFORMATION
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 19

 PACKAGE OPTION ADDENDUM

www.ti.com 26-Jul-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

PTPS7A0218PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125

PTPS7A0230PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125

PTPS7A0233PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Jul-2019

Addendum-Page 2
 IMPORTANT NOTICE AND DISCLAIMER

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