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ECE_103_Lecture33

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3 views16 pages

ECE_103_Lecture33

Uploaded by

justinhunt018
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Behavioral Modeling:Procedural blocks

IMPORTANT POINTS:

1. Initial block execute only once.


2. Always block execute continuously.
3. LHS must be reg type.
4. Statement inside initial and always blocks
runs sequentially, so the name procedural
blocks.
5. Use of begin mark the onset of procedural
block and end finishes the sequential
execution.

34
Behavioural Modelling: logic gates

Behavioural level
module logic_gates( input wire a, b, output reg y0,y1, y2, y3, y4, y5 );

always @(a,b)

begin
y0 = ~a;
y1 = a & b;
y2 = a | b;
y3 = ~(a & b);
y4 = ~(a | b);
y5 = a ^ b;
y6 = ~(a ^ b);
end

endmodule

35
Conditional Statements:
• If-else
• case
Synthesizable: Hardware is created.

Loops

• While
• For
• Forever
• Repeat

Non-Synthesizable: Ignored during Hardware mapping, so do not use loops in Design


File.

36
If else conditional statement
Type 1: if block

Type 2: if-else block

37
If else conditional statement

Type 3: if else-if…else

38
Example MUX: Behaviroal Modelling

39
If-else

40
case statement

41
4x1 Multiplexer using case - statement

module mux_4to1_case ( input [3:0] a, // 4-bit input called a


input [3:0] b, // 4-bit input called b
input [3:0] c, // 4-bit input called c
input [3:0] d, // 4-bit input called d
input [1:0] sel, // input sel used to select between a,b,c,d
output reg [3:0] out); // 4-bit output based on input sel

always @ (a or b or c or d or sel) begin


case (sel)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
2'b11 : out = d;
default: out=4’d0;
endcase
end
endmodule

42
Half Adder using case - statement

module ha(s,c,a,b);
input a,b;
output reg s,c;
always@(a,b)
begin
case({a,b})
2'b00 :begin s=1'b0; c=1'b0; end
2'b01 :begin s=1'b1; c=1'b0; end
2'b10 :begin s=1'b1; c=1'b0; end
2'b11 :begin s=1'b0; c=1'b1; end
default : begin s=1'b0; c=1'b0; end
endcase
end
endmodule

43
Loops
There are four types of looping statements in
Verilog:

• while
• for
• repeat
• Forever

44
While Loops

while loop: It executes until the while-expression


becomes false.

45
for Loop
for Loop contains three parts:
An initial condition;
A check to see if the terminating condition is true;
A procedural assignment to change value of the control variable

NOTE: for Loops are generally used when there is a fixed beginning
and end to the loop. If the Loop is simply looping on a certain
condition, it is better to use the while loop.
46
forever loop
forever loop does not contain any expression and executes forever until the
$finish task is encountered. A forever loop can be exited by the use of the
disable statement.

47
Assignment statements

48
Blocking and Non-blocking assignment

49

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