Sinhgad Technical Education Society’s

SMT. KASHIBAI NAVALE COLLEGE OF ENGINEERING

Approved by AICTE and Affiliated to Savitribai Phule Pune University (Accredited by NBA & NAAC with “A” Grade)
S.No. 44/1, Off Sinhgad road, Vadgaon(bk), Pune-411041. Website : www.skncoe.sinhgad.edu

Department of Electronics and Telecommunication Engineering

B.E. E &TC (2019 Pattern)
ACADEMIC YEAR 2024-25, SEM-I
ASSIGNMENT NO.5
COURSE: VLSI DESIGN & TECHNOLOGY
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UNIT- V: Application Specific Integrated Circuits
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CO5: Analyze various issues and constraints in design of an ASIC
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Q.1 Explain design hierarchy with neat diagram. CO5 BL2 6M

understand
Q.2 CO5 BL2
Explain in detail about photolithography and pattern transfers. Create 4M
Q.3 CO5 BL2 4M
Describe the basic MOS transistor operation. Create
Q.4 CO5 BL3
Explain the CMOS fabrication technique with neat diagram. Understand 6M
Q.5 CO5 BL2 4M
With neat diagrams explain the steps involved in the p-well fabrication process. Understand
Q.6 CO5 BL3 6M
With neat diagrams explain the steps involved in the n-well fabrication process. Understand
Q.7 CO5 BL2
Explain with neat diagram the SOI process and mention its advantages. Understand 6M
Q.8 CO5 BL2
Explain in detail about submicron CMOS process. Understand 8M
Q.9 CO5 BL3 6M
Explain the construction of nMOS and pMOS enhancement mode transistor. Create
Q.10 CO5 BL3 4M
Explain the operation of pMOS depletion mode transistor. Create
Q.11 CO5 BL3 4M
Explain in detail about CMOS design rules. Create
Q.12 CO5 BL3
Write notes on lamda based layout rule. Apply 8M
Q.13 Discuss in detail about different SCMOS design rule set. CO5 BL2 6M
Understand
Q.14 List the sequence of steps to create the pattern. CO5 BL2 6M
Understand
Q.15 Draw the layout of CMOS inverter. CO5 BL3 8M
Understand

Dr. P. M. Bangare Dr. P. M. Bangare Dr. S. K. Jagtap

Course Teacher Course Coordinator Program Coordinator (HOD)