EEE 3101: Digital Logic and Circuits

Adders

Course Teacher: Nafiz Ahmed Chisty

Associate Professor and Head (UG)

Department of EEE
Faculty of Engineering, AIUB
Room# DNG03, Ground Floor, D Building
Email: chisty@aiub.edu
Website: http://engg.aiub.edu/
Website: www.nachisty.com
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

BASIC ADDERS

Adders are important in computers and also in other types of digital

systems in which numerical data are processed. An understanding of the
basic adder operation is fundamental to the study of digital systems. In this
section, the half-adder and the full-adder are introduced.
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

The Half-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

A half-Adder accepts adds two bits and produces a Sum and a Carry
output.

Logic Symbol: Truth Table:

Circuit Diagram:

Expression:
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

The Half-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• 𝑆 = 𝐴̅. B + A. 𝐵̅= A⊕B

• COUT =A . B

//Device name and I/O ports

module HA (input wire A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B;
assign Cout= A & B;

endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

The Full-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

The Full-Adder accepts two input bits and an input carry and generates a sum output and
an output carry.

Logic Symbol: Truth Table:

Circuit Diagram: Expression:

 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

The Full-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• S = A ̅B̅CIN+ A̅BCIN + AB̅ CIN + ABCIN = A ⊕ B ⊕ C

• C OUT = A̅BCIN+ AB̅CIN + ABCIN + ABCIN = AB +(A ⊕ B )C IN

//Device name and I/O ports

module FA(input wire Cin, A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B ^ Cin;
assign Cout= (A & B) | ((A ^ B ) & Cin);

endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

The Full-Adder implementation with Half-Adders

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Half Adder Expression: Full Adder Expression:

 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

PARALLEL BINARY ADDERS

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Two or more full-adders are connected Example:

to form parallel binary adders.
A single full-adder is capable of adding
two 1 bit numbers and an input carry.
To add binary numbers with more than
one bit, additional full-adders are
required.

To add two binary numbers, a full-adder

is required for each bit in the numbers.
So for 2-bit numbers, two adders are
needed; for 4-bit numbers, four adders
are used; and so on. The carry output of
each adder is connected to the carry
input of the next higher-order adder.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Multi-bit AddersfromFull Adders

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• A 2-bit adder can be constructed by cascading (series placement) of two full adders.
//Top-Level module
//Device name and I/O ports
module Adder_2Bit (input wire [1:0] A, B,
output wire [1:0] S,
output wire Cout);
//Define internal C incorporating all carry type signals
wire [2:0] C;
assign C[0] = 0; //Use C[0] just for a “symmetric look”

//Level-2
//Device name and I/O ports
module FA (input wire Cin, A, B,
output wire S, Cout);
//Define behavior/structure of the circuit
assign S= A ^ B ^ Cin;
assign Cout= (A & B) | ((A ^ B ) & Cin);
endmodule

//Define behavior/structure of the circuit

//Instantiating two half adders
FA FA1 (.Cin(C[0]), .A(A[0]), .B(B[0]), .S (S[0]), .Cout (C[1]));
FA FA2 (.Cin(C[1]), .A(A[1]), .B(B[1]), .S (S[1]), .Cout (C[2]));
assign Cout = C[2]; //Pass C[2] as Cout
endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Four-Bit Parallel Adders

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

(a) Internal connection

 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Adder Expansion
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers
by using two 4-bit adders.
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Overflow, Number Wheel

• In digital design, input and output sizes of a sub-system are kept the same in many cases. So,
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

if this is followed the carryout becomes an extra signal. Even if carryout is not considered
part of the result due to the above requirement, it can serve another purpose—that is it
serves as an overflow indicator.
• In addition, HIGH carryout indicates overflow.
• Overflow means that the result could not be mapped within the available number of bits.
• For example, consider 011 (3) + 110 (6) in a 3-bit
adder.
011(3)
110 (6)
1 001 (1)
We can graphically represent the addition in a number wheel.
We go clock-wise for addition.
For this example, start at 3, and then go 6 steps clock-wise to get the addition result.
If the arrow goes beyond max. number (111(7)), then overflow occurs. From number wheel, we get
3 + 6 = 1 as well.
000
111 001

110 010

101 011
100
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Subtractor
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• The logic equation for subtraction can be developed from truthtable. One can build
half- subtractor and full-subtractor from truthtable. Similar, to adders, multi-bit
subtracters can be built from full-subtractor.
• However, subtracters are typically realized with 2’s compliment addition in
industrial EDA tools. This is because, when 2’s compliment subtraction is used,
adders can be used for both addition and subtraction purposes.
• Subtraction of two numbers is defined as addition of 2’s compliment version of one
of the inputs with the other inputs kept unchanged. So, one input is kept unchanged,
while the other input is provided to the adder in its 2’s compliment form.

Ysub =A–B
= A + (-B)
= A + (2’s compliment of B)

• 2’s compliment is formed from addition of 1’s compliment with 1.

• 1’s compliment is the NOT operation performed on an input.
So, Ysub = A + (2’s compliment of B)
= A + (1’s compliment of B + 1)
= A + 𝐵̅ + 1
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Overflow (Subtraction), Number Wheel

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• In subtraction, LOW carryout indicates overflow.

• Subtraction Overflow or underflow means that the result could not be mapped within the
available number of bits. This happens when a large number is subtracted from a small
number. In integer arithmetic, there is no negative number. In other words, there is no number
smaller than zero.
• We can graphically represent the subtraction in a number wheel.
• One needs to go counter-clock-wise direction for subtraction.
• For this example, to get the result of 3 – 5, start at 3, and then go 5 steps counter-clock-wise to
get the subtraction result.
• If the arrow goes beyond min. number (000(0)), then overflow occurs. From number wheel,
we get 3 – 5 = 6 as well.
000
111 001

110 010

101 011
100
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Adder-Subtractor
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Since both addition and subtraction uses addition, one can develop a common expression for
addition and subtraction provided there is a control signal that selects whether addition or
subtraction should be performed.
• Addition: A+B
Subtraction: A – B = A + (-B) = A + 𝐵̅ + 1

• If we can control the 2nd input to the adder (say, B_to_add), regarding whether it
should be B or 𝐵̅, we can use the same adder to produce both addition and subtraction.
• Secondly, subtraction requires an extra 1, while the addition does not need any.
• So, if the control signal, say AS, is chosen in such a way that a AS = 0 ensures addition
and AS = 1 ensures subtraction, then the control signal itself can be added to the
addition process. This will provide that extra 1 for subtraction.

• So, the common equation for adder-subtractor becomes S=A+B_to_add+AS.

Where, B_to_add = AS’. B + AS. B’= AS ⊕ B
For addition, this equation becomes A + B + 0.
For subtraction, it becomes A + 𝐵̅+ 1.
AS B_to_add S S values
Addition 0 B A + B_to_add + AS A+B+0
Subtraction 1 𝐵̅ A+𝐵
̅+ 1
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Adder-Subtractor
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• A 1-bit adder-subtracter utilizes a full adder and an XOR gate. The control signal AS
would be connected to the Cin port of the full adder.

A A
B B
AS AS

B_to_add

COUT COUT
S S
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Adder-Subtractor
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• A 2-bit adder-subtracter would utilize two full adders and two XOR gates, as shown
below. The control signal AS would be connected to the Cin port of the full adder for
the LSB bit.

2
A
2
B
AS

COUT
2
S
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| chisty@aiub.edu

Reference:
[1] Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall.
[2] M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall.

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Thanks