Circuits, Systems, and Signal Processing

https://doi.org/10.1007/s00034-024-02842-8

FPGA Implementation of an Effective Image Enhancement

Algorithm Based on a Novel Daubechies Wavelet Filter Bank

Md Tarikul Islam1 · Aswini Kumar Samantaray2 · Pradeep Gorre3 ·

Deepak Naik Jatoth1 · Sandeep Kumar4 · AlaaDdin Al-Shidaifat1 ·
Hanjung Song1

Received: 16 October 2023 / Revised: 17 August 2024 / Accepted: 20 August 2024

© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024

Abstract
The primary issues in producing natural images are low contrast and poor quality. A
novel Daubechies wavelet transform technique is proposed for image enhancement
which is implemented in field-programmable gate array (FPGA). The new Daubechies-
2 (tap-4) wavelet filter bank is splits the image into high-pass subband image and
low-pass subband image. These subbands are enhanced parallely using FPGA archi-
tectures of adaptive thresholding and top-hat transform. High-pass subband images
are improved by employing FPGA architecture of adaptive thresholding technique.
The FPGA architecture of morphology-based top-hat transform is used to improve
low-pass subband images. The FPGA architecture of newly designed Daubechies-2
wavelet, adaptive thresholding and morphology based top-hat transform, are imple-
mented in FPGA using XilinX Kintex-7 board. The hardware usage of the proposed
technique is compared with that of existing techniques. In addition, PSNR and RMSE
are used to assess the extent to which the suggested method performs. Experiments
revealed that this technique is excellent at both enhancing an image’s details and
effectively preserving its edge features with using less hardware.

Keywords Image enhancement · Adaptive threholding · Top-Hat transform ·

Daubechies wavelet · Peak signal to noise ratio

1 Introduction

Haze-like weather conditions have a major negative impact on intelligent surveillance

systems (ISS) such as autonomous driving vehicles and road traffic control where
the identification of pedestrians and vehicles is a top priority [16]. Haze obscures the
images that these ISS take, distorting perception by changing the scene’s colour and
intensity [16]. The quality of a scene is severely reduced by scattered atmospheric
particles as fog, haze, aerosol, mist, etc., in remote sensing applications. Research

Extended author information available on the last page of the article

 Circuits, Systems, and Signal Processing

on perceptual quality estimate and improvement models for foggy natural photos has
been prompted by the unpredictability of weather conditions. Dehazing algorithms
(DHAs) are eventually widely given as a solution in the previous works; provided an
automated algorithm is required to compare various algorithms as a result. The only
basis for evaluating the visual quality of these hazed/dehazed images is perceptibility,
as this quality parameter is necessary for image surveys in many vision-based ISS.
Although dehazing research has become more popular, little has been done to forecast
image quality. As a result, despite expanding study in the field of perceptual quality
evaluation, measurement of the visual quality of hazy images remains inaccurate.
Researchers have extensively investigated DHAs to improve visibility, and various
DHAs have been recommended for this use. As an illustration, He et al. [9] put out the
dark channel prior theory which claimed that an image devoid of haze, is made up of
a local minimum (near-zero) of the dark channel in at least one colour channel. Many
DHAs now have the dark channel as their foundation. A deep learning model, called
DehazeNet, was suggested by Cai et al. [3] to produce images which are haze free
by extracting haze features and then improving quality applying a bipolar rectified
linear unit (ReLU) activation function. To reduce colour distortion during dehazing,
Dudhane and Murala [6] used a cardinal colour channel and a multi-channel multi-scale
convolutional neural network (CNN).
The organization of the work is as follows. Section 2 brief the literature study related
to the topic. Section 3 gives the detailed explaination of the proposed work. Result
analysis are discussed in Sect. 4 while, the work is concluded in in Sect. 5.

2 Related Work

Numerous DHAs have been proposed in recent years due to the requirement for dehaz-
ing in computational image and consumer photography. In order to incorporate surface
shading, Fattal [8] improved the picture formation model. On the basis of that, he pre-
sented a technique for removing haze and estimating transmission. Dehazing was the
specific filtering issue that Tarel and Hautiere [26] focused on, and they provided a
solution based on the median filter. The authors suggested a corner and edge preserv-
ing filter as an alternative to the median filter. For dehazing, He et al. [10] invented a
dark channel prior (DCP). This algorithm denotes a condition when atleast one colour
channel has minimal intensity at few pixels in the non-sky regions. Another approach,
based on a directed joint bilateral filter, was introduced by Xiao and Gan [29]. Meng
et al. [17] investigated the transmission’s built-in boundary constraint and suggested
a regularisation technique to get rid of the haze.
To approximate the transmission from a few haze-relevant attributes, Tang et al.
[25] used random forest to develop a regression model. Under two scene restrictions,
namely locally context-aware scene transmission and constant scene radiance, Lai et
al. [13] developed the ideal transmission map. On the premise that a picture might be
represented by a few hundred unique colours that clustered in RGB space, Berman
et al. [2] suggested a nonlocal technique. Cai et al. [3] introduced a complete neu-
ral network dehazing technique. Additionally, there are DHAs created expressly for
outdoor photography. Long et al. [15] presented a DCP-based remote-sensing image
Circuits, Systems, and Signal Processing

DHA. Pan et al. [19] developed a technique based on the distinctions between dark
channels in normal and remote sensing photographs. By studying the sparse charac-
teristics of the cloudy and cloud-free areas, Xu et al. [30] suggested a cloud removal
approach. Elmasry et al. [7] proposed a recursive technique for the enhancement of
satellite images based on various wavelet transforms. An image dehazing technique
with boundary constraints is proposed for satellite images in [24]. A dark channel
prior technique is used in [1] for dehazing of real time synthetic daylight images.
Several researchers have attempted to deploy the image intensification technique
in electronics over the past few decades. According to Honda et al. [11], high-level
synthesis was used to create a Contrast Limited Adaptive Histogram Equalization
(CLAHE) design for a low-end FPGA board that enhances the side mirror camera’s
dark picture resolution. To minimize computational complexity and realization costs
while preserving high visual quality, the authors of [4] initially adapted the ACE algo-
rithm. To fulfil the need for real-time picture enhancement, an effective VLSI design
for the hardware-friendly ACE algorithm is then put forward. By offering flexibil-
ity, parallelization, pipelining, and reconfigurability, the authors of [20] propose an
enhanced image enhancement algorithm with better performance and show how it may
be implemented on an FPGA to meet the demand for a powerful, fast, and affordable
processing unit. The new image enhancement technique was developed on Cyclone
V by utilizing the Intel Quartus Prime CAD tool set, and the FPGA implementation
was created employing High Level Synthesis utilizing MATLAB specifications. An
enhanced adaptive scene transformation image improvement algorithm is proposed
in [23] based on a thorough examination of image improvement algorithms. Image
improvement, while retaining the original semantics, is intended to speed up process-
ing, enhance image quality, and ease further analysis and processing. According to
[27], the authors’ nine-stage pipelined hardware design for haze removal utlises the
saturated hazy image as a starting point to calculate the local air light and transmis-
sion of each pixel in the dehazed image. Because we adopted a pixel-based approach,
unlike patch-based approaches, the proposed technique does not need an edge detec-
tion unit to determine whether a pixel is on the edge or not. The suggested approach
may operates at 94.7 MHz and requires a minimum of 970 logic elements (LEs) to
implement on the FPGA platform. Wang et al. [28] proposed a technique for low
light image enhancement using lightweight convolutional neural network (CNN). The
authors also implemented their method in FPGA platform. However, this method con-
sumes more hardware and dynamic power due to its complex computations in CNN.
C et al. [12] studied different filter mechanisms including Daubechies wavelet filter
to remove noises from ultrasonic ovarian images. The authors proved that the wavelet
filter gives better result as compared other filters such as median filter, butterworth fil-
ter and fourier filter. Similarly, Nikam et al. [18] proposed a color image enhancement
technique using Daubechies wavelet filter. Samantaray et al. [22] proposed a dyadic
and symmetric Daubechies (Daub-4) wavelet filter for medical image retrieval. Since
the filter is completely dyadic and symmetric, it consumes less hardware as compared
to other wavelet filter bank. However, the filter is designed by slightly changing the
perfect reconstruction.
 Circuits, Systems, and Signal Processing

Fig. 1 Block diagram of FPGA implementation of proposed method

3 Proposed Method

The block diagram of representation of the proposed technique on FPGA implementa-

tion is illustrated in Fig. 1. Each time, the amount of pixels is parallelly processed after
being stored into an input block RAM (BRAM) using a.coe file. Based on the proposed
architecture of discrete wavelet transform (Daubechies- 2), the images are further
decomposed into three high-pass sub-bands (LH, HL and HH bands)and one low-pass
sub-bands (LL band). To enhance the high-pass sub-bands images, we use threshold-
ing FPGA architecture. Later, the enhanced high-pass sub-images are obtained. For
low-pass sub-band images, the FPGA architecture of morphology top-hat transform
is applied for enhancement. After the entire operation, the image data is saved in an
output BRAM.
The proposed method is described in detail as follows;

3.1 Discrete Wavelet Transform

One of the key techniques for compressing image data to use less memory is the wavelet
transform [21]. Compared to other algorithms, wavelet-based compression techniques
provide benefits including multi-resolution, scalability, and tolerable deterioration.
The discrete wavelet transform separates data, signals, and functions into various
frequency components before analyzing each component with an appropriate level of
resolution for its scale.
Daubechies wavelet [5] is an orthogonal wavelet with scaling and wavelet function
coefficients that specifies the quantity of vanishing moments. Depending on the order
of the filter coefficients, several types of Daubechies transforms, such as Daubechies-1
(Daub-1) to Daubechies-10 (Daub-10), have been defined.
In this work, a new Daubechies-2 (Daub-2) is proposed which is used to separate the
discrete approximations and details (sub signals) that make up the image information.
The diagram of image decomposition using wavelet transform, is given in Fig. 1.
High pass filters (HPF) and the low pass filters (LPF) of Daub-2 are applied to the
signal before the image is made of high frequency and low frequency components.
The input image is divided into various sub-band images by Daub-2, including LL,
LH, HL, and HH. To maintain the high frequency components of the image, Daub-2
has been used. By first applying the 1-D Daub-2 wavelet transform along the image’s
rows and then decomposing the outcomes along the columns, an image is subjected
Circuits, Systems, and Signal Processing

to a 2-D wavelet decomposition. In this study, we decompose an image using a one-

level wavelet technique. In order to avoid soft threshold filtering, the level of wavelet
decomposition should ideally not exceed four. Otherwise, the quality of the detailed
information may suffer [31]. Four deconstructed sub-band pictures, known as low-low
(LL), low-high (LH), high-low (HL), and high-high (HH), are produced as a result of
this technique. The frequency components of the sub bands span the whole range of
the original image’s frequency spectrum. The primary goal of edge enhancement is to
alter an image’s look to make it more visually appealing or to increase the visibility
of specific objects.
The coefficients of the original Daubechies-2 (Daub-2) filter are irrational in nature.
In order to implement this filter in FPGA, power consuming multipliers are needed
along with adders and shifters. In order to solve this issue, the authors proposed a novel
Daub-2 filter whose coefficients are dyadic in nature. These dyadic coefficients can be
implemented in FPGA using only adders and shifters and avoid the power consuming
multipliers. In order to implement the novel Daub-2 in FPGA, this filter is designed
as follows:
With maximum number of vanishing moments (zeros at z = −1), the low pass
filter (LPF) design equation of Daub-2 is expressed by:

H (z) = (1 + z −1 )2 (a0 + a1 z −1 ), a0 = 1 (1)

Similarly, the double shift orthogonal property of the wavelet filter bank for perfect
reconstruction condition is given as:


N −1
h m h m+2d = 0, d = 0 (2)
m=0

where h m represents the filter coefficient and N is the total number of coefficients in
the filter bank.
Two factors are considered from Eq. (1), the first factor is vanishing moment, given
as (1 + z −1 )2 with coefficients [1 2 1] while the second one is remainder factor,
given as 1 + a1 z −1 with coefficients [1 a1 ].
The of vanishing moment matrix C and remainder matrix D of Daub-2 filter
coefficients design can be formulated as:

⎛ ⎞
1 0
⎜2 1⎟
C=⎜
⎝1
⎟ , D = [ 1 a1 ]
2⎠
0 1

After multiplication of CDT , the coefficients of Daub-2 LPF are h 0 = 1, h 1 =

2 + a1 , h 2 = 1 + 2a1 and h 3 = a1 . By replacing the coefficient values in the double
shift orthogonal property given in Eq. (2) for Daub-2 filter, the error equation in terms
 Circuits, Systems, and Signal Processing

of a1 can be obtained as:

f (a1 ) = a12 + 4a1 + 1 = ε (3)

Where ε is a very small error introduced in perfect reconstruction to get dyadic value
of a1 . In order to get the value of a1 , the coefficient of the remainder is expressed
in terms of a1 = p2q (dyadic form where p = ±1 and qZ). Hence, an objective
function for Daub-2 filter can be formulated as follows:

f ( p, q) = p 4 24q + p 2 22q+4 + p 3 23q+3 + p2q+3

1/2 (4)
+ p 2 22q+1 + 1

Using the optimization technique continuous regression minimization, the coeffi-

cient values of proposed Daub-2 filter are realized using p = −1, q = −2 and a1 =
−1/4 with minimum deviation of 0.0143 in perfect reconstruction. The final coeffi-
cients of the proposed Daub-2 filter are represented as h 0 = 1, h 1 = 7/4, h 2 = 1/2
and h 3 = 1/4.

Algorithm 1 The work-flow of FPGA implementation of proposed method

1. Store the pixels of the input image in input block RAM (BRAM) serially.
2. Send the pixel data from BRAM to the Daub-2 filter unit consisting of adders and shifters (for a1 =
−1/4) one pixel per clock cycle.
3. Send the resultant high pass sub-band to adaptive thresholding unit.
(a) Calculate the normalized histogram using NHM module.
(b) Use PCOM and MIM modules to calculate class incidence and probabilities of median intensities
respectively.
(c) Calculate between-class variance using BCVM module followed by the threshold by OTM module.
4. Send the resultant low pass sub-band to morphology based top-hat transform unit consisting of erosion
and dilation modules.
(a) Compare each pixel in the image with the corresponding pixel in the structuring element. If all
corresponding pixels match, set the output pixel to 1; otherwise, set it to 0.
(b) Compare each pixel in the eroded image with the corresponding pixel in the structuring element.
If any corresponding pixel is 1, set the output pixel to 1; otherwise, set it to 0.
5. Combine the output of thresholding unit and top-hat transform unit using the synthesis Daub-2 filter
unit.
6. After the completion of the operation, the result is saved to output BRAM from which the output
enhanced image is obtained.

The total work flow of the proposed method is described in Algorithm 1. The
FPGA implementation structure of the proposed Daub-2 filter bank is shown in Fig. 2,
where the filter structures represents vanishing moment part implementation C with a
remainder part D of Daub-2 filter. It is noticed that the vanishing part contributes more
hardware utilisation of filter implementation whereas, designed remainder part coef-
ficients are dyadic. Therefore, the remainder part is implemented using only shifters.
Consequently, a total of four adders are required for Daub-2 filter as shown in Fig. 2.
Circuits, Systems, and Signal Processing

Fig. 2 Filter architecture of

proposed Daub-2 wavelet filter

3.2 Adaptive Threshoding

High-frequency sub-images include an extensive amount of image detail information.

These sub-images do, however, include a lot of noise. The smooth function of the
wavelet transform can aid in noise reduction, but it falls short of our needs.We can
also minimise some noise with the Haar wavelet transform, although high-frequency
sub-images still have a lot of noise. The detail information of image, noise, and high-
frequency coefficients are all improved at this point. We use the nonlinear approach
to remove the noise in high-frequency sub-images. Different thresholds are employed
to minimise noise in various sub-images because the noise attributes in various high
frequency sub-images vary.
The algorithm initially calculates the normalised histogram of an image A with
ai j represents a single pixel with b bits, and M × N denotes the size of the image.
The pixel can have L different integer intensity levels, each represented by a different
value of k that falls between 0 and L − 1, where L = 2b .
Each m-th image’s histogram, A(m), is calculated and saved in the vector as

p(m) = [ p0 (m), . . . , pk (m), . . . , p L−1 (m)] (5)

where, pk (m), is computed as

n k (m)
pk (m) = (6)
M×N

where the number of pixels with intensity k in the m-th image, denoted by n k (m),
is


N −1 M−1

n k (m) = Ci, j (n) (7)
i=0 j=0

with Ci, j (n) expressed as

1, if ai, j (n) = k
Ci, j (n) =
0, otherwise
 Circuits, Systems, and Signal Processing

Subsequently, the algorithm determines the best threshold between the two classes
after collecting the normalised histogram and storing it in the vector p. The ideal
threshold, designated as k ∗ (m) in this instance, can be described as

k ∗ (m) = arg0≤k≤L−1 maxσk2 (m) (8)

where the k-th 3 of the m-th image σk2 (m) is defined as

2
μ L−1 (m) × ωk (m) − μk (m)
σk2 (m) = (9)
ωk (m)(1 − ωk (m))

where ωk (m) represents the class occurrence probability with a given k threshold
while, μk (m) is the pixel mean intensity of the m-th image for k threshold, respectively.
μ L−1 (m) indicates the average intensity of the total m-th image, termed as global mean,
which is μk (m) for k = L − 1..
The variables ωk (m) and μk (m) can be expressed as


k
ωk (m) = Pi (m) (10)
i=0

and


k
μk (m) = i.Pi (m) (11)
i=0

After calculating the optimal threshold value, k ∗ (m), the input image A(m) pixels
are identified as a background or object, producing a mask for the input image.
The generic hardware architecture used to implement the algorithm is shown in
Fig. 3. As is evident, the architecture was created using the information provided
above. The normalised histogram module (NHM), between-class variance module
(BCVM),mean intensity module (MIM), probability of class occurrence module
(PCOM), and optimal threshold module (OTM) are the five key modules that make
up this system.
Through the usage of Eqs. (5) and (6), the NHM is in the process of producing the
normalized histogram of the input image as given in Fig. 4. Because the full image
must be scanned in order to obtain the histogram components, this algorithmic step
typically requires more clock cycles to execute than other steps. In order to streamline
this procedure, we suggest parallelizing this step by computing the partial values of
the components. It is evident that the NHM module consists of the same submodules
known as Partial Normalized Histogram (PNH), which compute the partial values of
the histogram’s constituent parts. The final values of these are then obtained by adding
them together. In accordance with Eq. (11) the MIM determines the average intensity
value of the pixels up to level k. There is a parallel computation for every kth average
intensity. Figure 5 illustrates the architecture of this module, which places registers
Circuits, Systems, and Signal Processing

Fig. 3 FPGA implementation

diagram of adaptive thresholding

(R), adders (SUM), and gains submodules (G k ) after each component. Equation (11)
states that a gain with a value of k is multiplied by each kth pk (m) component of the
normalized histogram. Equation (10) is used in PCOM to calculate the probability of
class occurrence ωk (m) for a given threshold k. A gain submodule to weight the input
is absent from this module, which shares an architecture with MIM given in Fig. 5.
BCVM uses Eq. (9) to determine the kth between-class variance of the mth image,
or σk2 (m). The internal structure of the BCVM module consists of L equal submodules
called Between-Class Variance (BCV) of k as shown in Fig. 6. The kth submodule
BC Vk computes each kth σk2 (m) in parallel. This submodule has eleven registers
(R), a point shift (B PCk ), a Look-Up Table (LU Tk ), two subtractors (SU Bi,k ), four
multipliers (MU L Ti,k ), and a look-up table (LU Tk ). The OTM module executes the
final stage of the thresholding algorithm, which compares all kth values of the between-
class variance, σk2 (m), in order to ascertain the ideal threshold of the mth image, k ∗ (m)
using Eq. (8). Figure 7 displays this module’s architecture. It is evident that each
component is followed by a register (R), 2 × (L − 1) multipliers (MUX), and L-1
comparators (C O M Pk ).

3.3 Morphology Based Top-Hat Transform

The field of mathematics, known as mathematical morphology, has been employed

extensively in the processing of digital images. Dilation and erosion are the two funda-
mental operations that form the basis of the majority of morphological procedures. Let
S(i, j) represent in for a structural element and A(i, j) represent a grayscale image
with a size of M × N . The terms A(i, j) ⊕ S and A(i, j)  S respectively describe the
dilation and erosion of A(i, j) by S(i, j). Opening and closing of A(i, j) by S(i, j),
represented as A ◦ S and A • S, respectively, are based on erosion and dilation. The fol-
lowing definitions represent the top-hat transform of A(i, j) by S(i, j) using opening
Circuits, Systems, and Signal Processing

Fig. 4 NHM unit architecture

Circuits, Systems, and Signal Processing

Fig. 5 MIM unit architecture

 Circuits, Systems, and Signal Processing

Fig. 6 BCVM unit architecture

Circuits, Systems, and Signal Processing

Fig. 7 OTM unit architecture

 Circuits, Systems, and Signal Processing

and closing operations:

W T H (i, j) = A(i, j) − A ◦ S(i, j) (12)

BT H (i, j) = A • S(i, j) − A(i, j) (13)

where BT H is the traditional black top-hat transform and W T H is the traditional

white top-hat transform, both of which are typically employed to extract bright picture
regions.
Combining the bright image regions from the original image and deleting the dark
image regions is one method for improving the contrast of an image using the classic
top-hat transform.

Aen = A + Aw − Ab (14)

where A is the original image, Ab is the extracted dim image regions, Aw is the
extracted bright image regions and Aen is the final enhanced image.
The conventional top-hat transform, also known as the white top-hat transform, is
used to emphasise foreground items and enhances shadow details in images.
The top hat morphology is directly implemented and shown in Fig. 8. Three-by-
three structure elements (SE) are used to create erosion (E) and dilation (D). Full pixel
neighbourhood is achieved using the conventional technique, which employs two delay
lines. This is accomplished through the Kintex 7 Block RAM module, which uses two
counters as address pointers for FIFO task. Every Block RAM module stores a single
image line (512 pixels× 8bits).
Predicting and then removing background is the main step of the top-hat algorithm.
The open operation (erosion and dilation) unit, delay unit, and backdrop difference
operating unit make up the majority of the top-hat unit.
Morphology is a form of local business. The erosion and dilation process must cache
the corresponding neighbour pixels in accordance with the structure elements chosen
in order to accomplish it. To achieve the majority of the target detection, we therefore
employes a 5×5 and 3×3 ring structure elements are employed in the erosion module
and dilation module. The number of latches and shift registers depends on the size of
the structural components.
The primary reason for implementing erosion (E) and dilation (D) operation is to
select a 5 × 5 sliding window, that slides the original image line by line and pixel by
pixel, which compares all the pixels to determine the maximum or minimum pixel
value inside the structure elements. Later, the center window pixel value is replaced
by the extremum. Hence, the establishing process of erosion (E) and dilation (D) is
decomposed into pipeline process to achieve the FPGA implementation.
For the erosion (E) procedure to be implemented, a total of 4 shift registers (each 320
length and 8 bits wide), 25 latches, and 11 comparators are required. The image pixels
and erosion template start to match once 1285 original pixels have been transferred,
and after 11 comparisons, the minimum value may be determined. Two 320 long, 8-bit
wide shift registers are needed for the dilation procedure. Following the entry of 643
erosion results, the matching of the input pixels and the dilation template yields the
maximum value after eight comparisons.
 Circuits, Systems, and Signal Processing

Fig. 8 FPGA implementation diagram of top-hat transform

 Circuits, Systems, and Signal Processing

4 Result Analysis

In this work, we conduct tests using the wide-ranging benchmark REalistic Single
Image DEhazing (RESIDE) dataset [14]. This dataset consists of 4,322 real-world
and synthetic hazy images with their corresponding ground truth images. RESIDE
dataset is broken down into five subsets and showcases a variety of data sources and
image contents. The experiment is done on the images from each subset of this dataset.
It is found that the proposed method gives almost similar results on all images in a
particular subset. Out of all images, the result of one image from each subset (five
images in total) is given.
Table 1 represents the comparison of the hardware area utilization. The proposed
method is implemented in Kintex 7 FPGA board from Xilinx. In order to have fair
comparison, all methods are implemented using the same FPGA board. The Xilinx
power estimator tool is used to evaluate power, and the synthesis and implementation
constraints in the Vivado 2019.2 design suite are set to area_opt design to estimate the
area utilization. It is found that the proposed Daub-2 filter uses four adders, two shifters
and zero multipliers due the dyadic coefficients. A total of 4 shift registers, and 11
comparators are required for the implementation of each erosion module on Top-Hat
transform. Similarly, 2 shift registers and 8 comparators are required to implement
one dilation module. 252 modules are used each for erosion and dilation operations.
The first row of the table highlights the references for comparison. while, the rows
from third to twelfth show the count of adders, comparators, multipliers, shifters,
registers, logical cells, throughput (Mpixels/s), clock frequency (MHz), latency (ms),
and the amount of dynamic power (DP) dissipation respectively, of the proposed and
existing methods. It is observed from Table 1 that the proposed method uses less
hardware due the novel Daub-2 filter and optimized thresholding and Top-Hat units.
As a result the proposed techniques consumes 99 mW dynamic power which is less
as compared to other existing methods except the method proposed in [21]. This is
because Samantaray et al. [21] used a dyadic and symmetric Daub-2 wavelet filter.
However, this method [21] gives less peak signal to noise ratio (PSNR) and structural
similarity (SSIM) as compared to the proposed method which is discussed in the next
paragraph. The results discussed in the Table 1 signifies an energy saving work when
compared with the other works. This is made possible by the technique’s high degree
of parallelism, which produces great throughput while the circuit runs at a low clock
frequency.
The performance of the method is measured in both quantitatively and qualitatively.
Peak signal to noise ration (PSNR), root mean square error (RMSE) and structural
similarity (SSIM) are the parameters used for quantitative analysis. The PSNR, RMSE
and SSIM values of the proposed method are computed and compared with the existing
methods. The PSNR, RMSE and SSIM comparisons are shown in Tables 2, 3 and 4,
respectively. It is observed from the tables that the proposed method gives better
PSNR, least RMSE and better SSIM values as compared to the existing methods.
Similarly, the images from the well-known bench mark image dataset [14] are used for
visual comparison. The visual image comparison of the proposed method with existing
methods is given in Fig. 9. It is found in Fig. 9 that some of the output images in [23] and
[11] are still hazy. Also, some output images in [27] method is too dark to distinguish
Table 1 Comparison of hardware consumption of proposed method with existing methods

Particulars Chen et al. [4] Patel et al. [20] Shi et al. [23] Upadhyay et al. Honda et al. [11] Wang et al. [28] Nikam et al. [18] C et al. [12] Samantaray Proposed
[27] et al.[21]
Circuits, Systems, and Signal Processing

Architecture 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
# Adders 198 188 176 168 154 192 172 170 124 129
# Comparators 10784 10654 10522 10446 10252 10714 10584 10582 9246 9576
# Multipliers 14 12 12 10 10 14 12 12 7 8
# Shifters 212 165 162 136 124 224 154 152 150 145
# Registers 5144 4952 4855 4606 4588 4995 4356 4348 4018 4228
# Logic cells 3888 2990 2785 2483 2251 3065 2225 2220 2012 2068
Throughput 74.5 74.3 86.9 94.9 99.0 48.8 78.6 78.4 110.2 108.4
(Mpixels/s)
Frequency (MHz) 80 82.4 88.5 92.4 94 72.5 85.5 85.5 101 100
Latency (ms) 1.18 1.06 1.01 0.96 0.88 1.12 0.98 0.98 0.76 0.78
DP (mW) 138 130 122 117 108 132 121 120 96 99
 Circuits, Systems, and Signal Processing

Table 2 PSNR comparison of the proposed method with other existing methods

Method Canon Cones NY Mountain Trees Average

Chen et al. [4] 28.51 29.85 29.46 29.64 29.01 29.29

Patel et al. [20] 30.12 31.14 30.28 32.15 32.43 31.22
Shi et al. [23] 31.73 30.54 32.52 33.47 35.28 32.71
Upadhyay et al. [27] 38.39 36.40 39.07 42.36 42.86 39.42
Honda et al. [11] 38.19 35.29 38.69 42.51 44.07 39.75
Wang et al. [28] 39.90 37.21 40.92 44.50 44.74 41.55
Nikam et al. [18] 29.92 30.35 30.45 30.66 30.21 30.28
C et al. [12] 35.74 36.05 36.25 36.48 36.15 36.58
Samantaray et al. [21] 39.75 37.02 40.35 44.12 44.22 41.26
Proposed Method 39.93 37.15 41.15 44.60 44.76 41.52

Table 3 RMSE comparison of the proposed method with other existing methods

Method Canon Cones NY Mountain Trees Average

Chen et al. [4] 9.79 9.81 8.61 8.51 9.12 9.17

Patel et al. [20] 8.21 6.49 7.27 6.68 4.45 6.62
Shi et al. [23] 7.32 6.11 6.22 4.24 3.25 5.43
Upadhyay et al. [27] 3.12 4.35 2.95 1.88 1.56 2.77
Honda et al. [11] 3.14 3.92 2.82 1.88 1.82 2.71
Wang et al. [28] 3.08 3.55 2.94 1.71 1.70 2.49
Nikam et al. [18] 7.42 7.52 6.85 6.72 7.64 7.68
C et al. [12] 3.40 3.54 2.99 2.92 3.25 3.32
Samantaray et al. [21] 3.11 3.74 2.96 1.77 1.75 2.60
Proposed method 3.02 3.65 2.70 1.65 1.68 2.54

Table 4 SSIM comparison of the proposed method with other existing methods

Method Canon Cones NY Mountain Trees Average

Chen et al. [4] 0.8864 0.8759 0.8852 0.8796 0.8759 0.8865

Patel et al. [20] 0.9045 0.8996 0.9052 0.9012 0.8995 0.9025
Shi et al. [23] 0.9124 0.9028 0.9124 0.9146 0.9052 0.9154
Upadhyay et al. [27] 0.9248 0.9152 0.9195 0.9201 0.9155 0.9238
Honda et al. [11] 0.9365 0.9256 0.9208 0.9260 0.9128 0.9284
Wang et al. [28] 0.9546 0.9486 0.9608 0.9684 0.9492 0.9588
Nikam et al. [18] 0.9115 0.9014 0.9156 0.9058 0.9188 0.9195
C et al. [12] 0.9466 0.9405 0.9458 0.9412 0.9428 0.9468
Samantaray et al. [21] 0.9532 0.9464 0.9598 0.9670 0.9485 0.9582
Proposed method 0.9556 0.9475 0.9612 0.9688 0.9496 0.9590
Circuits, Systems, and Signal Processing

Fig. 9 Comparison of proposed method with other existing method in terms of visual analysis

between different objects in the images. However, the proposed method retained fine
details of the images and gives better visual quality of the images as compared to
other existing methods. It is also found that the deep learning technique proposed
by Wang et al. [28] gives comparable result as compared to the proposed method in
terms of PSNR, RMSE and SSIM. However, this method consumes more hardware
and dynamic power due to its complex computations. C et al. [12] and Nikam et al.
[18] proposed image enhancement techniques using Daubechies filter. It is found from
the result analysis that these methods consume more hardware and dynamic power
due to the irrational coefficients of original Daubechies filter. Similarly, the method
proposed by Samantaray et al. [21] produces less PSNR and SSIM as compared to
the proposed method. This is due to more error introduced in perfect reconstruction
condition while designing the Daub-2 filter in order to get dyadic and symmetric filter
co-efficients. Hence, result of the proposed method can be used for further image
processing techniques such as segmentation, feature extraction etc. effectively.

5 Conclusion

In this research, we deliver a novel method for FPGA implementation for image
enhancement that effectively denoises high-pass sub-bands and enhances low-pass
 Circuits, Systems, and Signal Processing

sub-bands using a new Daub-2 wavelet transform and mathematical morphology

methods. This paper makes two significant contributions. The first contribution is
the addition of a new Daub-2 wavelet transform, which decomposes the image into
high-pass sub-bands and low-pass sub-bands to help in reconstruction while preserving
more of the image’s more refined features. The second contribution involves processing
high-pass sub-band images with adaptive thresholding and low-pass sub-band images
with top-hat transform. All the algorithms are implemented in Kintex 7 FPGA board
from Xilinx. The comparison of hardware consumption of the proposed method with
other existing method shows utilization of less hardware and less power. Experimental
results indicate that the method effectively preserves the edge characteristics of the
original image while enhancing its contrast. In the meantime, the qualitative and quan-
titative experimental findings show that our suggested strategy significantly improves
feature restoration, image contrast, and high clarity. The suggested approach is impor-
tant since it may be used for image classification, feature extraction, and pre-processing
for segmentation.
Acknowledgements This work was supported by the National Research Foundation of Korea(NRF) grant
funded by the Korea government(MSIT)(NRF-2022R1F1A1063656). The chip fabrication and EDA tool
were supported by the IC Design Education Center(IDEC), Korea.

Data Availability The data that support the findings of this study are available in [14].

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 Circuits, Systems, and Signal Processing

Authors and Affiliations

Md Tarikul Islam1 · Aswini Kumar Samantaray2 · Pradeep Gorre3 ·

Deepak Naik Jatoth1 · Sandeep Kumar4 · AlaaDdin Al-Shidaifat1 ·
Hanjung Song1

B Aswini Kumar Samantaray

aswini.samantaray@manipal.edu
B Hanjung Song
hjsong@inje.ac.kr
Md Tarikul Islam
tarikulislamdaffodil@gmail.com
Pradeep Gorre
pradeepgorre@gmail.com
Deepak Naik Jatoth
jatothdeepaknaik@gmail.com
Sandeep Kumar
fedrer.engg@gmail.com
AlaaDdin Al-Shidaifat
alaaddin@inje.ac.kr
1 Department of Nano Science and Engineering, Centre for Nano Manufacturing, Inje University,
Gimhae 621-749, South Korea
2 Department of Electronics and Communication Engineering, Manipal Institute of Technology
Bengaluru, Manipal Academy of Higher Education, Manipal, India
3 Department of Electronics and Communication Egineering, Vignan’s Foundation for Science,
Technology and Research, Guntur, India
4 Special Centre for Nanosciences, Jawaharlal Nehru University, New Delhi, India