3 mW, 100 kSPS,

16-Bit ADC in 6-Lead SOT-23

AD7680
FEATURES FUNCTIONAL BLOCK DIAGRAM
Fast throughput rate: 100 kSPS VDD
Specified for VDD of 2.5 V to 5.5 V
Low power
16-BIT SUCCESSIVE
3 mW typ at 100 kSPS with 2.5 V supply VIN T/H APPROXIMATION
ADC
3.9 mW typ at 100 kSPS with 3 V supply
16.7 mW typ at 100 kSPS with 5 V supply
SCLK
Wide input bandwidth AD7680 CONTROL
SDATA
LOGIC
86 dB SNR at 10 kHz input frequency CS

03643-0-001
Flexible power/serial clock speed management
No pipeline delays GND

High speed serial interface

Figure 1.
SPI®/QSPI™/μWire/DSP compatible
Standby mode: 0.5 μA max
6-Lead SOT-23 and 8-Lead MSOP packages Table 1. MSOP/SOT-23 16-Bit PulSAR ADC
APPLICATIONS Type/kSPS 100 kSPS 250 kSPS 500 kSPS
Battery-powered systems: True Differential AD7684 AD7687 AD7688
Personal digital assistants Pseudo Differential AD7683 AD7685 AD7686
Medical instruments Unipolar AD7680
Mobile communications
Instrumentation and control systems
Remote data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD7680 is a 16-bit, fast, low power, successive 1. First 16-bit ADC in a SOT-23 package.
approximation ADC. The part operates from a single 2.5 V to
2. High throughput with low power consumption.
5.5 V power supply and features throughput rates up to 100 kSPS.
The part contains a low noise, wide bandwidth track-and-hold 3. Flexible power/serial clock speed management. The
amplifier that can handle input frequencies in excess of 7 MHz. conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
The conversion process and data acquisition are controlled speed increase. This allows the average power consumption
using CS and the serial clock, allowing the devices to interface to be reduced when a power-down mode is used while not
with microprocessors or DSPs. The input signal is sampled on converting. The part also features a shutdown mode to
the falling edge of CS and the conversion is also initiated at this maximize power efficiency at lower throughput rates.
point. There are no pipeline delays associated with the part. Power consumption is 0.5 μA max when in shutdown.

The AD7680 uses advanced design techniques to achieve very 4. Reference derived from the power supply.
low power dissipation at fast throughput rates. The reference for
5. No pipeline delays.
the part is taken internally from VDD, which allows the widest
dynamic input range to the ADC. Thus, the analog input range This part features a standard successive approximation ADC
for this part is 0 V to VDD. The conversion rate is determined by with accurate control of the sampling instant via a CS input and
the SCLK frequency. once-off conversion control.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703© 2004-2011 Analog Devices, Inc. All rights reserved.
AD7680

TABLE OF CONTENTS
Specifications..................................................................................... 2 Typical Connection Diagram ................................................... 13

Specifications..................................................................................... 4 Digital Inputs .......................................................................... 13

Timing Specifications....................................................................... 6 Modes of Operation ....................................................................... 14

Absolute Maximum Ratings............................................................ 7 Normal Mode.............................................................................. 14

ESD Caution .................................................................................. 7 Power-Down Mode .................................................................... 15

Pin Configurations and Function Descriptions ........................... 8 Power vs. Throughput Rate ........................................................... 16

Terminology ...................................................................................... 9 Serial Interface ................................................................................ 17

Typical Performance Characteristics ........................................... 10 AD7680 to ADSP-218x .............................................................. 18

Circuit Information ........................................................................ 12 Application Hints ........................................................................... 19

Converter Operation .................................................................. 12 Grounding and Layout .............................................................. 19

Analog Input ............................................................................... 12 Outline Dimensions ....................................................................... 20

ADC Transfer Function ................................................................. 13 Ordering Guide .......................................................................... 21

REVISION HISTORY
5/11—Rev. 0 to Rev. A
Deleted the Evaluating the AD7680 Performance Section ...... 19
Changes to Ordering Guide .......................................................... 21

1/04—Revision 0: Initial Version

Rev. A | Page 2 of 24
 AD7680

SPECIFICATIONS 1
Table 2. VDD = 4.5 V to 5.5 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted
Parameter A, B Versions1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD) 2 83 dB min
85 dB typ
Signal-to-Noise Ratio (SNR)2 84 dB min
86 dB typ
Total Harmonic Distortion (THD)2 −97 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −95 dB typ
Intermodulation Distortion (IMD)2
Second-Order Terms −94 dB typ
Third-Order Terms −100 dB typ
Aperture Delay 20 ns max
Aperture Jitter 30 ps typ
Full Power Bandwidth 8 MHz typ @ −3 dB
2.2 MHz typ @ −0.1 dB
DC ACCURACY
No Missing Codes 15 Bits typ
Integral Nonlinearity2 ±4 LSB typ
Offset Error2 ±1.68 mV max
Gain Error2 ±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to VDD V
DC Leakage Current ±0.3 μA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, VINH 2.8 V min
Input Low Voltage, VINL 0.4 V max
Input Current, IIN ±0.3 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN2, 3 10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 μA
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±0.3 μA max
Floating-State Output Capacitance2, 3 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 μs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 μs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 μs max
400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 kSPS See the Serial Interface section
POWER REQUIREMENTS
VDD 4.5/5.5 V min/V max
IDD Digital I/PS = 0 V or VDD
Normal Mode (Static) 5.2 mA max SCLK on or off. VDD = 5.5 V
Normal Mode (Operational) 4.8 mA max fSAMPLE = 100 kSPS. VDD = 5.5 V; 3.3 mA typ
Full Power-Down Mode 0.5 μA max SCLK on or off. VDD = 5.5 V
Power Dissipation 4 VDD = 5.5 V
Normal Mode (Operational) 26.4 mW max fSAMPLE = 100 kSPS
Full Power-Down 2.75 μW max

1
Temperature range as follows: B Version: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.

Rev. A | Page 3 of 24
AD7680

SPECIFICATIONS 1
Table 3. VDD = 2.5 V to 4.096 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.
Parameter A Version1 B Version1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD) 2 83 83 dB min VDD = 4.096 V
82 82 dB min VDD = 2.5 V to 3.6 V
86 86 dB typ
Signal-to-Noise Ratio (SNR)2 84 84 dB min VDD = 4.096 V
83 83 dB min VDD = 2.5 V to 3.6 V
86 86 dB typ
Total Harmonic Distortion (THD) 2 −98 −98 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −95 −99 dB typ
Intermodulation Distortion (IMD)2
Second-Order Terms −94 −94 dB typ
Third-Order Terms −100 −100 dB typ
Aperture Delay 20 10 ns max
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 7 7 MHz typ @ −3 dB; VDD = 4.096 V
5 5 MHz typ @ −3 dB; VDD = 2.5 V to 3.6 V
2 2 MHz typ @ −0.1 dB; VDD = 4.096 V
1.6 1.6 MHz typ @ −0.1 dB; VDD = 2.5 V to 3.6 V
DC ACCURACY
No Missing Codes 14 15 Bits min
Integral Nonlinearity2 ±3.5 ±3.5 LSB max VDD = 4.096 V
±3 ±3 LSB max VDD = 2.5 V to 3.6 V
Offset Error2 ±1.25 ±1.25 mV max VDD = 4.096 V
±1.098 ±1.098 mV max VDD = 2.5 V to 3.6 V
Gain Error2 ±0.038 ±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to VDD 0 to VDD V
DC Leakage Current ±0.3 ±0.3 μA max
Input Capacitance 30 30 pF typ
LOGIC INPUTS
Input High Voltage, VINH 2.4 2.4 V min
Input Low Voltage, VINL 0.4 0.4 V max
Input Current, IIN ±0.3 ±0.3 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN2, 3 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD − 0.2 VDD − 0.2 V min ISOURCE = 200 μA
Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±0.3 ±0.3 μA max
Floating-State Output Capacitance2, 3 10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 8 μs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 9.6 μs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 1.5 μs max Full-scale step input
400 400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 100 kSPS See the Serial Interface section

Rev. A | Page 4 of 24
 AD7680
Parameter A Version1 B Version1 Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.5/4.096 2.5/4.096 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2.8 2.8 mA max SCLK on or off; VDD = 4.096 V
2 2 mA max SCLK on or off; VDD = 3.6 V
Normal Mode (Operational) 2.6 2.6 mA max fSAMPLE = 100 kSPS; VDD = 4.096 V; 1.75 mA typ
1.9 1.9 mA max fSAMPLE = 100 kSPS; VDD = 3.6 V; 1.29 mA typ
Full Power-Down Mode 0.3 0.3 μA max SCLK on or off
Power Dissipation 4
Normal Mode (Operational) 10.65 10.65 mW max fSAMPLE = 100 kSPS; VDD = 4.096 V
6.84 6.84 mW max fSAMPLE = 100 kSPS; VDD = 3.6 V
3 3 mW typ VDD = 2.5 V
Full Power-Down 1.23 1.23 μW max VDD = 4.096V
1.08 1.08 μW max VDD = 3.6 V

1
Temperature range as follows: A, B Versions: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.

Rev. A | Page 5 of 24
AD7680

TIMING SPECIFICATIONS 1
Table 4. VDD = 2.5 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter 3V 5V Unit Description
fSCLK 2 250 250 kHz min
2.5 2.5 MHz max
tCONVERT 20 × tSCLK 20 × tSCLK min
tQUIET 100 100 ns min Minimum quiet time required between bus relinquish and start of next conversion
t1 10 10 ns min Minimum CS pulse width
t2 10 10 ns min CS to SCLK setup time
t3 3 48 35 ns max Delay from CS until SDATA three-state disabled
t43 120 80 ns max Data access time after SCLK falling edge
t5 0.4 tSCLK 0.4 tSCLK ns min SCLK low pulse width
t6 0.4 tSCLK 0.4 tSCLK ns min SCLK high pulse width
t7 10 10 ns min SCLK to data valid hold time
t8 4 45 35 ns max SCLK falling edge to SDATA high impedance
tPOWER-UP 5 1 1 μs typ Power up time from full power-down

1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power vs. Throughput Rate section.

200μA IOL

TO OUTPUT 1.6V
PIN CL
50pF
03643-0-002

200μA IOH

Figure 2. Load Circuit for Digital Output Timing Specification

Rev. A | Page 6 of 24
 AD7680

ABSOLUTE MAXIMUM RATINGS

Table 5. TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
VDD to GND −0.3 V to +7 V rating only; functional operation of the device at these or any
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V other conditions above those listed in the operational sections
Digital Input Voltage to GND −0.3 V to +7 V of this specification is not implied. Exposure to absolute
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect
Input Current to Any Pin Except Supplies1 ±10 mA device reliability.
Operating Temperature Range
Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOT-23 Package, Power Dissipation 450 mW
θJA Thermal Impedance 229.6°C/W
θJC Thermal Impedance 91.99°C/W
MSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infared (15 secs) 220°C
ESD 2 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 7 of 24
AD7680

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SOT-23 MSOP

VDD 1 6 CS VDD 1 8 CS
GND 2 AD7680 5 SDATA GND 2 AD7680 7 SDATA

03643-0-003
TOP VIEW TOP VIEW
VIN 3 (Not to Scale) 4 SCLK GND 3 (Not to Scale) 6 NC

03643-0-022
VIN 4 5 SCLK

Figure 3. SOT-23 Pin Configuration NC = NO CONNECT

Figure 4. MSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Pin No.
SOT-23 MSOP Mnemonic Function
1 1 VDD Power Supply Input. The VDD range for the AD7680 is from 2.5 V to 5.5 V.
2 2, 3 GND Analog Ground. Ground reference point for all circuitry on the AD7680. All analog input signals should
be referred to this GND voltage.
3 4 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
4 5 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock
input is also used as the clock source for the AD7680's conversion process.
5 7 SDATA Data Out. Logic output. The conversion result from the AD7680 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7680 consists of four leading zeros followed by 16 bits of conversion data that are provided MSB
first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the
Serial Interface section.
6 8 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7680 and framing the serial data transfer.
N/A 6 NC No Connect. This pin should be left unconnected.

Rev. A | Page 8 of 24
 AD7680

TERMINOLOGY
Integral Nonlinearity Total Harmonic Distortion (THD)
This is the maximum deviation from a straight line passing THD is the ratio of the rms sum of harmonics to the
through the endpoints of the ADC transfer function. The fundamental. For the AD7680, it is defined as
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point V2 2 + V3 2 + V4 2 + V5 2 + V6 2
THD (dB) = 20 log
1/2 LSB above the last code transition. V1

Differential Nonlinearity where V1 is the rms amplitude of the fundamental and V2, V3,
This is the difference between the measured and the ideal 1 LSB V4, V5, and V6 are the rms amplitudes of the second through the
change between any two adjacent codes in the ADC. sixth harmonics.

Offset Error Peak Harmonic or Spurious Noise

This is the deviation of the first code transition (00 . . . 000) to Peak harmonic or spurious noise is defined as the ratio of the
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB. rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
Gain Error fundamental. Normally, the value of this specification is
This is the deviation of the last code transition (111 . . . 110) to determined by the largest harmonic in the spectrum, but for
(111 . . . 111) from the ideal (i.e., VREF − 1 LSB) after the offset ADCs where the harmonics are buried in the noise floor, it is a
error has been adjusted out. noise peak.
Track-and-Hold Acquisition Time Intermodulation Distortion
The track-and-hold amplifier returns to track mode at the end With inputs consisting of sine waves at two frequencies, fa and fb,
of conversion. The track-and-hold acquisition time is the time any active device with nonlinearities creates distortion products
required for the output of the track-and-hold amplifier to reach at the sum and difference frequencies of mfa ± nfb where m, n =
its final value, within ±1 LSB, after the end of the conversion. 0, 1, 2, 3. Intermodulation distortion terms are those for which
See the Serial Interface section for more details. neither m nor n are equal to zero. For example, the second-order
Signal-to-(Noise + Distortion) Ratio terms include (fa + fb) and (fa − fb), while the third-order terms
This is the measured ratio of signal-to-(noise + distortion) at include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb).
the output of the ADC. The signal is the rms amplitude of the The AD7680 is tested using the CCIF standard where two input
fundamental. Noise is the sum of all nonfundamental signals up frequencies near the top end of the input bandwidth are used.
to half the sampling frequency (fS/2, excluding dc). The ratio In this case, the second-order terms are usually distanced in
depends on the number of quantization levels in the digitization frequency from the original sine waves, while the third-order
process; the more levels, the smaller the quantization noise. The terms are usually at a frequency close to the input frequencies.
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit As a result, the second- and third-order terms are specified
converter with a sine wave input is given by separately. The calculation of the intermodulation distortion is
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
Thus, for a 16-bit converter, this is 98 dB. of the sum of the fundamentals expressed in dBs.

Rev. A | Page 9 of 24
AD7680

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 shows a typical FFT plot for the AD7680 at 100 kSPS Figure 7 shows a graph of the total harmonic distortion versus
sample rate and 10 kHz input frequency. Figure 6 shows the the analog input frequency for various supply voltages, while
signal-to-(noise + distortion) ratio performance versus the Figure 8 shows a graph of the total harmonic distortion versus
input frequency for various supply voltages while sampling at the analog input frequency for various source impedances (see
100 kSPS with an SCLK of 2.5 MHz. the Analog Input section). Figure 9 and Figure 10 show the
typical INL and DNL plots for the AD7680.

0 110
VDD = 5V FSAMPLE = 100kSPS
FSAMPLE = 100kSPS TA = 25°C
–20 FIN = 10kHz
SNR = 88.28dB
–40 SINAD = 87.82dB 105
THD = –97.76dB VDD = 4.3V
SFDR = –98.25dB
–60 VDD = 4.75V

THD (dB)
VDD = 3.6V
dB

–80 100
VDD = 5.25V

–100 VDD = 3.0V

VDD = 2.7V
–120 95
VDD = 2.5V
03643-0-021

03643-0-017
–140

–160 90
0 10k 20k 30k 40k 50k 10 100
FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 5. AD7680 Dynamic Performance at 100 kSPS Figure 7. AD7680 THD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS
95 110
FSAMPLE = 100kSPS
TA = 25°C RIN = 10Ω
105

100
90 RIN = 50Ω
VDD = 5.25V
95
THD (dB)
SINAD (dB)

RIN = 100Ω
90
VDD = 4.75V

85 VDD = 4.3V 85
VDD = 3.6V
FSAMPLE = 100kSPS
03643-0-018
VDD = 3.0V 80
TA = 25°C
03643-0-016

RIN = 1000Ω
VDD = 4.75V
VDD = 2.7V
VDD = 2.5V 75
80 10 100
10 100 INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)

Figure 6. AD7680 SINAD vs. Analog Input Frequency Figure 8. AD7680 THD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS for Various Source Impedances

Rev. A | Page 10 of 24
 AD7680
2.5 1.5
VDD = 3.0V VDD = 3.0V
TEMP = 25°C TEMP = 25°C
2.0
1.0

1.5
0.5

DNL ERROR (LSB)

INL ERROR (LSB)

1.0
0
0.5

–0.5
0

–1.0

03643-0-019

03643-0-020
–0.5

–1.0 –1.5
0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000
CODE CODE

Figure 9. AD7680 Typical INL Figure 10. AD7680 Typical DNL

Rev. A | Page 11 of 24
AD7680

CIRCUIT INFORMATION
The AD7680 is a fast, low power, 16-bit, single-supply ADC. The CAPACITIVE
part can be operated from a 2.5 V to 5.5 V supply and is capable of DAC

throughput rates of 100 kSPS when provided with a 2.5 MHz clock. A SAMPLING
CAPACITOR
VIN
SW1
CONTROL
The AD7680 provides the user with an on-chip track-and-hold B
LOGIC
CONVERSION SW2

03643-0-005
ADC and a serial interface housed in a tiny 6-lead SOT-23 PHASE
COMPARATOR
package or in an 8-lead MSOP package, which offer the user VDD/2

considerable space-saving advantages over alternative solutions.

Figure 12. ADC Conversion Phase
The serial clock input accesses data from the part and also
provides the clock source for the successive approximation ANALOG INPUT
ADC. The analog input range for the AD7680 is 0 V to VDD. An Figure 13 shows an equivalent circuit of the analog input
external reference is not required for the ADC nor is there a structure of the AD7680. The two diodes, D1 and D2, provide
reference on-chip. The reference for the AD7680 is derived from ESD protection for the analog inputs. Care must be taken to
the power supply and thus gives the widest dynamic input range. ensure that the analog input signal never exceeds the supply
The AD7680 also features a power-down option to save power rails by more than 300 mV. This causes these diodes to become
between conversions. The power-down feature is implemented forward-biased and to start conducting current into the
across the standard serial interface as described in the Modes of substrate. The maximum current these diodes can conduct
Operation section. without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 13 is typically about 5 pF and can be
CONVERTER OPERATION attributed primarily to pin capacitance. Resistor R1 is a lumped
The AD7680 is a 16-bit, successive approximation ADC based component made up of the on resistance of a track-and-hold
around a capacitive DAC. The AD7680 can convert analog switch. This resistor is typically about 25 Ω. Capacitor C2 is the
input signals in the 0 V to VDD range. Figure 11 and Figure 12 ADC sampling capacitor and has a capacitance of 25 pF
show simplified schematics of the ADC. The ADC comprises typically. For ac applications, removing high frequency
control logic, SAR, and a capacitive DAC. Figure 11 shows the components from the analog input signal is recommended by
ADC during its acquisition phase. SW2 is closed and SW1 is in use of an RC low-pass filter on the relevant analog input pin. In
Position A. The comparator is held in a balanced condition and applications where harmonic distortion and signal-to-noise
the sampling capacitor acquires the signal on the selected VIN ratio are critical, the analog input should be driven from a low
channel. impedance source. Large source impedances significantly affect
the ac performance of the ADC. This may necessitate the use of
CAPACITIVE
an input buffer amplifier. The choice of the op amp is a function
DAC
of the particular application. When no amplifier is used to drive
SAMPLING
VIN
A
CAPACITOR the analog input, the source impedance should be limited to low
SW1
CONTROL
values. The maximum source impedance depends on the
B
ACQUISITION SW2 LOGIC amount of total harmonic distortion (THD) that can be
03643-0-004

PHASE
COMPARATOR
tolerated. The THD increases as the source impedance
VDD/2
increases, and performance degrades (see Figure 8).
Figure 11. ADC Acquisition Phase VDD

When the ADC starts a conversion, SW2 opens and SW1 moves D1
C2
R1 25pF
to Position B, causing the comparator to become unbalanced VIN
(Figure 12). The control logic and the capacitive DAC are used C1 D2
03643-0-006

5pF
to add and subtract fixed amounts of charge from the sampling CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion Figure 13. Equivalent Analog Input Circuit
is complete. The control logic generates the ADC output code
(see the ADC Transfer Function section).

Rev. A | Page 12 of 24
 AD7680

ADC TRANSFER FUNCTION

The output coding of the AD7680 is straight binary. The In fact, because the supply current required by the AD7680 is so
designed code transitions occur at successive integer LSB low, a precision reference can be used as the supply source to
values, i.e., 1 LSB, 2 LSBs. The LSB size is VDD/65536. The ideal the AD7680. For example, a REF19x voltage reference (REF195
transfer characteristic for the AD7680 is shown in Figure 14. for 5 V or REF193 for 3 V) or an AD780 can be used to supply
the required voltage to the ADC (see Figure 15). This
configuration is especially useful if the power supply available is
111...111 quite noisy, or if the system supply voltages are at some value
111...110 other than the required operating voltage of the AD7680, e.g.,
15 V. The REF19x or AD780 outputs a steady voltage to the
111...000
AD7680. Recommended decoupling capacitors are a 100 nF low
1 LSB = VDD/65536 ESR ceramic (Farnell 335-1816) and a 10 μF low ESR tantalum
011...111 (Farnell 197-130).
3V 5V
REF193 SUPPLY
000...010 10F
TANT 0.1F 10F 0.1F
000...001
000...000
03643-0-007

1 LSB +VDD–1 LSB VDD

0V SCLK
ANALOG INPUT
0V TO VDD VIN SDATA C/P
Figure 14. AD7680 Transfer Characteristic
INPUT AD7680
CS
GND
TYPICAL CONNECTION DIAGRAM

03643-0-008
Figure 15 shows a typical connection diagram for the AD7680. SERIAL
VREF is taken internally from VDD and as such should be well INTERFACE

decoupled. This provides an analog input range of 0 V to VDD. Figure 15. Typical Connection Diagram
The conversion result is output in a 24-bit word, or alternatively,
Digital Inputs
all 16 bits of the conversion result may be accessed using a
minimum of 20 SCLKs. This 20-/24-bit data stream consists of The digital inputs applied to the AD7680 are not limited by the
a four leading zeros, followed by the 16 bits of conversion data, maximum ratings that limit the analog inputs. Instead, the
followed by four trailing zeros in the case of the 24 SCLK digital inputs applied can go to 7 V and are not restricted by the
transfer. For applications where power consumption is of VDD + 0.3 V limit as on the analog inputs. For example, if the
concern, the power-down mode should be used between AD7680 were operated with a VDD of 3 V, 5 V logic levels could
conversions or bursts of several conversions to improve power be used on the digital inputs. However, it is important to note
performance (see the Modes of Operation section). that the data output on SDATA still has 3 V logic levels when
VDD = 3 V.

Another advantage of SCLK and CS not being restricted by the

VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If one of these digital inputs is applied before VDD, then
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to VDD.

Rev. A | Page 13 of 24
AD7680

MODES OF OPERATION
The mode of operation of the AD7680 is selected by controlling The conversion is initiated on the falling edge of CS as described
the (logic) state of the CS signal during a conversion. There are in the Serial Interface section. To ensure that the part remains
two possible modes of operation, normal and power-down. The fully powered up at all times, CS must remain low until at least
point at which CS is pulled high after the conversion has been 10 SCLK falling edges have elapsed after the falling edge of CS.
initiated determines whether or not the AD7680 enters power- If CS is brought high any time after the 10th SCLK falling edge,
down mode. Similarly, if the AD7680 is already in power-down, but before the 20th SCLK falling edge, the part remains
CS can control whether the device returns to normal operation powered up, but the conversion is terminated and SDATA goes
or remains in power-down. These modes of operation are back into three-state. At least 20 serial clock cycles are required
designed to provide flexible power management options. These to complete the conversion and access the complete conversion
options can optimize the power dissipation/throughput rate result. In addition, a total of 24 SCLK cycles accesses four
ratio for differing application requirements. trailing zeros. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
NORMAL MODE
conversion, effectively idling CS low.
This mode provides the fastest throughput rate performance,
because the user does not have to worry about the power-up Once a data transfer is complete (SDATA has returned to three-
times with the AD7680 remaining fully powered all the time. state), another conversion can be initiated after the quiet time,
Figure 16 shows the general diagram of the operation of the tQUIET, has elapsed by bringing CS low again.
AD7680 in this mode.

CS

1 10 20
SCLK

03643-0-009
SDATA 4 LEADING ZEROS + CONVERSION RESULT

Figure 16. Normal Mode Operation

Rev. A | Page 14 of 24
 AD7680
POWER-DOWN MODE
This mode is intended for use in applications where slower In order to exit this mode of operation and power up the
throughput rates are required. Either the ADC is powered AD7680 again, a dummy conversion is performed. On the
down between each conversion, or a series of conversions may falling edge of CS, the device begins to power up and continues
be performed at a high throughput rate, and then the ADC is to power up as long as CS is held low until after the falling edge
powered down for a relatively long duration between these of the 10th SCLK. The device is fully powered up once at least
bursts of several conversions. When the AD7680 is in 16 SCLKs (or approximately 6 μs) have elapsed and valid data
power-down, all analog circuitry is powered down. results from the next conversion as shown in Figure 18. If CS is
brought high before the 10th falling edge of SCLK, regardless of
To enter power-down, the conversion process must be
the SCLK frequency, the AD7680 goes back into power-down
interrupted by bringing CS high anywhere after the second
again. This avoids accidental power-up due to glitches on the
falling edge of SCLK and before the 10th falling edge of SCLK
CS line or an inadvertent burst of 8 SCLK cycles while CS is low.
as shown in Figure 17. Once CS has been brought high in this
So although the device may begin to power-up on the falling
window of SCLKs, the part enters power-down, the conversion
edge of CS, it powers down again on the rising edge of CS as
that was initiated by the falling edge of CS is terminated, and
long as it occurs before the 10th SCLK falling edge.
SDATA goes back into three-state. If CS is brought high before
the second SCLK falling edge, the part remains in normal mode
and will not power down. This avoids accidental power-down
due to glitches on the CS line.

CS

1 2 10 20

SCLK

03643-0-010
THREE-STATE
SDATA

Figure 17. Entering Power-Down Mode

THE PART IS FULLY POWERED

UP WITH VIN FULLY ACQUIRED
THE PART BEGINS
TO POWER UP tPOWER UP

CS

1 10 20 1 20

SCLK
03643-0-011

SDATA INVALID DATA VALID DATA

Figure 18. Exiting Power-Down Mode

Rev. A | Page 15 of 24
AD7680

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7680 when not Figure 19 shows the power dissipation versus the throughput
converting, the average power consumption of the ADC rate when using the power-down mode with 3.6 V supplies, a
decreases at lower throughput rates. Figure 19 shows how as the 2.5 MHz SCLK, and a 20 SCLK serial transfer.
throughput rate is reduced, the part remains in its shut-down 10
VDD = 3.6V
state longer, and the average power consumption over time FSCLK = 2.5MHz
drops accordingly.

For example, if the AD7680 is operated in a continuous

1
sampling mode, with a throughput rate of 10 kSPS and an SCLK

POWER (mW)
of 2.5 MHz (VDD = 3.6 V), and the device is placed in power-
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
0.1
normal operation is 6.84 mW (VDD = 3.6 V). If the power-up
time from power-down is 1 μs, and the remaining conversion

03643-0-012
time is 8 μs, (using a 20 SCLK transfer), then the AD7680 can
be said to dissipate 6.84 mW for 9 μs during each conversion
0.01
cycle. With a throughput rate of 10 kSPS, the cycle time is 100 0 5 10 15 20 25 30 35 40 45 50
μs. THROUGHPUT (kSPS)

For the remainder of the conversion cycle, 91 μs, the part Figure 19. Power vs. Throughput Using
remains in power-down mode. The AD7680 can be said to Power-Down Mode with 20 SCLK Transfer at 3.6 V
dissipate 1.08 μW for the remaining 91 μs of the conversion
cycle. Therefore, with a throughput rate of 10 kSPS, the average
power dissipated during each cycle is

(9/100) × (6.84 mW) + (91/100) × (1.08 μW) = 0.62 mW

Rev. A | Page 16 of 24
 AD7680

SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial A minimum of 20 serial clock cycles are required to perform
interfacing to the AD7680. The serial clock provides the the conversion process and to access data from the AD7680.
conversion clock and also controls the transfer of information CS going low provides the first leading zero to be read in by the
from the AD7680 during conversion. microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
The CS signal initiates the data transfer and conversion process. leading zero; thus the first falling clock edge on the serial clock
The falling edge of CS puts the track-and-hold into hold mode, has the first leading zero provided and also clocks out the
takes the bus out of three-state, and samples the analog input. second leading zero. If a 24 SCLK transfer is used as in Figure 20,
The conversion is also initiated at this point and requires at least the data transfer consists of four leading zeros followed by the
20 SCLK cycles to complete. Once 17 SCLK falling edges have 16 bits of data, followed by four trailing zeros. The final bit
elapsed, the track-and-hold goes back into track mode on the (fourth trailing zero) in the data transfer is valid on the 24th
next SCLK rising edge. Figure 20 shows a 24 SCLK transfer that falling edge, having been clocked out on the previous (23rd)
allows a 100 kSPS throughput rate. On the 24th SCLK falling falling edge. If a 20 SCLK transfer is used as shown in Figure 21,
edge, the SDATA line goes back into three-state. If the rising the data output stream consists of only four leading zeros
edge of CS occurs before 24 SCLKs have elapsed, the conversion followed by 16 bits of data with the final bit valid on the 20th
terminates and the SDATA line goes back into three-state; SCLK falling edge. A 20 SCLK transfer allows for a shorter cycle
otherwise SDATA returns to three-state on the 24th SCLK time and therefore a faster throughput rate is achieved.
falling edge as shown in Figure 20.

t1
CS
tCONVERT
t2 t6
1 2 3 4 5 18 19 20 21 22 23 24
SCLK
t5 t8
t3 t4 t7
tQUIET
SDATA 0 ZERO ZERO ZERO DB15 DB1 DB0 ZERO ZERO ZERO ZERO

03643-0-013
3-STATE 3-STATE
4 LEADING ZEROS 4 TRAILING ZEROS

Figure 20. AD7680 Serial Interface Timing Diagram—24 SCLK Transfer

t1
CS
tCONVERT
t2 t6
SCLK 1 2 3 4 5 18 19 20
t5 t8
t7
t3 t4 tQUIET
SDATA 0 ZERO ZERO ZERO DB15 DB1 DB0 0
03643-0-014

3-STATE 3-STATE

4 LEADING ZEROS

Figure 21. AD7680 Serial Interface Timing Diagram—20 SCLK Transfer

Rev. A | Page 17 of 24
AD7680
It is also possible to take valid data on each SCLK rising edge an input. The DSP operates in alternate framing mode and the
rather than falling edge, since the SCLK cycle time is long SPORT control register is set up as described. Transmit and
enough to ensure the data is ready on the rising edge of SCLK. receive autobuffering is used in order to get a 24 SCLK transfer.
However, the first leading zero is still driven by the CS falling Each buffer contains three 8-bit words. The frame synchroniza-
edge, and so it can be taken on only the first SCLK falling edge. tion signal generated on the TFS is tied to CS, and as with all
It may be ignored and the first rising edge of SCLK after the CS signal processing applications, equidistant sampling is necessary.
falling edge would have the second leading zero provided and In this example, the timer interrupt is used to control the
the 23rd rising SCLK edge would have the final trailing zero sampling rate of the ADC.
provided. This method may not work with most
AD7680* ADSP-218x*
microcontrollers/DSPs but could possibly be used with FPGAs
SCLK SCLK
and ASICs.
SDATA DR
AD7680 TO ADSP-218x CS RFS

03643-0-015
The ADSP-218x family of DSPs can be interfaced directly to the TFS
AD7680 without any glue logic required. The SPORT control
*ADDITIONAL PINS OMITTED FOR CLARITY
register should be set up as follows:
Figure 22. Interfacing to the ADSP-218x
TFSW = RFSW = 1, Alternate Framing
The timer register is loaded with a value that provides an
INVRFS = INVTFS = 1, Active Low Frame Signal interrupt at the required sample interval. When an interrupt is
received, the values in the transmit autobuffer start to be
DTYPE = 00, Right Justify Data
transmitted and TFS is generated. The TFS is used to control
SLEN = 0111, 8-Bit Data-Words the RFS and therefore the reading of data. The data is stored in
the receive autobuffer for processing or to be shifted later. The
ISCLK = 1, Internal Serial Clock frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given, i.e.,
TFSR = RFSR = 0, Frame First Word
TX0 = AX0, the state of the SCLK is checked. The DSP waits
IRFS = 0 until the SCLK has gone high, low, and high again before
transmission starts. If the timer and SCLK values are chosen
ITFS = 1 such that the instruction to transmit occurs on or near the
rising edge of SCLK, the data may be transmitted or it may wait
To implement the power-down mode, SLEN should be set to
until the next clock edge.
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 22. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as

Rev. A | Page 18 of 24
 AD7680

APPLICATION HINTS
GROUNDING AND LAYOUT as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
The printed circuit board that houses the AD7680 should be should never be run near the analog inputs. Avoid crossover of
designed such that the analog and digital sections are separated digital and analog signals. Traces on opposite sides of the board
and confined to certain areas of the board. This facilitates the should run at right angles to each other, which reduces the
use of ground planes that can be separated easily. A minimum effects of feedthrough on the board. A microstrip technique is
etch technique is generally best for ground planes, because it by far the best but is not always possible with a double-sided
gives the best shielding. Digital and analog ground planes board. In this technique, the component side of the board is
should be joined at only one place. If the AD7680 is in a system dedicated to ground planes while the signals are placed on the
where multiple devices require an AGND to DGND solder side.
connection, the connection should still be made at one point
only, a star ground point that should be established as close as Good decoupling is also very important. All analog supplies
possible to the AD7680. should be decoupled with 10 μF tantalum in parallel with
0.1 μF capacitors to AGND, as discussed in the Typical
Avoid running digital lines under the device because these
Connection Diagram section. To achieve the best performance
couple noise onto the die. The analog ground plane should be from these decoupling components, the user should attempt to
allowed to run under the AD7680 to avoid noise coupling. The keep the distance between the decoupling capacitors and the
power supply lines to the AD7680 should use as large a trace as VDD and GND pins to a minimum, with short track lengths
possible to provide low impedance paths and reduce the effects connecting the respective pins.
of glitches on the power supply line. Fast switching signals, such

Rev. A | Page 19 of 24
AD7680

OUTLINE DIMENSIONS
3.00
2.90
2.80

6 5 4 3.00
1.70
1.60 2.80
1.50 2.60
1 2 3

PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX 0.20 MAX
0.95 MIN 0.08 MIN
0.55
0.15 MAX 10° 0.45
0.05 MIN SEATING 4° 0.60
0.50 MAX PLANE BSC 0.35
0.30 MIN 0°

12-16-2008-A
COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 23. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters
3.20
3.00
2.80

8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4

PIN 1
IDENTIFIER

0.65 BSC

0.95 15° MAX

0.85 1.10 MAX
0.75
0.80
0.15 6° 0.23
0.40 0.55
0.05 0° 0.09 0.40
COPLANARITY 0.25
10-07-2009-B

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 24. 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters

Rev. A | Page 20 of 24
 AD7680
ORDERING GUIDE
Temperature Linearity Package
Model1 Range Error (LSB)2 Package Description Option Branding
AD7680ARJZ-REEL7 −40°C to +85°C 14 Bits Min 6-Lead Small Outline Transistor Package (SOT-23) RJ-6 C40
AD7680ARM −40°C to +85°C 14 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQA
AD7680ARM-REEL −40°C to +85°C 14 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQA
AD7680ARM-REEL7 −40°C to +85°C 14 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQA
AD7680ARMZ −40°C to +85°C 14 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 C40
AD7680BRJZ-R2 −40°C to +85°C 15 Bits Min 6-Lead Small Outline Transistor Package (SOT-23) RJ-6 C3H
AD7680BRJZ-REEL7 −40°C to +85°C 15 Bits Min 6-Lead Small Outline Transistor Package (SOT-23) RJ-6 C3H
AD7680BRM −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQB
AD7680BRM-REEL −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQB
AD7680BRM-REEL7 −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 CQB
AD7680BRMZ −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 C3H
AD7680BRMZ-REEL −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 C3H
AD7680BRMZ-REEL7 −40°C to +85°C 15 Bits Min 8-Lead Mini Small Outline Package (MSOP) RM-8 C3H

1
Z = RoHS Compliant Part.
2
Linearity error here refers to no missing codes.

Rev. A | Page 21 of 24
AD7680

NOTES

Rev. A | Page 22 of 24
 AD7680

NOTES

Rev. A | Page 23 of 24
AD7680

NOTES

© 2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D03643-0-5/11(A)

Rev. A | Page 24 of 24