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4GB, 8GB, 16GB, 32GB: e·MMC

Features

e·MMC™ Memory
MTFC4GLDDQ-4M IT, MTFC8GLDDQ-4M IT
MTFC16GJDDQ-4M IT, MTFC32GJDDQ-4M IT

Features Figure 1: Micron e·MMC Device

• MultiMediaCard (MMC) controller and NAND Flash

• 100-ball LBGA (RoHS 6/6-
compliant)
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V
• Industrial temperature ranges MMC MMC controller MMC
power interface
– Operating temperature: –40˚C to +85˚C
– Storage temperature: –40˚C to +85˚C
• Typical current consumption
– Standby current: 70μA (4GB, 8GB); 90µA (16GB,
32GB)
– Active current (RMS): 70mA (4GB, 8GB); 90mA NAND Flash
power NAND Flash
(16GB, 32GB)

MMC-Specific Features
• JEDEC/MMC standard version 4.41-compliant
(JEDEC Standard No. 84-A441) – SPI mode not
supported (see www.jedec.org/sites/default/files/
docs/JESD84-A441.pdf) MMC-Specific Features (Continued)
– Advanced 11-signal interface – Enhanced reliable write
– x1, x4, and x8 I/Os, selectable by host – Configurable reliability settings
– MMC mode operation – Background operation
– Command classes: class 0 (basic); class 2 (block – Fully enhanced configurable
read); class 4 (block write); class 5 (erase); – Backward-compatible with previous MMC
class 6 (write protection); class 7 (lock card) modes
– MMCplus™ and MMCmobile™ protocols • ECC and block management implemented
– Temporary write protection
– 52 MHz clock speed (MAX)
– Boot operation (high-speed boot)
– Sleep mode
– Replay-protected memory block (RPMB)
– Secure erase and trim
– Hardware reset signal
– Multiple partitions with enhanced attribute
– Permanent and power-on write protection
– Double data rate (DDR) function
– High-priority interrupt (HPI)

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4GB, 8GB, 16GB, 32GB: e·MMC

Features

e·MMC Performance

Table 1: MLC Partition Performance

Part Number
MTFC16GJDDQ-4M IT
Condition MTFC4GLDDQ-4M IT MTFC8GLDDQ-4M IT MTFC32GJDDQ-4M IT Units
Sequential write 6.6 13.5 20 MB/s
Sequential read 30 44 44 MB/s
Random write 90 90 90 IOPs
Random read 1080 1080 1100 IOPs

Note: 1. Bus in x8 I/O mode. Sequential access of 1MB chunk; random access of 4KB chunk. Additional performance
data, such as power consumption or timing for different device modes, will be provided in a separate docu-
ment upon customer request.

Ordering Information

Table 2: Ordering Information

Shipping
Base Part Number Density Package NAND Flash Type Media
MTFC4GLDDQ-4M IT 4GB 100-ball LBGA 1 x 32Gb, MLC, 25nm Tray
14.0mm x 18.0mm x 1.4mm Tape and reel
MTFC8GLDDQ-4M IT 8GB 100-ball LBGA 2 x 32Gb, MLC, 25nm Tray
14.0mm x 18.0mm x 1.4mm Tape and reel
MTFC16GJDDQ-4M IT 16GB 100-ball LBGA 2 x 64Gb, MLC, 25nm Tray
14.0mm x 18.0mm x 1.4mm Tape and reel
MTFC32GJDDQ-4M IT 32GB 100-ball LBGA 4 x 64Gb, MLC, 25nm Tray
14.0mm x 18.0mm x 1.4mm Tape and reel

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Features

Part Numbering Information

Micron®e·MMC memory devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.

Figure 2: Marketing Part Number Chart

MT FC xx x x xx - xx xx x ES

Micron Technology Design Revision

FC = NAND Flash + Controller Production Status
NAND Flash Density Wafer Process Applied
NAND Flash Component Operating Temperature Range
Controller ID Special Options
Package Codes

Note: 1. Not all combinations are necessarily available. For a list of available devices or for further information on
any aspect of these products, please contact your nearest Micron sales office.

Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.

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4GB, 8GB, 16GB, 32GB: e·MMC

General Description

General Description
Micron e·MMC is a communication and mass data storage device that includes a Multi-
MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-
vanced 11-signal bus, which is compliant with the MMC system specification. Its cost
per bit, small package sizes, and high reliability make it an ideal choice for industrial
applications like infrastructure and networking equipment, PC and servers, a variety of
other industrial products.
The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-
ance across a wide range of operating temperatures, and resists shock and vibration dis-
ruption.

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4GB, 8GB, 16GB, 32GB: e·MMC

Signal Descriptions

Signal Descriptions

Table 3: Signal Descriptions

Symbol Type Description

CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-
idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
CMD I/O Command: This signal is a bidirectional command channel used for command and response trans-
fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de-
fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi-
ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
VCC Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ Supply VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
VSS1 Supply VSS: NAND I/F I/O and NAND Flash ground connection.
VSSQ1 Supply VSSQ: e·MMC controller core and e·MMC I/F ground connection.
VDDIM Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF ca-
pacitor is recommended. Do not tie to supply voltage or ground.
NC – No connect: No internal connection is present.
RFU – Reserved for future use: No internal connection is present. Leave it floating externally.

Note: 1. VSS and VSSQ are connected internally.

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100-Ball Signal Assignments

100-Ball Signal Assignments

Figure 3: 100-Ball LFBGA (Top View, Ball Down)

1 2 3 4 5 6 7 8 9 10

A NC NC NC NC A

B NC NC B

D RFU RFU RFU RFU RFU RFU RFU RFU D

E RFU RFU VDDIM RFU RFU RFU RFU RFU E

F VCC VCC VCC VCC VCC VCC VCC VCC F

G VSS VSS VSS VSS VSS VSS VSS VSS G

H VSSQ VCCQ RFU RFU RFU RFU VCCQ VSSQ H

J RFU RFU RFU RFU RFU RFU RFU RFU J

K DAT0 DAT2 RFU RFU RFU RFU DAT5 DAT7 K

L VCCQ VSSQ VCCQ RFU RFU VCCQ VSSQ VCCQ L

M RFU RFU VSSQ RST_n RFU VSSQ RFU RFU M

N DAT1 DAT3 RFU RFU RFU RFU DAT4 DAT6 N

P VSSQ VCCQ RFU CMD CLK RFU VCCQ VSSQ P

T NC NC T

U NC NC NC NC U

Notes: 1. Connect a 1μF decoupling capacitor from VDDI to ground.

2. Some test pads on the device are not shown. They are not solder balls and are for Mi-
cron internal use only.
3. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
4. VCC, VCCQ, VSS, and VSSQ balls must all be connected.

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Package Dimensions

Package Dimensions

Figure 4: 100-Ball LBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DQ)

Seating plane

A 0.12 A

100X Ø0.466
Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on Ø0.40 SMD
ball pads. 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E
F
G
18 ±0.1
H
10.0 CTR
J

16.0 CTR K
L
M
N
P
R
T
1.0 TYP
U

1.0 TYP 1.3 ±0.1

9.0 CTR 0.303 MIN
14 ±0.1
36X Ø0.325 on 0.5 pitch.
Ni/Au plated test pads.
No solder balls.

Notes: 1. Dimensions are in millimeters.

2. Solder ball material: SnAgCu (96.5% Sn, 3% Ag, 0.5% Cu).
3. Test pads are not solder balls and are for Micron internal use only.

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4GB, 8GB, 16GB, 32GB: e·MMC

Architecture

Architecture
Figure 5: e·MMC Functional Block Diagram

e·MMC

MMC VCC
controller VCCQ
RST_n
CMD Registers
DAT[7:0]
CLK
OCR CSD RCA
VDDIM
VSS1
CID ECSD DSR
VSSQ1

NAND Flash

Note: 1. VSS and VSSQ are internally connected.

MMC Protocol Independent of NAND Flash Technology

The MMC specification defines the communication protocol between a host and a de-
vice. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communica-
tion protocol.
The controller also handles block management functions such as logical block alloca-
tion and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.

Defect and Error Management

Micron e·MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.

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CID Register

CID Register
The card identification (CID) register is 128 bits wide. It contains the device identifica-
tion information used during the card identification phase as required by e·MMC proto-
col. Each device is created with a unique identification number.

Table 4: CID Register Field Parameters

Name Field Width CID Bits CID Value

Manufacturer ID MID 8 [127:120] FEh
Reserved – 6 [119:114] –
Card/BGA CBX 2 [113:112] 01h
OEM/application ID OID 8 [111:104] –
Product name PNM 48 [103:56] MMC04G
MMC08G
MMC16G
MMC32G
Product revision PRV 8 [55:48] –
Product serial number PSN 32 [47:16] –
Manufacturing date MDT 8 [15:8] –
CRC7 checksum CRC 7 [7:1] –
Not used; always 1 – 1 0 –

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CSD Register

CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum da-
ta access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following ta-
ble) can be changed by the PROGRAM_CSD (CMD27) command.

Table 5: CSD Register Field Parameters

Cell CSD CSD

Name Field Width Type1 Bits Value
CSD structure CSD_STRUCTURE 2 R [127:126] 03h
System specification version SPEC_VERS 4 R [125:122] 4h
Reserved2 – 2 TBD [121:120] –
Data read access time 1 TAAC 8 R [119:112] 4Fh
Data read access time 2 in CLK cy- NSAC 8 R [111:104] 01h
cles (NSAC × 100)
Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h
Card command classes CCC 12 R [95:84] 0F5h
Maximum read data block length READ_BL_LEN 4 R [83:80] 9h
Partial blocks for reads supported READ_BL_PARTIAL 1 R 79 0h
Write block misalignment WRITE_BLK_MISALIGN 1 R 78 0h
Read block misalignment READ_BLK_MISALIGN 77 R 77 0h
DS register implemented DSR_IMP 1 R 76 1h
Reserved – 2 R [75:74] –
Device size C_SIZE 12 R [73:62] FFFh
Maximum read current at VDD,min VDD_R_CURR_MIN 3 R [61:59] 7h
Maximum read current at VDD,max VDD_R_CURR_MAX 3 R [58:56] 7h
Maximum write current at VDD_W_CURR_MIN 3 R [55:53] 7h
VDD,min
Maximum write current at VDD_W_CURR_MAX 3 R [52:50] 7h
VDD,max
Device size multiplier C_SIZE_MULT 3 R [49:47] 7h
Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh
Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh
Write protect group size WP_GRP_SIZE 4GB 5 R [36:32] 07h
8GB 0Fh
16GB 1Fh
32GB
Write protect group enable WP_GRP_ENABLE 1 R 31 1h
Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h
rite-speed factor R2W_FACTOR 3 R [28:26] 2h

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CSD Register

Table 5: CSD Register Field Parameters (Continued)

Cell CSD CSD

Name Field Width Type1 Bits Value
Maximum write data block WRITE_BL_LEN 4 R [25:22] 9h
length
Partial blocks for writes suppor- WRITE_BL_PARTIAL 1 R 21 0h
ted
Reserved – 4 R [20:17] –
Content protection application CONTENT_PROT_APP 1 R 16 0h
File-format group FILE_FORMAT_GRP 1 R/W 15 0h
Copy flag (OTP) COPY 1 R/W 14 0h
Permanent write protection PERM_WRITE_PROTECT 1 R/W 13 0h
Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 12 0h
File format FILE_FORMAT 2 R/W [11:10] 0h
ECC ECC 2 R/W/E [9:8] 0h
CRC CRC 7 R/W/E [7:1] –
Not used; always 1 – 1 – 0 1h

Notes: 1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. The IPEAK, max driving capability can be modified according to the actual capacitive load
on the e·MMC interface signals in the user application board, using CMD4.

CMD4 Argument Driving Capability (mA)

0x01000000 4
0x02000000 8
0x04000000 12 (default)
0x08000000 16
0x10000000 20
0x20000000 24
0x40000000 28
0x80000000 32

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ECSD Register

ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This seg-
ment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.

Table 6: ECSD Register Field Parameters

Size
(Bytes Cell ECSD ECSD
Name Field ) Type1 Bytes Value
Properties Segment
Reserved2 – 7 – [511:505] –
Supported command sets S_CMD_SET 1 R 504 1h
HPI features HPI_FEATURES 1 R 503 3h
Background operations sup- BKOPS_SUPPORT 1 R 502 1h
port
Reserved – 255 – [501:247] –
Background operations status BKOPS_STATUS 1 R 246 0h
Number of correctly program- CORRECTLY_PRG_ 4 R [245:242] –
med sectors SECTORS_NUM
First initialization time after INI_TIMEOUT_PA 4GB 1 R 241 F2h
partitioning 8GB F4h
(first CMD1 to device ready)
16GB F6h
32GB FFh
Reserved – 1 – 240 –
Power class for 52 MHz, DDR at PWR_CL_DDR_52_360 1 R 239 0h
3.6V3
Power class for 52 MHz, DDR at PWR_CL_DDR_52_195 1 R 238 0h
1.95V3
Reserved – 2 – [237:236] –
Minimum write performance MIN_PERF_DDR_W_8_52 1 R 235 0h
for 8-bit at 52 MHz in DDR
mode
Minimum read performance MIN_PERF_DDR_R_8_52 1 R 234 0h
for 8-bit at 52 MHz in DDR
mode
Reserved – 1 – 233 –
TRIM multiplier TRIM_MULT 4GB, 1 R 232 06h
8GB
16GB, 0Fh
32GB
Secure feature support SEC_FEATURE_SUPPORT 1 R 231 15h

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ECSD Register

Table 6: ECSD Register Field Parameters (Continued)

Size
(Bytes Cell ECSD ECSD
Name Field ) Type1 Bytes Value
SECURE ERASE multiplier SEC_ERASE_MUL 4GB, 1 R 230 02h
T 8GB
16GB, 06h
32GB
SECURE TRIM multiplier SEC_TRIM_MULT 4GB, 1 R 229 03h
8GB
16GB, 09h
32GB
Boot information BOOT_INFO 1 R 228 7h
Reserved – 1 – 227 –
Boot partition size BOOT_SIZE_MUL 1 R 226 80h
T
Access size ACC_SIZE 4GB 1 R 225 05h
8GB 06h
16GB, 07h
32GB
High-capacity erase unit size HC_ERASE_GRP_S 4GB 1 R 224 04h
IZE 8GB 08h
16GB, 10h
32GB
High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R 223 01h
Reliable write-sector count REL_WR_SEC_C 1 R 222 01h
High-capacity write protect HC_WP_GRP_SIZE 4GB, 1 R 221 02h
group size 8GB,
16GB
32GB 04h
Sleep current (VCC) S_C_VCC 1 R 220 08h
Sleep current (VCCQ) S_C_VCCQ 1 R 219 08h
Reserved – 1 – 218 –
Sleep/awake timeout S_A_TIMEOUT 1 R 217 10h
Reserved – 1 – 216 –
Sector count SEC_COUNT 4GB 4 R [215:212] 00734000h
8GB 00E88000h
16GB 01D30000h
32GB 03B20000h
Reserved – 1 – 211 –
Minimum write performance MIN_PERF_W_8_52 1 R 210 08h
for 8-bit at 52 MHz

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ECSD Register

Table 6: ECSD Register Field Parameters (Continued)

Size
(Bytes Cell ECSD ECSD
Name Field ) Type1 Bytes Value
Minimum read performance MIN_PERF_R_8_52 1 R 209 08h
for 8-bit at 52 MHz
Minimum write performance MIN_PERF_W_8_26_4_52 1 R 208 08h
for 8-bit at 26 MHz and 4-bit at
52 MHz
Minimum read performance MIN_PERF_R_8_26_4_52 1 R 207 08h
for 8-bit at 26 MHz and 4-bit at
52 MHz
Minimum write performance MIN_PERF_W_4_26 1 R 206 08h
for 4-bit at 26 MHz
Minimum read performance MIN_PERF_R_4_26 1 R 205 08h
for 4-bit at 26 MHz
Reserved – 1 – 204 –
Power class for 26 MHz at PWR_CL_26_360 1 R 203 00h
3.6V3
Power class for 52 MHz at PWR_CL_52_360 1 R 202 00h
3.6V3
Power class for 26 MHz at PWR_CL_26_195 1 R 201 00h
1.95V3
Power class for 52 MHz at PWR_CL_52_195 1 R 200 00h
1.95V3
Partition switching timing PARTITION_SWITCH_TIME 1 R 199 1h
Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME 1 R 198 02h
Reserved – 1 – 197 –
Card type CARD_TYPE 1 R 196 07h
Reserved – 1 – 195 –
CSD structure version CSD_STRUCTURE 1 R 194 2h
Reserved – 1 – 193 –
Extended CSD revision EXT_CSD_REV 1 R 192 5h
Modes Segment
Command set CMD_SET 1 R/W/E_ 191 0h
P
Reserved – 1 – 190 –
Command set revision CMD_SET_REV 1 R 189 0h
Reserved – 1 – 188 –
Power class POWER_CLASS 1 R/W/E_ 187 0h
P
Reserved – 1 – 186 –

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ECSD Register

Table 6: ECSD Register Field Parameters (Continued)

Size
(Bytes Cell ECSD ECSD
Name Field ) Type1 Bytes Value
High-speed interface timing HS_TIMING 1 R/W/E_ 185 0h
P
Reserved – 1 – 184 –
Bus width mode BUS_WIDTH 1 W/E_P 183 0h
Reserved – 1 – 182 –
Erased memory content ERASED_MEM_CONT 1 R 181 0h
Reserved – 1 – 180 –
Partition configuration PARTITION_CONFIG 1 R/W/E, 179 0h
R/W/E_
P
Boot configuration protection BOOT_CONFIG_PROT 1 R/W, 178 0h
R/W/C_
P
Boot bus width BOOT_BUS_WIDTH 1 R/W/E 177 0h
Reserved – 1 – 176 –
High-density erase group defi- ERASE_GROUP_DEF 1 R/W/E_ 175 00h
nition P
Reserved – 1 – 174 –
Boot area write protection reg- BOOT_WP 1 R/W, 173 0h
ister R/W/C_
P
Reserved – 1 – 172 –
User write protection register USER_WP 1 R/W, 171 0h
R/W/
C_P,
R/W/E_
P
Reserved – 1 – 170 –
Firmware configuration FW_CONFIG 1 R/W 169 0h
RPMB size RPMB_SIZE_MULT 1 R 168 1h
Write reliability setting regis- WR_REL_SET 1 R/W 167 00h4
ter3
Write reliability parameter reg- WR_REL_PARAM 1 R 166 05h
ister
Reserved – 1 – 165 –
Manually start background op- BKOPS_START 1 W/E_P 164 –
erations
Enable background operations BKOPS_EN 1 R/W 163 0h
handshake
Hardware reset function RST_n_FUNCTION 1 R/W 162 0h

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ECSD Register

Table 6: ECSD Register Field Parameters (Continued)

Size
(Bytes Cell ECSD ECSD
Name Field ) Type1 Bytes Value
HPI management HPI_MGMT 1 R/W/E_ 161 0h
P
Partitioning support PARTITIONING_SUPPORT 1 R 160 3h
Maximum enhanced area size MAX_ENH_SIZE_ 4GB 3 R [159:157] 0001CDh
MULT 8GB 0001D1h
16GB 0001D3h
32GB 0001D9h
Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W 156 0h
Partitioning setting PARTITION_SETTING_COMPLETED 1 R/W 155 0h
General-purpose partition size GP_SIZE_MULT 12 R/W [154:143] 0h
Enhanced user data area size ENH_SIZE_MULT 3 R/W [142:140] 0h
Enhanced user data start ad- ENH_START_ADDR 4 R/W [139:136] 0h
dress
Reserved – 1 – 135 –
Bad block management mode SEC_BAD_BLK_MGMNT 1 R/W 134 0h
Reserved – 134 – [133:0] –

Notes: 1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. Micron has tested power failure under best application knowledge conditions with posi-
tive results. Customers may request a dedicated test for their specific application condi-
tion.
4. Set at 00h when shipped for optimized write performance; can be set to 1Fh to enable
protection on previously written data if power failure occurs during a WRITE operation.
This byte is one-time programmable.

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DC Electrical Specifications – Device Power

DC Electrical Specifications – Device Power

The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; V CCQ is used for the
controller and the e·MMC interface voltage.

Figure 6: Device Power Diagram

VCC
C3 C4

VCCQ
C1 C2

Core regulator
NAND NAND Flash
VDDIM control signals
C5 C6
I/O block

I/O block
NAND
MMC

CLK
Core NAND
CMD
logic block
data bus

VCCQ
DAT[7:0]

MMC controller
VCCQ

Table 7: Power Domains

Parameter Symbol Comments

Host interface VCCQ High voltage range = 3.3V (nominal)
Low voltage range = 1.8V (nominal)
Memory VCC High voltage range = 3.3V (nominal)
Internal VDDIM The internal regulator connection to an external decoupling capacitor

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DC Electrical Specifications – Device Power

Table 8: Capacitor and Resistance Specifications

Parameter Symbol Min Max Typ Units Notes

Pull-up resistance: CMD R_CMD 4.7 50 10 kΩ 1
Pull-up resistance: DAT[7:0] R_DAT 10 50 50 kΩ 1
Pull-up resistance: RST_n R_RST_n 4.7 50 50 kΩ 2
CLK/CMD/DAT[7:0] impedance 45 55 50 Ω 3
Serial resistance on CLK SR_CLK 0 47 22 Ω
VCCQ capacitor C1 2.2 4.7 2.2 µF 4
C2 0.1 0.22 0.1
VCC capacitor (≤8GB) C3 2.2 4.7 2.2 µF 5
C4 0.1 0.22 0.1
VCC capacitor (>8GB) C3 2.2 4.7 4.7 µF 5
C4 0.1 0.22 0.22
VDDIM capacitor (Creg) C5 1 4.7 1 µF 6
C6 0.1 0.1 0.1

Notes: 1. Used to prevent bus floating.

2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line
(Extended_CSD[162] = 00h).
3. Impedance match.
4. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible.
5. The coupling capacitor should be connected with VCC and VSS as closely as possible.
6. The coupling capacitor should be connected with VDDIM and VSS as closely as possible.

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Revision History

Revision History
Rev. B – 9/13
• Fixed density placement in ESCD Registers

Rev. A – 3/13
• Initial release

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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