Table of Contents

for this manuscript

An IEEE 754 Double-Precision Floating-Point

Multiplier for Denormalized and Normalized
Floating-Point Numbers
Ross Thompson James E. Stine
Air Force Research Laboratory Oklahoma State University
525 Brooks Road VLSI Computer Architecture Research Group
Rome, NY 13441 USA Department of Electrical and Computer Engineering
{stephen.thompson.37}@us.af.mil Stillwater, OK 74078 USA
{james.stine}@okstate.edu

Abstract—This paper discusses an optimized double-precision intermediate product, such that all modes reduce to truncation
floating-point multiplier that can handle both denormalized at the rounding bit position. The injection constant (INJ) is
and normalized IEEE 754 floating-point numbers. Discussions defined as:
of the optimizations are given and compared versus similar ⎧
implementations, however, the main objective is keeping com- ⎨ 0 : RZ
pliant for denormalized IEEE 754 floating-point numbers while IN J = 2−53 : RN E
still maintaining high performance operations for normalized ⎩ 2−52 − 2−104 : RI
numbers.
This only works when the product is in the range [1, 2), but
the mantissa can overflow into the range [2, 4) requiring a
I. PAPER injection correction (INJCOR) to be added into the product.
Although multiplication is straight-forward to implement, The ES algorithm provides little advice about computing the
there is still a need to preserve precision for denormal numbers. sticky, round, and carry[0] bits. Finding round and carry[0]
One particular method to handle denormalized IEEE-754 num- requires computing the carry propagate chain through all bits
bers uses injection-based rounding within its architecture [1]. in the lower path, −1 to −52, however, only the sum bit needs
While this technique in [1] is helpful for denormalized num- be generated at bit −1. Using a technique from [2], the sticky
bers, it does not completely address denormal operands and can be computed directly from the carry save format.
outputs with correct rounding within the IEEE 754 standard. To account for carry[0] carrying into the upper data path
The major contribution of this paper is that it utilizes the and the INJCOR, the technique in the ES paper uses a
injection-based rounding for multiplication and applies it cor- special increment decision, Tinc (INC in the ES paper). The
rectly to IEEE 754 normalized and denormalized numbers. equation definition in the ES paper is correct, however, we
believe there is a small mistake in the implementation logic
A. Multiplier Design I within [1]. Tinc should increment when the majority of round
(R), carry[0] (C), and Lx are high and the mantissa has
The first design produces a fully compliant IEEE 754 dou- overflowed Y 0[52] = 1 and the rounding mode is RNE. In
ble precision binary floating-point multiplier that is primarily the case of Lx = 1, R = 1, and C = 0, the logic incorrectly
designed around an injection- based rounding algorithm [1]. sets T inc = 0. The following equation correctly implements
To further improve the design additional hardware is added Tinc.
to fully support denormal operands and results. After partial ⎧
⎪ (C · R · RN E) + (L · R · RN E)
product reduction, the carry save pair is added with the ⎨ + ((L + C) · RI)
injection constant using a row of carry save adders and a T inc =
carry propagate adder. Concurrently, rounding is computed ⎩ + (C · L · (RZ + RN E))
⎪ : Y 0[53]
using the Even and Seidel (ES) fixed position injection based L·C : Y 0[53]
algorithm [1]. Finally, to support a second stage of rounding and the inexact
The Even/Seidel rounding algorithm (ES), as shown in Fig- flag, Tinx is computed so that it indicates if the current
ure 1, works by reducing the four rounding modes (RM); round rounding is not the infinitely precise answer.
⎧
to zero (RZ), round to nearest even (RNE), round up (RPI), ⎪ R+S : RZ · Y 0[53]
and round down (RNI) to a single truncation operation [1]. ⎪
⎨
R + S + (Lx ⊕ C[52]) : RZ · Y 0[53]
The process has two steps: first, RPI and RNI are reduced T inx =
⎪ R+S
⎪ : (RI + RN E) · Y 0[53]
into one of two modes, either RZ or a new mode round to ⎩
infinity (RI) using the product’s sign bit and the direction of R + S + (Lx ⊕ C[52]) : (RI + RN E) · Y 0[53]
the rounding. When the sign matches the rounding direction,
RPI and positive, or RNI and negative the rounding mode is When the exponent is less than emin (0), the product is no
RI, otherwise RZ. Second, an injection constant is added to the longer a valid IEEE 754 number. To correct this problem the

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 Table of Contents
for this manuscript

Sum[53:0] Carry[53:0] Sum[−1:−52] Carry[−1:−52] Inj[−1:−52] A[52:0] B[52:0]

HA Array Carry/Save Adder shift[7:0] Partial Product Generation

[53:0] [53:0]
Sum Carry RM
HA Array (IP + INJ) Carry out [−1:−52] [−1:−52] Partial Product
[52:0] [52:0] Lx Round Reduction
Sticky Gen
S C Calculate Sum Carry
Injection
[53:−52] [53:−52]
Compound Adder (52 bit) C[0] Round Sticky A_exponent shifter shifter
RM RM 11 11 left/right left/right
B_exponent
Sum[53:−107] Carry(53:−107)
RM
INJ[−1:−107]
fix L fix L
(ovf) (novf) Carry Save Adder (3:2)
Increment
Inexact
[53:−107] [53:−107]
Y0[53] Y1[1] Y0[11] Exponent
Compound Adder and Injection Rounding
S + C + INJ + 1 S + C + INJ Y1 Y0
Y1 Y0
[51:−1] [51:−1]
Y1[53] Y0[53]
Y0[53:1]
Tinc Tinx Y0[53]
Y1[53:1] (inc) Y1[53] Result Selection
1 0 0 1

Shift Shift Z1[0] Z0[0]

1 0 [52:0]
Z1[52:1] Z0[52:1]
1 0 Pack, Exceptions, and Special Values
final_p[0]
final_p[52:1] X[63:0] Exceptions[3:0]
final_p[52:0]

Fig. 1: Details of the first step of the rounding hardware. This Fig. 2: Block diagram of the mantissa path when shifting the
follows the design of Even and Seidel, but generates signal carry save redundant from before adding the injection constant.
Tinx for the second stage of rounding. Also, the 106 bit sum Note: the barrel shifters in the packing and unpacking modules
is segmented into two carry/save parts [53:0] and [-1:-52]. have been removed.

mantissa is shifted right such that the exponent is increased An additional optimization can be made now that the shift-
to emin. However, this presents a problem for the rounding ing occurs before adding the carry-save intermediate product.
function as the rounding position has now moved resulting In the original ES method, the mantissas need to be normalized
in incorrectly rounded product. By applying multistep gradual to ensure the rounding position is known. Moreover, this
rounding, a second stage of rounding ensures the proper new method eliminates that requirement. The unpacking pre-
position is rounded [3]. Additionally the input to the ES normalization step can be removed if the shifter is modified
method requires the inputs be normalized. Denormal operands to shift in both directions. Doing so, dramatically reduces the
are detected using a leading zero counter and then shifted to unpacking delay by eliminating a shifter and removing the
normalize. This adds delay to the critical path which will be leading zero detection from the critical path.
reduced in the next section.
C. Conclusion
B. Multiplier Design II: Fast Denormal Rounding Two multipliers have been implemented in RTL-based Ver-
Multistep gradual rounding is expensive in terms of delay ilog and verified for compliance with the IEEE 754 standard.
and area as the sticky bit must be computed twice and an Both versions, the multistep and fast architectures, have been
extra +1 adder is needed. To work around the issue, the fully verified against SoftFloat [4]. Both designs are based
injection based rounding has to be modified to support adding upon the fixed position injection constant rounding method
the injection at variable positions. A better solution uses a presented by Even and Seidel, but extend their work to provide
fixed injection constant, but shifts the intermediate product support for rounding denormal numbers [1].
such that the round bit aligns to the injection constant before
adding. This is achieved by moving the barrel shifter from R EFERENCES
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product reduction and final carry-propagate addition. Shifting for IEEE floating-point multiplication,” IEEE Transactions on Comput-
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first, it denormalizes the mantissa in the event of an exponent [2] R. Yu and G. Zyner, “167 MHz radix-4 floating point multiplier,” in
below emin and second, it aligns the mantissa to the correct Proceedings of the 12th Symposium on Computer Arithmetic, 1995, pp.
rounding position. 149–154.
[3] C. Lee, “Multistep gradual rounding,” IEEE Transactions on Computers,
In the previous multiplier, the packing (denormalizing) vol. 38, no. 4, pp. 595–600, Apr 1989.
shifter needed to shift up to 54 bits to completely underflow a [4] J. Hauser, “The SoftFloat and TestFloat Validation Suite for Binary
result. Because the shift now occurs prior to overflow detection Floating-Point Arithmetic,” University of California, Berkeley, Tech.
(mantissa [2,4)) the shifter will need a maximum shift of 55. Rep., 1999, available at http://www.jhauser.us/arithmetic/TestFloat.html.

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