IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Design Of Vedic IEEE 754 Floating Point

Multiplier
Soumya Havaldar, K S Gurumurthy

II. LITERATURE REVIEW

Abstract - Floating point number can co-occurrently develop a Paldurai. K and Dr. K. Hariharan [1] designed a FPGA
prominent range of numbers and a high level of precision.
Implementation of Delay Optimized Single Precision Floating
Multiplication of floating point numbers found extensive use in
wider range of technological and commercial calculations. It is point multiplier which shows an improvement in
needed to implement faster multipliers involving limited area and multiplication speed by 21.7% when compared to
consuming reduced power. An IEEE-754 format established conventional multiplier. Irine Padma B. T et al [2] proposed a
multiplier applying Vedic Urdhva - Tiryagbhyam mathematics Pipelined Floating point multiplier based on Vedic
will be cultivated to cover both single precision and double Multiplication technique where the LUTs used are less in
precision format floating point numbers in the paper. This paper number which implies reduced hardware requirement, thereby
proposes a floating point multiplier which manages overflow, reducing the power consumption. Sai Siva Teja et al [3]
underflow and rounding. The proposed and conventional floating designed a FPGA implementation of low-area floating point
point multipliers based on Vedic mathematics would be coded in
multiplier using Vedic Nikhilam Sutra, here the area has been
Verilog, Synthesized and Simulated using ISE Simulator. Xilinx
Virtex VI FPGA will be used for Hardware realization and reduced because of the less usage of CLBs and flip flops.
Verification. It is proposed to compare resource utilization and Priyanka Koneru et al [4] proposed Asynchronous single
timing performance of the proposed multiplier with that of precision floating point multiplier using verilog HDL, here the
existing as of now. mantissa part of floating point format is done using booth
algorithm and vedic multiplier where they showed that the
Keywords - Floating point number, IEEE 754 format, Vedic Vedic Multiplier was surpassing in terms of path delay and
mathematics, Urdhva-Triyakbhyam sutra, Verilog. area. I. V. Vaibhav et al [5] designed a VHDL implementation
I. INTRODUCTION of floating point multiplier using vedic mathematics, to obtain
the improvement in power efficiency the urdhva triyagbhyam
Floating point numbers represent real numbers in binary is implemented and they found that the components can be
format. Since computer memory is limited, you cannot store decreased which in turn reduces the complexity of the
numbers with precision up to infinity, no matter whether you hardware circuit. Ms Meenu S Ravi et al [6] proposed an
use binary fractions or decimal ones, at some point you have analysis and study of different multipliers to design floating
to truncate the number. Representing a number in floating point MAC units for digital signal processing applications;
point format has more boldness and efficiency when compared they showed here that the floating point multiplier can be run
to fixed-point representations. Fixed-point quantities are at the frequency 80 MHz when implemented on FPGA.
represented in two's complement format which is complicated
as compared to biasing the exponent part in floating point III. ARCHITECTURE OF THE SYSTEM
multiplication. These are the few issues which motivated me A. Floating Point Number - Floating point number mean the
to carry out this as my final year project and same is decimal point can be shifted to right or left of the fixed
introduced in the paper. number, hence the name floating point. The floating point
representation gives greater precision and reinforces a much
The floating point numbers can be expressed using expandable range of values compared to the fixed point
the IEEE-754 standard which defines a set of floating point representation.
data formats, single precision consisting of 32 bits and double
precision consisting of 64 bits. Xilinx Virtex VI platform B. Floating Point Representation - The IEEE-754 standard
FPGA usage for the implementation of Floating Point format can be represented in binary pattern as well as in a
numbers rather than microprocessor based configurations will decimal format. In this paper the multiplication of two binary
be the leading choice due to high speed operation, parallel floating point numbers is done. A Single Precision Floating
processing, re-programmability. This paper describes the Point Multiplier and a Double Precision Floating Point
Design of Single and Double Precision Floating Point Multiplier in IEEE-754 standard binary format is shown in the
Multiplier based on Vedic mathematics. Proposed Multiplier fig 1 and fig 2. The Single Precision Floating Point Multiplier
will be modeled using Verilog. The design is Synthesized and consists of 32 bits in which the sign bit is represented by 1 bit,
Simulated using ISE Simulator. Xilinx Virtex VI FPGA will the exponent bit is represented by 8 bits, and the mantissa bit
be used for Hardware implementation of the multiplier is of 23 bits. The Double Precision Floating Point Multiplier
algorithms. consists of 8 bytes in which the sign bit is represented by MSB
bit, the exponent bit is represented by 11bits, and the mantissa
Soumya Havaldar, VLSI Design & Embedded Systems,
Reva Institute Of Technology And Management Bangalore, India - 560064 bits are of 52 bits.
(yh.sowmya@gmail.com)

Dr. K S Gurumurthy
Dept. of Electronics & Communication, Reva Institute Of Technology And
Management Bangalore, India – 560064
Fig.1: IEEE-754 Single Precision Floating Point Pattern

978-1-5090-0774-5/16/$31.00 © 2016 IEEE

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Fig.2: IEEE-754 Double Precision Floating Point Pattern

C. Vedic Mathematics - Vedic mathematics was reorganized

from the ancient Indian scriptures (Vedas) by Swami Bharati
Krishna Tirthaji Maharaja (1884-1960) after his eight years of
research on Vedas, he came up with sixteen sutras and 13 sub-
sutras. Out of these sutras Urdhva Tiryagbhyam is used in the
paper. This sutra is simple in understanding, simple in design,
less steps are involved in calculating and uses less hardware
compared to other sutras of Vedas. A demonstration of two
decimal number multiplication using Urdhva Tiryagbhyam
sutra is shown in fig 3.
Fig.4: Floating Point Multiplier Structure

Step 1: 24 bit Mantissa multiplication

M = X1 * X2 = 1.111101001000… * 1.100101000..
= 10.11110010100100000…
= 1.011110010100100000… * 21 (normalizing)
E_M = 1+127 = 128₁₀ = 1000 0000₂

Step 2: 8 bit Exponent Addition

E = E_X1 + E_X2 + E_M – 127 (biasing)
= 133 + 130 + 128 - 127
= 137₁₀ = 10001001₂
Fig.3: Illustration of Urdhva Tiryagbhyam Sutra
Step 3: Sign bit
The 3x3 multiplication is done for the two numbers, where the
S1 XOR S2 = 0 XOR 0 = 0
solution is obtained in a single line calculation. Thus, by using
Urdhva Tiryagbhyam Sutra for binary multiplication, the steps
Step 4: Final Floating point Multiplier Result
involved in reaching the final product will be less, therefore
V = 0 10001001 01111001010010000000000
the execution time of the multiplier decreases and also
operates in a higher speed.
Hence seeing the example we can summarize the steps
IV. DESIGN METHOD FOR SINGLE AND DOUBLE PRECISION involved in an IEEE 754 Single precision floating point
FLOATING POINT MULTIPLIER multiplier as follows:
1. Multiplying the significant
A. In this paper a Single and double precision floating point
multiplier which can handle over flow, under flow and M_out = (1.Mantissa A * 1.Mantissa B)
rounding of the result are designed. Fig 4 shows the multiplier Take the bit Mantissa part, add 1 at the MSB and now it has
structure that includes the addition of exponents, 53 bits. Multiply these two Mantissa's using Vedic Multiplier
multiplication of mantissa, and sign calculation. This structure and get the result.
remains same for all precision floating point multipliers
according to the standard IEEE 754, except the biasing value, 2. Addition of Exponents
number of bits in an exponent part and mantissa part will be as E_out = (Exponent A + Exponent B – Bias)
shown in the floating point bit pattern in fig 1 and 2. Here three 11 bit numbers are added in order to calculate the
exponent by using Ripple Carry Adder.
B. Floating Point Multiplication Algorithm
Multiplication of two floating point binary digits represented 3. Sign bit Calculation
in IEEE 754 format is interpreted as: S = Sign A XOR Sign B
V = (-1) ^Sign * 2^ (exponent - bias) * 1.fraction If S is 0 it indicates the given value is positive, and if S is 1it
indicates the value as a negative number.
Let me consider one example to multiply two floating point 4. Normalization
numbers so that it will be easy to understand the steps It gives the normalized 52 bits and biased exponent, after
involved: checking the leading 1 on the 108 bit mantissa output.
Let two floating point numbers be,
X1 = 0 10000101 11110100100000000000000 5. Round up the result to fit in the available bits. And check
X2 = 0 10000010 10010100000000000000000 for bits underflow/overflow occurrence.

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

V. PROPOSED VEDIC MULTIPLIER VI. DESIGN OF EXPONENT AND SIGN BITS

Proposed design uses Urdhva - Tiryagbhyam Vedic The Exponent parts of two numbers to be multiplied are added
Multiplication technique for the implementation of the using Ripple Carry Adders as shown in fig 8.
Mantissa part of IEEE 754 Floating Point Multiplier. Here 3x3
blocks is used as the key block. For a 3 bit product the partial
multiplications and their additions of product are accessed
parallel in Urdhva - Tiryagbhyam as shown in fig 5.

Fig.8: Ripple Carry Adder

The MSB bits of two numbers which are multiplied will be

XORed to obtain Sign bit which represents whether the
product is positive or negative.

VII. SIMULATION RESULTS

The design is developed using Verilog HDL and Synthesized
in Xilinx ISE 14.6 platform. The Block diagram, RTL
schematic and the Simulation results of IEEE 754 single and
double precision floating point multipliers are shown in Fig.9,
Fig.5: Hardware implementation of 3x3 block Fig.10, Fig.11, Fig.12, Fig.13 and Fig.14.

The Vedic multiplier architecture for mantissa part for the

proposed single and double precision, 24x24 and 53x53 are
shown in Fig.6 and Fig.7. Firstly the basic block of 3x3 bit
multiplier is designed with two half adders, one full adder and
three 2-bit adders as shown in fig 4, then 6x6 block multiplier
is designed using 3x3 block, then a 12x12 block multiplier is
designed using 6x6 block, and from these 12x12 block the
required VM are designed which uses Ripple carry adder for
the final output of the Vedic Multipliers. Fig.9: Block diagram of IEEE 754 Vedic Single precision floating point
multiplier

Fig.10: Block diagram of IEEE 754 Vedic Double precision floating point
multiplier

Fig.6: Proposed Single Precision 24x24 Vedic Multiplier

Fig.13: Simulation result of IEEE 754 Vedic Single Precision Floating point
multiplier

Fig.7: Proposed Double Precision 53x53 Vedic Multiplier

Fig.14: Simulation result of IEEE 754 Vedic Double Precision Floating point
multiplier

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Also, Fig.15 and Fig.16 shows the Simulation results of the

24x24 and 53x53 blocks Mantissa part of the IEEE 754 Single
precision and Double precision floating point number Urdhva
– Tiryagbhyam Vedic multiplier.

Fig.15: Simulation result of 24x24 Vedic Multiplier

Fig.11: RTL schematic of IEEE 754 Vedic Single Precision Floating point
multiplier

Fig.16: Simulation result of 53x53 Vedic Multiplier

The Device Utilization Summary and Timing Details of IEEE

754 Single and Double precision floating multiplier on Virtex
VI FPGA are shown in Table 1.a, Table 1.b, and Table 2
respectively.

Table 1.a: Device Utilization Summary for SP

Logic utilization Previous design Used
No. of Slice 1018 / 2400 705 / 465600
LUTs (42%) (1%)
No. of bonded 96 / 102 (94%) 96 / 240 (40%)
IOBs
Table 1.b: Device Utilization Summary for DP
Logic utilization Used Available Utilization
No. of slices LUTs 5153 204000 2%
No. of bonded IOBs 192 600 32%
Table 2: Timing Constraints
Delay Previous design Proposed design
SP FPM 49.497 ns 21.823 ns
DP FPM - 45.169 ns

VIII. SCOPE FOR FUTURE WORK

The different Vedic sutras can be used to develop a mantissa
part. Also the design can be extended to the next format of 128 .
bits for designing floating point multiplier. .

IX. CONCLUSION
The paper proposes a floating point multiplier that supports
the IEEE 754 Single and Double Precision Floating Point
standard. The design concludes that use of Urdhva
Tiryagbhyam Vedic Multiplier gives the complete
multiplication calculation in one line, hence occupies less
space which implies reduction in area. Also hardware
components used are less and Operating speed is high due to
crosswise and vertical calculation hence reduces complexity.

Fig.11: RTL schematic of IEEE 754 Vedic Double Precision Floating point
multiplier

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

REFERENCES
[1] Paldurai.K and Dr.K.Hariharan "FPGA Implementation of Delay
Optimized Single Precision Floating point Multiplier“, 2015 International
Conference on Advanced Computing and Communication Systems (ICACCS-
2015), Jan. 05-07-2015, Coimbatore, INDIA.

[2] Irine Padma B.T and Suchitra. K, “Pipelined Floating Point Multiplier
Based On Vedic Multiplication Technique,” International Journal of
Innovative Research in Science, Engineering and Technology (IJIRSET),
ISSN: 2347-6710, Volume-3, Special Issue -5, July 2014.

[3] R. Sai Siva Teja and A. Madhusudhan,”FPGA Implementation of Low-

Area Floating Point Multiplier Using Vedic Mathematics”, International
Journal of Emerging Technology and Advanced Engineering (IJETAE),
Volume-3, Issue -12, December 2013, pp.362-366.

[4] Priyanka Koneru, Tinnanti Sreenivasu,and Addanki Purna Ramesh,

“Asynchronous Single Precision Floating Point Multiplier Using Verilog
HDL,” International Journal of Advanced Research in Electronics and
Communication Engineering (IJARECE), ISSN:2278-909X,Volume-2,Issue -
11, November 2014, pp.885-887.

[5] I.V.Vaibhav, K.V.Saicharan, B.Sravanthi and D.Srinivasulu, “VHDL

Implementation of Floating Point Multiplier using Vedic Mathematics”,
International Conference on Electrical, Electronics and Communications
(ICEEC) , ISBN-978-93-81693-66-03 , June 2014 pp.110-115.

[6] Ms. Meenu S.Ravi and Mr. Ajit Saraf, “Analysis and study of different
multipliers to design floating point MAC units for digital signal processing
applications”, International Journal of Research in Advent Technology,
(IJRAT), ISSN:2321-9637,Volume-2,Issue-3, March 2014, pp.264-267.

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