EMBEDDED SYSTEMS

- LECTURE 8: FPGAS / INTRODUCTION TO VERILOG

Dr. Moheb Mekhail

19.11.2023
Content today

• Programmable Logic Device (CPLD)

• Field Programmable Gate Array (FPGA)
• Basic Architecture of FPGAs
• Introduction to Verilog

Dr. Moheb Mekhail

Quiz 2

• Next week in lecture

• 26.11.2023 at 10:15
• 30 minutes
• After Quiz: lecture till end of slot 2
• Lecture today not included
• Content: FreeRTOS, PIC, Verilog

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Programmable Logic Array (PLA)

Both Arrays:
the AND Array and
the OR Array
are programmable

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Overview: PLA / PAL

Technology AND Array OR Array

Simple PLD fixed programmable

Programmable Logic programmable programmable

Array (PLA)
Programmable Array programmable fixed
Logic (PAL)

PLAs and PALs are non-volatile memories

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Complex Programmable Logic Device (CPLD)

• Complex Programmable Logic Devices (CPLDs) is a combination of a

fully programmable AND/OR array and a bank of macrocells.
• The AND/OR array is reprogrammable and can perform a multitude of logic
functions.
• Macrocells are functional blocks that perform combinatorial or sequential logic
along with feedback paths.
• CPLDs use electrically erasable technology.
• The devices are in-system programmable (on PCB) using software.
• CPLDs are available from many manufacturers, the features and the
architectures vary among the manufacturers → Mastering the operation
of CPLD requires understanding the device datasheets
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 Basic Architecture of the CPLD

• CPLD consists of multiple

programmable logic devices
(PLDs). The PLDs are called
Logic Array Blocks (LABs) or
Programmable Array Logic
(PAL) blocks.
• The number of LABs in CPLD is
specified in the datasheets of
device manufacturers. Four
LABs are shown here

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Basic Architecture of the CPLD

• Logic Array Blocks (LABs) are fabricated on a single chip and the LABs
are interconnected by a programmable switch structure.
• The switch structure is called switch matrix or Programmable Interconnect
Array (PIA). User inputs to CPLD are routed through switch matrix to
LABs. The outputs of LABs are the outputs of CPLD and they are also
routed through the switch matrix.
• User inputs to CPLD are the requirements of logic circuits for new designs.
• The output of CPLD is the simplified logic function.

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Example: XC9572XL CPLD from XILINX

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FPGAs

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FPGAs
• Field Programmable Gate Array (FPGA) has higher logic density than
CPLD.
• Two types of FPGAs are available.
• Re-programmable devices using Static Random Access Memory (SRAM)
technology (more popular)
• One-time programmable devices using anti-fuse technology.
• An external memory device such as Flash memory chip is required to
support the functioning of FPGA. The configuration data of FPGA is
stored in the external memory device.
• The output of FPGA could be combinational or registered type using
flip-flops.
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FPGA versus CLPD
Both are programmable digital logic chips and are made by the same
companies. But they have different characteristics.
FPGA CLPD
FPGAs can contain large digital designs CPLDs can contain small designs only
FPGAs are "fine-grain" devices - that means CPLDs are "coarse-grain" devices - they
that they contain a lot (up to 100k) of tiny contain max few 100's large blocks of
blocks of logic with flip-flops. logic with flip-flops.
FPGAs are RAM based - they need to be CPLDs are EEPROM based - they are
"downloaded" (configured) at each power- active at power-up (i.e. as long as they've
up. been programmed at least once...).
Have special routing resources to implement Have no special resources
efficiently arithmetic functions (binary
counters, adders, comparators...).
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Basic Architecture of FPGAs

I/O block

Configurable logic block (CLB)”

Programmable interconnect

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CLBs
Each CLB contains several programmable logic blocks. Each logic contains combinational
and sequential hardware. Look-Up Tables (LUTs) for Combinational hardware and flip-flops
are the components of logic blocks.

Programmable
Example: 2-LUT for “AND”
Latch Input 1 Input 2 Output
6-Input 0 0 0
Look-Up
0 1 0
Table
1 0 0
FF
1 1 1

Sequential circuit
LUT construction
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How to implement Logic functions using LUTs?
• LUT with k inputs could be programmed to implement any Boolean function
with k variables and it requires 2k SRAM bits.
• To implement a LUT with k inputs use a 2k “:1 Multiplexer

Example:
• assume number of inputs = k = 3
• → 2k = 8
• → use 8:1 MUX

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Programming FPGAs
• FPGA configuration is described using a hardware description language
(HDL)
• A HDL language is used for description, simulating and testing before
synthesis
• When the description is verified, tools to translate the design into real
hardware (gates and wires) are used.
• Each FPGA manufacturer (such as Altera and Xilinix) has its own tools
for simulating and translating into Hardware
• Most common HDL languages are VHDL or Verilog.

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FPGAs and CPUs
• CPUs are highly flexible, but their underlying hardware is fixed. Once a
CPU is manufactured the hardware cannot be changed.
• CPU relies on software to tell it which specific operation (arithmetic
function) to perform, on which data in memory.
• CPUs can generally only execute one instruction at a time.
• FPGAs in contrast can process massive amounts of data in parallel.
• it’s not uncommon to see a 20X performance improvement vs. a CPU
implementation of functions that can be highly parallelized.

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FPGA / CPU / GPU
• GPUs address a major drawback of CPUs – the ability to process a
large amount of data in parallel and can operate on very wide data
sets.
• Fundamentally, GPUs are CPU-like because they have fixed hardware
and operate using software instructions. A single instruction could
process a thousand pieces of data or more, making them suitable for
specific domains such as graphics acceleration, high performance
computing, video processing, certain forms of machine learning, and
more.
• Fundamentally, however, a GPU’s basic architecture and data flow are
fixed prior to manufacturing.

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FPGAs and Hardware Acceleration
• The architecture of FPGAs makes them an efficient solution for hardware
acceleration. Devices such as ASICs and GPUs use an antiquated
method of jumping between programming and memory.
• Unlike ASICs and GPUs, FPGAs don’t need to jump between memory
and programming, which makes the process of storing and retrieving
data more efficient.
• That flexibility can help offload energy-consuming tasks to one or
several FPGAs from a conventional CPU or another device.
• since FPGAs can be reprogrammed, you can easily implement upgrades
and adjustments to a hardware acceleration system.

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HDL Languages
Name Description
Verilog One of the most widely used, supports also analog design
VHDL (VHSIC HDL) One of the most widely used, supports also analog design
CUPL (Compiler for Universal a proprietary language from Logical Devices, Inc.
Programmable Logic)
SystemVerilog a superset of Verilog, with enhancements to address system-
level design and verification
TL-Verilog (Transaction-Level An extension of Verilog/SystemVerilog with constructs for
Verilog) pipelines and transactions.
AHDL (Altera Hardware a proprietary language from Altera
Description Language )
ABEL (Advanced Boolean Obsolete HDL made by Data I/O Corporation
Expression Language)

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HDL languages
• VHDL is a language that enables designers to describe digital systems
using a range of abstraction levels, from the low-level transistor and
gate levels up to complex hierarchical systems.
• VHDL was developed in the 1980s by the U.S. Department of Defense
and was for long time the dominating HDL
• Verilog is developed later and became popular, but still VHDL remains
a widely used HDL
• Today both Verilog and VHDL are widely used in digital circuit design
and verification.

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Verilog: levels of abstraction.
Verilog supports a design at three are:
• Behavioral level: describes a system by concurrent algorithms
(Behavioural). Every algorithm is sequential, which means it consists of a
set of instructions that are executed one by one. Functions, tasks and
blocks are the main element
• Register-transfer level: specify the characteristics of a circuit using
operations and the transfer of data between the registers. Modern
definition of an RTL code is "Any code that is synthesizable is called RTL
code".
• Gate level: the characteristics of a system are described by logical links
and their timing properties. All signals are discrete signals. They can
only have definite logical values (`0', `1', `X', `Z`).
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Verilog: Basics
• Verilog is case-sensitive. “a” and “A” differ!
• Most of the syntax and concept is similar to C language.
• A Verilog file is saved with a “.v” extension.
• Comments: There are two forms to represent the comments
// this is a comment
/* this is also a comment */

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Verilog: Basics
• Numbers: can be presented in binary, octal, decimal or hexadecimal
Negative numbers are represented in 2’s compliment numbers. Verilog
allows integers, real numbers and signed & unsigned numbers.
• Syntax: <size>’ <base> <number>
• Size: decimal value specifying the number of bits to represent a number.
• Base: base represents the format of the number. It can be decimal (d or
D), hexadecimal (h or H), octal (o or O), binary (b or B)
• Number: specifying number is chosen base format.
• 4'b1011; // 4-bit binary number indicates value 11 in binary
4'd11; // 4-bit number specified in decimal with value 11.
4'hB; //4-bit number specified in hex, value=11 in decimal.
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Verilog: Data Types
• Value Set: 0, 1, X (unknown/don’t care value), Z (high impedance value)
• Nets (wire)
• Registers (reg)
• Input, Output, Inout
• Integers (integer)
• Time (time)
• Parameter

▪ Arrays (Eg: wire temp[0:5][0:2])

▪ Strings (Eg: reg 8*[3:1]str = “Verilog”)
▪ Vectors (group of bits, can be reg or wire)
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Data Types: Value Set
Verilog consists of, mainly, four basic values. All Verilog data types, which are
used in Verilog store these values −

• 0 (logic zero, or false condition)

• 1 (logic one, or true condition)

• x (unknown logic value)

• z (high impedance state)

Use of x and z is very limited for synthesis.

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Data Types: Wire
A wire is used to represent a physical wire in a circuit and it is used for
connection of gates or modules. The value of a wire can only be read and not
assigned in a function or block. A wire cannot store value but is always driven
by a continuous assignment statement or by connecting wire to output of a
gate/module. Other specific types of wires are −

Wand (wired-AND) − here value of Wand is dependent on logical AND of all

the device drivers connected to it.

Wor (wired-OR) − here value of a Wor is dependent on logical OR of all the

device drivers connected to it.

Tri (three-state) − here all drivers connected to a tri must be z, except only one
(which determines value of tri).
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Data Types: Wire, example
Wire [msb:lsb] wire_variable_list;
Wire c // simple wire
Wand d;

Assign d = a; // value of d is the logical AND of

Assign d = b; // a and b
Wire [9:0] A; // a cable (vector) of 10 wires.

Wand [msb:lsb] wand_variable_list;

Wor [msb:lsb] wor_variable_list;
Tri [msb:lsb] tri_variable_list;

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Data Types: Register
A reg (register) is a data object, which is holding the value from one
procedural assignment to next one and are used only in different functions
and procedural blocks. A reg is a simple Verilog, variable-type register
and can’t imply a physical register.

Examples:
reg c; // single 1-bit register variable
reg [5:0] gem; // a 6-bit vector;
reg [6:0] d, e; // two 7-bit variables

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Input, Output, Inout
These keywords are used to declare input, output and bidirectional ports of a
task or module. Here input and inout ports, which are of wire type and output
port is configured to be of wire, reg, wand, wor or tri type. Always, default is
wire type.
Example:
Module sample(a, c, b, d);
Input c; // An input where wire is used.

Output a, b; // Two outputs where wire is used.

Output [2:0] d; /* A three-bit output.*/
reg [1:0] a; // The above ‘a’ port is for declaration in reg.

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Integer
• Integers are used in general-purpose variables. They are used mainly in
loops-indicies, constants, and parameters.
• They are of ‘reg’ type data type. They store data as signed numbers
whereas explicitly declared reg types store them as an unsigned data.
If the integer is not defined at the time of compiling, then the default
size would be 32 bits.

Example:
Integer c; // single 32-bit integer
Assign d=63; // 63 defaults to a 7-bit variable.

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Supply0, Supply1
Supply0 define wires tied to logic 0 (ground) and supply1 define wires
tied to logic 1 (power).

Example:
supply0 logic_0_wires;
supply0 gnd1; // equivalent to a wire assigned as 0

supply1 logic_1_wires;
supply1 c, s;

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Time
Time is a 64-bit quantity that can be used in conjunction with the $time
system task to hold simulation time. Time is not supported for synthesis and
hence is used only for simulation purposes.

Example:
time time_variable_list;
time c;
c = $time; // c = current simulation time

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Parameter
A parameter is defining a constant which can be set when you use a
module, which allows customization of module during the instantiation
process.

Example:
Parameter add = 3’b010, sub = 2’b11;
Parameter n = 3;
Parameter [2:0] param2 = 3’b110;

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Verilog: operators
• Operators are special characters used to put conditions or to operate the
variables. There are one, two and sometimes three characters used to
perform operations on variables.

Ex. >, +, ~, &! =

• Operators in Verilog are the same as in C language. The additional ones
that are different and important are:
➢Concatenation: {A, B, C} will result in concatenation of values of A, B and C
➢Replication: {2{A}} will result in the concatenation of values of A twice ie.
replication of the value of A.

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Operators, examples
Logical AND
wire[7:0] a, b, c; // a, b and c are multibit variables.
reg x;

if ((a == b) && (c)) x = 1; //x = 1 if a equals b, and c is nonzero.

else x = !a; // x =0 if a is anything but zero.

reduction AND
Module chk_zero (x, z);
Input [2:0] x;
Output z;
Assign z = & x; // Reduction AND
End module
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Concatenation Operator
The concatenation operator combines two or more operands to form a larger
vector.
The operator included in Concatenation operation is − { }(concatenation)

Example:

wire [1:0] a, h; wire [2:0] x; wire [3;0] y, Z;

assign x = {1’b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0]
assign b = {a, h}; // b[3] = a[1], b[2] = a[0], b[1] = h[1], b[0] = h[0]

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Replication Operator
The replication operator are making multiple copies of an item.
The operator used in Replication operation is − {n{item}} (n fold replication
of an item)

Example:
Wire [1:0] a, f; wire [4:0] x;
Assign x = {2{1’f0}, a}; // Equivalent to x = {0,0,a }
Assign y = {2{a}, 3{f}}; //Equivalent to y = {a,a,f,f}

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Verilog: Identifiers
• Identifiers are names given to objects that can be referred to in a
design.
• An identifier can contain alphabets (a-z, A-Z), digits (0–1) and special
characters(_, $).
• An identifier must begin with an alphabet or underscore(__).
• Identifiers are case-sensitive.
• Some identifiers allow the use of any printable ASCII character. They
are called as escaped identifiers. An escaped identifier starts with a \
and ends with a white space.
• An identifier can not be a reserved keyword of the Verilog library.

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Verilog: keywords
The keywords are reserved identifiers, which contain only lowercase
letters. The user cannot redefine any of them.

Examples:
if, else, for, repeat,
and, nand, or, not
input, output, wire
join, module, wait

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Verilog: Parameters
• Parameters are used to declare constants in Verilog.
• These constants can be overridden during compilation time.
• ”defparam” keyword is used to override a parameter.

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Module
A Module is the basic building block of a Verilog code.

module sub_add(add, in1, in2, out);

input add; // defaults to wire
input [7:0] in1, in2; wire in1, in2;

output [7:0] out; reg out;

... statements ...
End module

*Note: there’s no space between “end” and “module” in “endmodule”. That’s a

common mistake!
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Continuous Assignment
• The continuous assignment in a Module is used for assigning a value on
to a wire, which is the normal assignment used at outside of always or
initial blocks.
• This assignment is done with an explicit assign statement or to assign a
value to a wire during its declaration.
• Continuous assignment are continuously executed at the time of
simulation. The order of assign statements does not affect it. If you do
any change in any of the right-hand-side inputs signal it will change a
left-hand-side output signal.
Wire [1:0] x = 2’y01; // assigned on declaration
Assign y = c | d; // using assign statement
Assign d = a & b;
/* the order of the assign statements does not matter. */
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Port Definition
The three types of ports are:
• Input (module can only receive),
• Output (module can only send) and
• Inout (module can both send and receive).

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Initial Block
• Initial block is used for one-time execution during the whole simulation.
• There may be any number of initial blocks inside a module.
• If there is more than one initial block, every block executes at 0 simulation
time.
• Initial blocks are typically used for initialization, monitoring, providing test
inputs and other operations, which must be executed only once during the
entire simulation.
• Timing control is used to provide delay
• ‘#’ followed by time value provides a delay.
• Initial block is not synthesizable, hence used for Testbench or simulation,
Initial begin
//procedural assignments;
//delay statements;
end
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Always Block
• Always block executes continuously during simulation, just like a looping
fashion.
• If there are multiple always blocks, then all blocks start at O time and execute
simultaneously.
• always block can be controlled with the help of a sensitivity list. If a
sensitivity list is not provided, then always block runs continuously.
• always block is executed whenever an event occurs on any of the variables
present in the sensitivity list.
• @ is event control directive that halts the execution of the statement until the
event occurs on any of the variables listed in the sensitivity list.
• Statements inside the always block are executed in a sequential manner

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Always Block
• Timing control is used to provide a delay in the execution of an assignment by
a specified time.
• always block is synthesizable
• always block can be used for both combinational and sequential logic design.

always [@ (senstivity_list)]
begin
//[timing control]
//procedural assignments;
end

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Blocking Assignment
• Preferred for combinational design.
• During simulation, it blocks the execution of statements until the assignment
occurs.
• Are executed one after the other in the procedural block.
• In blocking statements, the assignment occurs at the very same time
• “=”sign is used to perform blocking procedural assignment.

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Blocking Assignment
module block_test;
reg [1:0] a=2'b01, b=2'b10, c=2'b11;
initial begin
a=2'b00; b=a; c=b; // Blocking Assignments
Sdisplay(" a=%b\n, b=%b\n, c=%b\n", a,b,c);
end
endmodule

OUTPUT:
a=00
b=00
c=00
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Non-Blocking Assignment
• Non-blocking statements do not block the execution of other statements.
• In case of non-blocking, the assignment is scheduled to occur at the end of the
current simulation time or at the end of the procedure block.
• Verilog recommends using non-blocking statements to model sequential
circuits.
• ”<=” sign is used for assignment.

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Non-Blocking Assignment
module block_test;
reg [1:0] a=2'b01, b=2'b10, c=2'b11;
initial begin
a<=2b00; b<=a; c<=b; // Non- Blocking Assignments
Sdisplay(" a=%b\n, b=%b\n, c=%b\n", a,b,c);
end
endmodule

OUTPUT:
a=01
b=10
c=11
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