UVM

INTRODUCTION

◼ UVM is the Universal Verification Methodology

An Accellera standard to define a standard verification
methodology and base class library
Supported by Cadence, Mentor, and Synopsys

◼ Combined, these features provide a powerful, flexible

technology and methodology to help you create scalable,
reusable, and interoperable testbench
TESTBENCH ARCHITECTURE
Overview(1)
 TESTBENCH ARCHITECTURE
Overview(2)

◼ Test instantiates the environment and modifies the

environment on a testcase

◼ Agent, coverage, and scoreboard should be encapsulate

in an environment

◼ Sequencer, driver, and monitor associated with an

interface should be encapsulated as an agent for that
interface
TESTBENCH ARCHITECTURE
Agent(1)
 TESTBENCH ARCHITECTURE
Agent(2)
◼ Most DUTs have a number of different signal interface, each
of which have their own protocol

◼ The UVM agent collects together a group of uvm_components

focused around a specific pin-level interface

◼ The content of an agent will usually include:

 A sequence_item: is used to define what pin level activity
 A driver: drive pin of DUT
 A monitor: observer pin level activity and send to scoreboard
 A sequencer: route sequence_item from a sequence to a driver
 A configuration: used to pass information to the agent which affects
what it does and how it is build and connected
 TESTBENCH ARCHITECTURE
Example(1)

class uart_test extends uvm_test;

`uvm_component_utils(uart_test)

//the environment class

uart_env m_env;
//configuration objects
apb_agent_config m_apb_config;
uart_agent_config m_uart_config;
uart_env_config m_env_config

function new(string name=“uart_tesst”, uvm_component parent=null );

super.new(name, parent);
endfunction
…
endclass
 TESTBENCH ARCHITECTURE
Example(2)

class uart_env extends uvm_env;

`uvm_component_utils(uart_env)

apb_agent m_apb_agent;
uart_agent m_uart_agent;
uart_env_config m_cfg;
uart_scoreboard m_scoreboard;
uart_virtual_sequence m_v_sqr;

function new(string name=”uart_env”, uvm_component parent=null);

super.new(name, parent);
endfunction

…
endclass
 TESTBENCH ARCHITECTURE
Example(3)
class apb_agent extends uvm_agent;
`uvm_component_utils(apb_agent)

apb_driver m_driver;
apb_monitor m_monitor;
apb_sequencer m_sequencer;
apb_agent_config m_cfg;

function new(string name=”apb_agent”, uvm_component parent=null);

super.new(name, parent);
endfunction
…
endclass
UVM CLASS LIBRARY
Overview
UVM CLASS LIBRARY
Using the UVM Class Library
 UVM CLASS LIBRARY
Example(1)

class apb_driver extends uvm_driver #(apb_seq_item);

`uvm_component_utils(apb_driver)

//interface
virtual apb_if APB;
//config apb agent
apb_agent_config m_cfg;

function new(string name=“apb_driver”, uvm_component parent=null);

super.new(name, parent);
endfunction
…
endclass
 UVM CLASS LIBRARY
Example(2)

class apb_monitor extends uvm_monitor;

`uvm_component_utils(apb_monitor)

//interface
virtual apb_if APB;
//config apb agent
apb_agent_config m_cfg;

function new(string new=“name”, uvm_component parent=null);

super.new();
endfunction

…
endclass
 UVM CLASS LIBRARY
Example(3)
class apb_sequencer extends uvm_sequencer #(apb_seq_item);
`uvm_component_utils(apb_sequencer)

function new(string name=“apb_sequencer”,uvm_component parent= null);

super.new(name, parent);
endfunction

…
endclass
UVM_COMPONENT PHASE
Overview
 UVM_COMPONENT PHASE
Component phase description(1)

◼ 1. Build phase: the build phases are executed at the start

of the UVM testbench simulation and their purpose is to
construct, configure and connect the testbench component
hierarchy. All the build phase methods are function and
therefore execute in zero simulation time
Build: construct the testbench component hierarchy from the top
down
Connect: is used to make TLM connections between
components
End_of_elaboration: is used to make any final adjustments to
the structure, configuration or connectivity of the testbench
before simulation starts
 UVM_COMPONENT PHASE
Component phase description (2)

◼ 2. Run time phase: the testbench stimulus is generated

and executed during the run time phase. The UVM
executes the run phase and the phases pre_set through to
post_shutdown in parallel
Start_of_simulation: it intended to be used for display
testbench topology or configuration information

Run: is used for the stimulus generation and checking

activities of the testbench. The run phase is implemented as a
task and all uvm_component run tasks are executed in parallel.
Transactors such as drivers and monitors will nearly always
use phase
 UVM_COMPONENT PHASE
Component phase description(3)

◼ 3. Clean up phase: are used to extract information from

scoreboard and functional coverage to determine
whether the testcase has passed or reached its coverage
goals. The clean up phases are implemented as function
and therefore take zero time to execute
Extract: is used to retrieve and process information from
scoreboard and functional coverage
Check: is used to check that the DUT behaved correctly
Report: is used to display the results of the simulation or write
the results to file
Final: is used to complete any other outstanding actions that
the testbench has not already completed
 UVM_COMPONENT PHASE
Example(1)
class uart_test extends uvm_test;
…
function void build_phase(uvm_phase phase);
m_env=uart_env::type_id::create(“m_env”, this);
…
endfunction

function void start_of_simulation_phase(uvm_phase phase);

uvm_top.print_topology();
factory.print();
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this, “”);
`uvm_info(“TEST”, “HELLO WORLD”, UVM_MEDIUM)
phase.drop_objection(this, “”);
endtask
endclass
 UVM_COMPONENT PHASE
Example(2)
class apb_agent extends uvm_agent;
…
function void build_phase (uvm_phase phase);
m_driver = apb_driver::type_id::create(“m_driver”, this);
m_monitor = apb_monitor::type_id::create(“m_monitor”, this);
m_sequencer=apb_sequencer::type_id::create(“m_sequencer, this”);
endfunction

function void connect_phase(uvm_phase phase);

m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
endfunction

endclass
 UVM_COMPONENT PHASE
Example(3)
class apb_driver extends uvm_driver #(apb_seq_item);
…
function void build_phase(uvm_phase phase);
…
endfunction

task run_phase(uvm_phase phase);

apb_seq_item req;
forever begin
seq_item_port.get_next_item(req);
drive(req);
seq_item_port.item_done();
end
endtask

endclass
 TESTBENCH MODULE
Overview

◼ UVM tests are derived from uvm_test class

◼ Execution of test is done via global task run_test()

◼ This task is placed in the top level testbench module, the

top level testbench module also include
Instance DUT
Instance interfaces connected with DUT
An initial block which generates a clock and reset
Import UVM package
Enable generating file.vpd
 TESTBENCH MODULE
Example(1)
module simulation_top;
import uvm_pkg::*;
reg SystemClock, SystemReset;
wire pclk, presetn;

//instance interface
apb_if APB(pclk, presetn);
uart_if UART();

//instance DUT
uart_top dut(.pclk(pclk),
.presetn(presetn),
.penable(APB.PENBLE),
…);
 TESTBENH MODULE
Example(2)
initial begin //run testcase
run_test();
$finish;
end

initial begin //clock generation

SystemClock = 0;
forever begin
#(`simulation_cycle/2) SystemClock=~SystemClock;
end
end

endmodule
 TESTBENCH MODULE
Example(3)

interface apb_if(input PCLK, input PRESETn);

parameter PADDR_WIDTH = 32;
parameter PWDATA_WIDTH = 32;
parameter PRDATA_WIDTH = 32;

logic PWRITE;
logic PENABLE;
logic [15:0] PSEL;
logic [PADDR_WIDTH -1:0] PADDR;
logic [PWDATA_WIDTH-1:0] PWDATA;
logic [PRDATA_WIDTH-1:0] PRDATA;

endinterface
 COMPILE AND SIMULATION
Overview

◼ Compile with vcs using –ntb_opts uvm-1.1 switch

vcs -sverilog -ntb_opts uvm-1.1 test.sv

◼ Specify test to run with +UVM_TESTNAME=uart_test

simv +UVM_TESTNAME=uart_test
 COMPILE AND SIMULATION
Inner working of UVM simulation
◼ Macro registers the class in factory registry table
class uart_test extends uvm_test;
`uvm_component_utils (uart_test)
◼ UVM package creates a global instance of uvm_root class
named uvm_top
import uvm_package::*;
◼ When run_test() executes, uvm_top retrieves
+UVM_TESTNAME from register and create
a child component called uvm_test_top
initial
run_test();
 COMPILE AND SIMULATION
Parent child
◼ During execution, parent component manages children
components’ phase execution
◼ Parent-child relationships
Set up at component creation
Establishes component phasing execution order
Establishes component search path for
component configuration
◼ Phase execution order
 UVM REPORT
Overview
◼ Message:
While developing or using environments, users need to print
messages
User may want to get trace messages from a suspect component
Critical to large environment with many verification component

◼ Every UVM report has a severity and verbosity

Severity: indicates importance
Example: fatal, error, warning, info
Verbosity: indicates filter level
Example: none, low, medium, high, full, debug
 UVM REPORT
Create message
◼ Create messages with macro

◼ Example
 UVM REPORT
Controlling message verbosity
◼ UVM defines verbosity: UVM_NONE, UVM_LOW,
UVM_MEDIUM, UVM_HIGH, UVM_FULL,
UVM_DEBUG

◼ By changing the verbosity maximum, messages can be

filtered: for example, if the verbosity is set to UVM_LOW,
all messages coded with UVM_MEDIUM and higher will
not print

◼ Default verbosity is UVM_MEDIUM, to change verbosity

set with run-time switch
UART ENVIRONMENT
Overview